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https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
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vv_gulyaev |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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-- Date : Thu Jul 23 09:43:35 2020
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-- Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_stub.vhdl
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-- Design : clk_gen
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7k325tffg900-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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clk_out1 : out STD_LOGIC;
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reset : in STD_LOGIC;
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locked : out STD_LOGIC;
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clk_in1_p : in STD_LOGIC;
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clk_in1_n : in STD_LOGIC
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1_p,clk_in1_n";
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begin
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end;
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