1 |
2 |
vv_gulyaev |
|
2 |
|
|
*** Running vivado
|
3 |
|
|
with args -log clk_gen.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_gen.tcl
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
****** Vivado v2017.4 (64-bit)
|
7 |
|
|
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
|
8 |
|
|
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
9 |
|
|
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
10 |
|
|
|
11 |
|
|
source clk_gen.tcl -notrace
|
12 |
|
|
Command: synth_design -top clk_gen -part xc7k325tffg900-2 -mode out_of_context
|
13 |
|
|
Starting synth_design
|
14 |
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
|
15 |
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
|
16 |
|
|
INFO: Launching helper process for spawning children vivado processes
|
17 |
|
|
INFO: Helper process launched with PID 3376
|
18 |
|
|
---------------------------------------------------------------------------------
|
19 |
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1395.582 ; gain = 85.000 ; free physical = 669 ; free virtual = 93762
|
20 |
|
|
---------------------------------------------------------------------------------
|
21 |
|
|
INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
|
22 |
|
|
INFO: [Synth 8-638] synthesizing module 'clk_gen_clk_wiz' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
|
23 |
|
|
INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
|
24 |
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
25 |
|
|
Parameter DIFF_TERM bound to: FALSE - type: string
|
26 |
|
|
Parameter DQS_BIAS bound to: FALSE - type: string
|
27 |
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
28 |
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
29 |
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
30 |
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
31 |
|
|
INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
|
32 |
|
|
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
|
33 |
|
|
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
34 |
|
|
Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float
|
35 |
|
|
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
|
36 |
|
|
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
|
37 |
|
|
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float
|
38 |
|
|
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
|
39 |
|
|
Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float
|
40 |
|
|
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
|
41 |
|
|
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
|
42 |
|
|
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
|
43 |
|
|
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
|
44 |
|
|
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
|
45 |
|
|
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
|
46 |
|
|
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
|
47 |
|
|
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
|
48 |
|
|
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
|
49 |
|
|
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
|
50 |
|
|
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
|
51 |
|
|
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
|
52 |
|
|
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
|
53 |
|
|
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
|
54 |
|
|
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
|
55 |
|
|
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
|
56 |
|
|
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
|
57 |
|
|
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
|
58 |
|
|
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
|
59 |
|
|
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
|
60 |
|
|
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
|
61 |
|
|
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
|
62 |
|
|
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
|
63 |
|
|
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
|
64 |
|
|
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
|
65 |
|
|
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
|
66 |
|
|
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
|
67 |
|
|
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
|
68 |
|
|
Parameter COMPENSATION bound to: ZHOLD - type: string
|
69 |
|
|
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
|
70 |
|
|
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
|
71 |
|
|
Parameter IS_PSEN_INVERTED bound to: 1'b0
|
72 |
|
|
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
|
73 |
|
|
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
|
74 |
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
75 |
|
|
Parameter REF_JITTER1 bound to: 0.010000 - type: float
|
76 |
|
|
Parameter REF_JITTER2 bound to: 0.010000 - type: float
|
77 |
|
|
Parameter SS_EN bound to: FALSE - type: string
|
78 |
|
|
Parameter SS_MODE bound to: CENTER_HIGH - type: string
|
79 |
|
|
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
|
80 |
|
|
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
81 |
|
|
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
|
82 |
|
|
INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
|
83 |
|
|
INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
|
84 |
|
|
INFO: [Synth 8-256] done synthesizing module 'clk_gen_clk_wiz' (4#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
|
85 |
|
|
INFO: [Synth 8-256] done synthesizing module 'clk_gen' (5#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
|
86 |
|
|
---------------------------------------------------------------------------------
|
87 |
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1437.121 ; gain = 126.539 ; free physical = 669 ; free virtual = 93763
|
88 |
|
|
---------------------------------------------------------------------------------
|
89 |
|
|
|
90 |
|
|
Report Check Netlist:
|
91 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
92 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
93 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
94 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
95 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
96 |
|
|
---------------------------------------------------------------------------------
|
97 |
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1437.121 ; gain = 126.539 ; free physical = 667 ; free virtual = 93762
|
98 |
|
|
---------------------------------------------------------------------------------
|
99 |
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
100 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
101 |
|
|
INFO: [Device 21-403] Loading part xc7k325tffg900-2
|
102 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
103 |
|
|
|
104 |
|
|
Processing XDC Constraints
|
105 |
|
|
Initializing timing engine
|
106 |
|
|
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
|
107 |
|
|
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
|
108 |
|
|
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
|
109 |
|
|
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
|
110 |
|
|
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
|
111 |
|
|
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
|
112 |
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_gen_propImpl.xdc].
|
113 |
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/clk_gen_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
114 |
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
115 |
|
|
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
|
116 |
|
|
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
|
117 |
|
|
Completed Processing XDC Constraints
|
118 |
|
|
|
119 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
120 |
|
|
No Unisim elements were transformed.
|
121 |
|
|
|
122 |
|
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1774.355 ; gain = 0.996 ; free physical = 310 ; free virtual = 93077
|
123 |
|
|
---------------------------------------------------------------------------------
|
124 |
|
|
Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103
|
125 |
|
|
---------------------------------------------------------------------------------
|
126 |
|
|
---------------------------------------------------------------------------------
|
127 |
|
|
Start Loading Part and Timing Information
|
128 |
|
|
---------------------------------------------------------------------------------
|
129 |
|
|
Loading part: xc7k325tffg900-2
|
130 |
|
|
---------------------------------------------------------------------------------
|
131 |
|
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103
|
132 |
|
|
---------------------------------------------------------------------------------
|
133 |
|
|
---------------------------------------------------------------------------------
|
134 |
|
|
Start Applying 'set_property' XDC Constraints
|
135 |
|
|
---------------------------------------------------------------------------------
|
136 |
|
|
Applied set_property DONT_TOUCH = true for inst. (constraint file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc, line 9).
|
137 |
|
|
---------------------------------------------------------------------------------
|
138 |
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103
|
139 |
|
|
---------------------------------------------------------------------------------
|
140 |
|
|
---------------------------------------------------------------------------------
|
141 |
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 332 ; free virtual = 93102
|
142 |
|
|
---------------------------------------------------------------------------------
|
143 |
|
|
|
144 |
|
|
Report RTL Partitions:
|
145 |
|
|
+-+--------------+------------+----------+
|
146 |
|
|
| |RTL Partition |Replication |Instances |
|
147 |
|
|
+-+--------------+------------+----------+
|
148 |
|
|
+-+--------------+------------+----------+
|
149 |
|
|
---------------------------------------------------------------------------------
|
150 |
|
|
Start RTL Component Statistics
|
151 |
|
|
---------------------------------------------------------------------------------
|
152 |
|
|
Detailed RTL Component Info :
|
153 |
|
|
---------------------------------------------------------------------------------
|
154 |
|
|
Finished RTL Component Statistics
|
155 |
|
|
---------------------------------------------------------------------------------
|
156 |
|
|
---------------------------------------------------------------------------------
|
157 |
|
|
Start RTL Hierarchical Component Statistics
|
158 |
|
|
---------------------------------------------------------------------------------
|
159 |
|
|
Hierarchical RTL Component report
|
160 |
|
|
---------------------------------------------------------------------------------
|
161 |
|
|
Finished RTL Hierarchical Component Statistics
|
162 |
|
|
---------------------------------------------------------------------------------
|
163 |
|
|
---------------------------------------------------------------------------------
|
164 |
|
|
Start Part Resource Summary
|
165 |
|
|
---------------------------------------------------------------------------------
|
166 |
|
|
Part Resources:
|
167 |
|
|
DSPs: 840 (col length:140)
|
168 |
|
|
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
|
169 |
|
|
---------------------------------------------------------------------------------
|
170 |
|
|
Finished Part Resource Summary
|
171 |
|
|
---------------------------------------------------------------------------------
|
172 |
|
|
---------------------------------------------------------------------------------
|
173 |
|
|
Start Cross Boundary and Area Optimization
|
174 |
|
|
---------------------------------------------------------------------------------
|
175 |
|
|
---------------------------------------------------------------------------------
|
176 |
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 333 ; free virtual = 93102
|
177 |
|
|
---------------------------------------------------------------------------------
|
178 |
|
|
|
179 |
|
|
Report RTL Partitions:
|
180 |
|
|
+-+--------------+------------+----------+
|
181 |
|
|
| |RTL Partition |Replication |Instances |
|
182 |
|
|
+-+--------------+------------+----------+
|
183 |
|
|
+-+--------------+------------+----------+
|
184 |
|
|
---------------------------------------------------------------------------------
|
185 |
|
|
Start Applying XDC Timing Constraints
|
186 |
|
|
---------------------------------------------------------------------------------
|
187 |
|
|
---------------------------------------------------------------------------------
|
188 |
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 572 ; free virtual = 93068
|
189 |
|
|
---------------------------------------------------------------------------------
|
190 |
|
|
---------------------------------------------------------------------------------
|
191 |
|
|
Start Timing Optimization
|
192 |
|
|
---------------------------------------------------------------------------------
|
193 |
|
|
---------------------------------------------------------------------------------
|
194 |
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 572 ; free virtual = 93068
|
195 |
|
|
---------------------------------------------------------------------------------
|
196 |
|
|
|
197 |
|
|
Report RTL Partitions:
|
198 |
|
|
+-+--------------+------------+----------+
|
199 |
|
|
| |RTL Partition |Replication |Instances |
|
200 |
|
|
+-+--------------+------------+----------+
|
201 |
|
|
+-+--------------+------------+----------+
|
202 |
|
|
---------------------------------------------------------------------------------
|
203 |
|
|
Start Technology Mapping
|
204 |
|
|
---------------------------------------------------------------------------------
|
205 |
|
|
---------------------------------------------------------------------------------
|
206 |
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 578 ; free virtual = 93069
|
207 |
|
|
---------------------------------------------------------------------------------
|
208 |
|
|
|
209 |
|
|
Report RTL Partitions:
|
210 |
|
|
+-+--------------+------------+----------+
|
211 |
|
|
| |RTL Partition |Replication |Instances |
|
212 |
|
|
+-+--------------+------------+----------+
|
213 |
|
|
+-+--------------+------------+----------+
|
214 |
|
|
---------------------------------------------------------------------------------
|
215 |
|
|
Start IO Insertion
|
216 |
|
|
---------------------------------------------------------------------------------
|
217 |
|
|
---------------------------------------------------------------------------------
|
218 |
|
|
Start Flattening Before IO Insertion
|
219 |
|
|
---------------------------------------------------------------------------------
|
220 |
|
|
---------------------------------------------------------------------------------
|
221 |
|
|
Finished Flattening Before IO Insertion
|
222 |
|
|
---------------------------------------------------------------------------------
|
223 |
|
|
---------------------------------------------------------------------------------
|
224 |
|
|
Start Final Netlist Cleanup
|
225 |
|
|
---------------------------------------------------------------------------------
|
226 |
|
|
---------------------------------------------------------------------------------
|
227 |
|
|
Finished Final Netlist Cleanup
|
228 |
|
|
---------------------------------------------------------------------------------
|
229 |
|
|
---------------------------------------------------------------------------------
|
230 |
|
|
Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
231 |
|
|
---------------------------------------------------------------------------------
|
232 |
|
|
|
233 |
|
|
Report Check Netlist:
|
234 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
235 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
236 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
237 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
238 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
239 |
|
|
---------------------------------------------------------------------------------
|
240 |
|
|
Start Renaming Generated Instances
|
241 |
|
|
---------------------------------------------------------------------------------
|
242 |
|
|
---------------------------------------------------------------------------------
|
243 |
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
244 |
|
|
---------------------------------------------------------------------------------
|
245 |
|
|
|
246 |
|
|
Report RTL Partitions:
|
247 |
|
|
+-+--------------+------------+----------+
|
248 |
|
|
| |RTL Partition |Replication |Instances |
|
249 |
|
|
+-+--------------+------------+----------+
|
250 |
|
|
+-+--------------+------------+----------+
|
251 |
|
|
---------------------------------------------------------------------------------
|
252 |
|
|
Start Rebuilding User Hierarchy
|
253 |
|
|
---------------------------------------------------------------------------------
|
254 |
|
|
---------------------------------------------------------------------------------
|
255 |
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
256 |
|
|
---------------------------------------------------------------------------------
|
257 |
|
|
---------------------------------------------------------------------------------
|
258 |
|
|
Start Renaming Generated Ports
|
259 |
|
|
---------------------------------------------------------------------------------
|
260 |
|
|
---------------------------------------------------------------------------------
|
261 |
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
262 |
|
|
---------------------------------------------------------------------------------
|
263 |
|
|
---------------------------------------------------------------------------------
|
264 |
|
|
Start Handling Custom Attributes
|
265 |
|
|
---------------------------------------------------------------------------------
|
266 |
|
|
---------------------------------------------------------------------------------
|
267 |
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
268 |
|
|
---------------------------------------------------------------------------------
|
269 |
|
|
---------------------------------------------------------------------------------
|
270 |
|
|
Start Renaming Generated Nets
|
271 |
|
|
---------------------------------------------------------------------------------
|
272 |
|
|
---------------------------------------------------------------------------------
|
273 |
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
274 |
|
|
---------------------------------------------------------------------------------
|
275 |
|
|
---------------------------------------------------------------------------------
|
276 |
|
|
Start Writing Synthesis Report
|
277 |
|
|
---------------------------------------------------------------------------------
|
278 |
|
|
|
279 |
|
|
Report BlackBoxes:
|
280 |
|
|
+-+--------------+----------+
|
281 |
|
|
| |BlackBox name |Instances |
|
282 |
|
|
+-+--------------+----------+
|
283 |
|
|
+-+--------------+----------+
|
284 |
|
|
|
285 |
|
|
Report Cell Usage:
|
286 |
|
|
+------+-----------+------+
|
287 |
|
|
| |Cell |Count |
|
288 |
|
|
+------+-----------+------+
|
289 |
|
|
|1 |BUFG | 2|
|
290 |
|
|
|2 |MMCME2_ADV | 1|
|
291 |
|
|
|3 |IBUFDS | 1|
|
292 |
|
|
+------+-----------+------+
|
293 |
|
|
|
294 |
|
|
Report Instance Areas:
|
295 |
|
|
+------+---------+----------------+------+
|
296 |
|
|
| |Instance |Module |Cells |
|
297 |
|
|
+------+---------+----------------+------+
|
298 |
|
|
|1 |top | | 4|
|
299 |
|
|
|2 | inst |clk_gen_clk_wiz | 4|
|
300 |
|
|
+------+---------+----------------+------+
|
301 |
|
|
---------------------------------------------------------------------------------
|
302 |
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062
|
303 |
|
|
---------------------------------------------------------------------------------
|
304 |
|
|
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
305 |
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1774.355 ; gain = 126.539 ; free physical = 623 ; free virtual = 93114
|
306 |
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 627 ; free virtual = 93118
|
307 |
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
308 |
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
309 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
310 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
311 |
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
312 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
313 |
|
|
No Unisim elements were transformed.
|
314 |
|
|
|
315 |
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
316 |
|
|
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
317 |
|
|
synth_design completed successfully
|
318 |
|
|
synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:01:07 . Memory (MB): peak = 1774.355 ; gain = 499.598 ; free physical = 603 ; free virtual = 93094
|
319 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.
|