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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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// Date : Thu Jul 23 09:49:59 2020
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// Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
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// Command : write_verilog -force -mode synth_stub -rename_top axi_uartlite_module -prefix
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// axi_uartlite_module_ axi_uartlite_module_stub.v
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// Design : axi_uartlite_module
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7k325tffg900-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_uartlite,Vivado 2017.4" *)
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module axi_uartlite_module(s_axi_aclk, s_axi_aresetn, interrupt,
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s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, rx, tx)
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/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,interrupt,s_axi_awaddr[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,rx,tx" */;
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input s_axi_aclk;
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input s_axi_aresetn;
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output interrupt;
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input [3:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [3:0]s_axi_araddr;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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input rx;
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output tx;
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endmodule
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