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vv_gulyaev |
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date : Thu Jul 30 13:54:39 2020
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| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command : report_utilization -file aes128_ecb_fpga_wrap_utilization_synth.rpt -pb aes128_ecb_fpga_wrap_utilization_synth.pb
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| Design : aes128_ecb_fpga_wrap
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| Device : 7k325tffg900-2
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| Design State : Synthesized
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+-------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------------+------+-------+-----------+-------+
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| Slice LUTs* | 2780 | 0 | 203800 | 1.36 |
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| LUT as Logic | 2780 | 0 | 203800 | 1.36 |
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| LUT as Memory | 0 | 0 | 64000 | 0.00 |
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| Slice Registers | 876 | 0 | 407600 | 0.21 |
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| Register as Flip Flop | 872 | 0 | 407600 | 0.21 |
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| Register as Latch | 4 | 0 | 407600 | <0.01 |
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| F7 Muxes | 637 | 0 | 101900 | 0.63 |
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| F8 Muxes | 270 | 0 | 50950 | 0.53 |
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+-------------------------+------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 4 | Yes | - | Set |
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| 872 | Yes | - | Reset |
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| 0 | Yes | Set | - |
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| 0 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+----------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------+------+-------+-----------+-------+
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| Block RAM Tile | 0 | 0 | 445 | 0.00 |
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| RAMB36/FIFO* | 0 | 0 | 445 | 0.00 |
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| RAMB18 | 0 | 0 | 890 | 0.00 |
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+----------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 840 | 0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB | 7 | 0 | 500 | 1.40 |
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| Bonded IPADs | 0 | 0 | 50 | 0.00 |
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| Bonded OPADs | 0 | 0 | 32 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
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| PHASER_REF | 0 | 0 | 10 | 0.00 |
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| OUT_FIFO | 0 | 0 | 40 | 0.00 |
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| IN_FIFO | 0 | 0 | 40 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
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| IBUFDS | 0 | 0 | 480 | 0.00 |
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| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
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| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
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| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
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| ILOGIC | 0 | 0 | 500 | 0.00 |
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| OLOGIC | 0 | 0 | 500 | 0.00 |
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+-----------------------------+------+-------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 0 | 0 | 32 | 0.00 |
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| BUFIO | 0 | 0 | 40 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
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| BUFMRCE | 0 | 0 | 20 | 0.00 |
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| BUFHCE | 0 | 0 | 168 | 0.00 |
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| BUFR | 0 | 0 | 40 | 0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+----------+------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+---------------------+
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| LUT6 | 1930 | LUT |
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| FDCE | 868 | Flop & Latch |
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| MUXF7 | 637 | MuxFx |
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| LUT2 | 435 | LUT |
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| LUT3 | 306 | LUT |
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| MUXF8 | 270 | MuxFx |
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| LUT5 | 220 | LUT |
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| LUT4 | 154 | LUT |
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| CARRY4 | 8 | CarryLogic |
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| OBUF | 5 | IO |
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| LDCE | 4 | Flop & Latch |
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| FDPE | 4 | Flop & Latch |
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| LUT1 | 3 | LUT |
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| IBUF | 2 | IO |
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+----------+------+---------------------+
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8. Black Boxes
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--------------
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+---------------------+------+
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| Ref Name | Used |
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+---------------------+------+
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| clk_gen | 1 |
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| axi_uartlite_module | 1 |
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+---------------------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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