1 |
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vv_gulyaev |
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2 |
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--Generic Help
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3 |
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--C_CDC_TYPE : Defines the type of CDC needed
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4 |
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-- 0 means pulse synchronizer. Used to transfer one clock pulse
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5 |
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-- from prmry domain to scndry domain.
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-- 1 means level synchronizer. Used to transfer level signal.
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-- 2 means level synchronizer with ack. Used to transfer level
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-- signal. Input signal should change only when prmry_ack is detected
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9 |
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--
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--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
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-- Set to 0 when incoming signal is purely floped signal.
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--
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--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
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-- it might be needed.
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-- 0 means reset not needed for sync flops
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-- 1 means reset needed for sync flops. i
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-- In this case prmry_resetn should be in prmry clock,
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-- while scndry_reset should be in scndry clock.
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--
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--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
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-- However, based on design buses can also be CDC'ed.
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-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
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-- Output is on scndry_vect_out.
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-- 1 means it is a single bit. In this case input be connected to prmry_in.
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25 |
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-- Output is on scndry_out.
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--
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--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
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28 |
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--
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29 |
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--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
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-- Value of 0, 1 is allowed only for level CDC.
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31 |
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-- Min value for Pulse CDC is 2
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32 |
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--
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--Whenever this file is used following XDC constraint has to be added
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-- set_false_path -to [get_pins -hier *cdc_to*/D]
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38 |
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--IO Ports
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--
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40 |
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-- prmry_aclk : clock of originating domain (source domain)
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-- prmry_resetn : sync reset of originating clock domain (source domain)
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-- prmry_in : input signal bit. This should be a pure flop output without
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-- any combi logic. This is source.
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-- prmry_vect_in : bus signal. From Source domain.
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-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
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-- Used only when C_CDC_TYPE = 2
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-- scndry_aclk : destination clock.
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-- scndry_resetn : sync reset of destination domain
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-- scndry_out : sync'ed output in destination domain. Single bit.
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-- scndry_vect_out : sync'ed output in destination domain. bus.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_misc.all;
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library unisim;
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use unisim.vcomponents.FDR;
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63 |
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entity cdc_sync is
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generic (
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C_CDC_TYPE : integer range 0 to 2 := 1 ;
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-- 0 is pulse synch
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-- 1 is level synch
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-- 2 is ack based level sync
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C_RESET_STATE : integer range 0 to 1 := 0 ;
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-- 0 is reset not needed
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-- 1 is reset needed
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C_SINGLE_BIT : integer range 0 to 1 := 1 ;
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-- 0 is bus input
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-- 1 is single bit input
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C_FLOP_INPUT : integer range 0 to 1 := 0 ;
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C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
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C_MTBF_STAGES : integer range 0 to 6 := 2
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-- Vector Data witdth
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);
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port (
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prmry_aclk : in std_logic ; --
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prmry_resetn : in std_logic ; --
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prmry_in : in std_logic ; --
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prmry_vect_in : in std_logic_vector --
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(C_VECTOR_WIDTH - 1 downto 0) ; --
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prmry_ack : out std_logic ;
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--
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scndry_aclk : in std_logic ; --
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scndry_resetn : in std_logic ; --
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--
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-- Primary to Secondary Clock Crossing --
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scndry_out : out std_logic ; --
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--
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scndry_vect_out : out std_logic_vector --
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(C_VECTOR_WIDTH - 1 downto 0) --
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);
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end cdc_sync;
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-------------------------------------------------------------------------------
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104 |
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-- Architecture
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-------------------------------------------------------------------------------
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architecture implementation of cdc_sync is
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108 |
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attribute DowngradeIPIdentifiedWarnings : string;
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attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
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110 |
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111 |
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--attribute DONT_TOUCH : STRING;
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--attribute KEEP : STRING;
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113 |
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--attribute DONT_TOUCH of implementation : architecture is "yes";
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signal prmry_resetn1 : std_logic := '0';
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signal scndry_resetn1 : std_logic := '0';
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signal prmry_reset2 : std_logic := '0';
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signal scndry_reset2 : std_logic := '0';
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--attribute KEEP of prmry_resetn1 : signal is "true";
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--attribute KEEP of scndry_resetn1 : signal is "true";
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120 |
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121 |
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-------------------------------------------------------------------------------
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122 |
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-- Functions
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123 |
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-------------------------------------------------------------------------------
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125 |
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-- No Functions Declared
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126 |
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127 |
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-------------------------------------------------------------------------------
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128 |
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-- Constants Declarations
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129 |
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-------------------------------------------------------------------------------
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130 |
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131 |
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-- No Constants Declared
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132 |
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133 |
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-------------------------------------------------------------------------------
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134 |
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-- Begin architecture logic
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135 |
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-------------------------------------------------------------------------------
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136 |
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begin
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137 |
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138 |
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HAS_RESET : if C_RESET_STATE = 1 generate
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139 |
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begin
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140 |
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prmry_resetn1 <= prmry_resetn;
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141 |
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scndry_resetn1 <= scndry_resetn;
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142 |
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143 |
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end generate HAS_RESET;
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144 |
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145 |
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HAS_NO_RESET : if C_RESET_STATE = 0 generate
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146 |
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begin
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147 |
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148 |
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prmry_resetn1 <= '1';
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149 |
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scndry_resetn1 <= '1';
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150 |
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151 |
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end generate HAS_NO_RESET;
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152 |
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153 |
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prmry_reset2 <= not prmry_resetn1;
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154 |
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scndry_reset2 <= not scndry_resetn1;
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155 |
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156 |
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157 |
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-- Generate PULSE clock domain crossing
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158 |
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GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
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159 |
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160 |
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-- Primary to Secondary
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161 |
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signal s_out_d1_cdc_to : std_logic := '0';
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162 |
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--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
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163 |
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signal s_out_d2 : std_logic := '0';
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164 |
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signal s_out_d3 : std_logic := '0';
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165 |
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signal s_out_d4 : std_logic := '0';
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166 |
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signal s_out_d5 : std_logic := '0';
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167 |
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signal s_out_d6 : std_logic := '0';
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168 |
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signal s_out_d7 : std_logic := '0';
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169 |
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signal s_out_re : std_logic := '0';
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170 |
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signal prmry_in_xored : std_logic := '0';
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171 |
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signal p_in_d1_cdc_from : std_logic := '0';
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172 |
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173 |
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signal srst_d1 : std_logic := '0';
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174 |
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signal srst_d2 : std_logic := '0';
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175 |
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signal srst_d3 : std_logic := '0';
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176 |
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signal srst_d4 : std_logic := '0';
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177 |
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signal srst_d5 : std_logic := '0';
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178 |
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signal srst_d6 : std_logic := '0';
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179 |
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signal srst_d7 : std_logic := '0';
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180 |
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181 |
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-----------------------------------------------------------------------------
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182 |
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-- ATTRIBUTE Declarations
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183 |
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-----------------------------------------------------------------------------
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184 |
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-- Prevent x-propagation on clock-domain crossing register
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185 |
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ATTRIBUTE async_reg : STRING;
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186 |
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ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
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187 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
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188 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
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189 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
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190 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
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191 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
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192 |
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ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
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193 |
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194 |
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begin
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195 |
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196 |
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--*****************************************************************************
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197 |
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--** Asynchronous Pulse Clock Crossing **
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198 |
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--** PRIMARY TO SECONDARY OPEN-ENDED **
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199 |
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--*****************************************************************************
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200 |
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201 |
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scndry_vect_out <= (others => '0');
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202 |
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prmry_ack <= '0';
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203 |
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204 |
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prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
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205 |
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206 |
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--------------------------------------REG_P_IN : process(prmry_aclk)
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207 |
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-------------------------------------- begin
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208 |
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-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
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209 |
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-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
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210 |
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-------------------------------------- p_in_d1_cdc_from <= '0';
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211 |
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-------------------------------------- else
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212 |
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-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
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213 |
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-------------------------------------- end if;
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214 |
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-------------------------------------- end if;
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215 |
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-------------------------------------- end process REG_P_IN;
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216 |
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217 |
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218 |
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219 |
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REG_P_IN_cdc_from : component FDR
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220 |
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generic map(INIT => '0'
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221 |
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)port map (
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222 |
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Q => p_in_d1_cdc_from,
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223 |
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C => prmry_aclk,
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224 |
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D => prmry_in_xored,
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225 |
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R => prmry_reset2
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226 |
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);
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227 |
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228 |
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229 |
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230 |
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231 |
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232 |
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REG_P_IN2_cdc_to : component FDR
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233 |
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generic map(INIT => '0'
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234 |
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)port map (
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235 |
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Q => s_out_d1_cdc_to,
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236 |
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C => scndry_aclk,
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237 |
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D => p_in_d1_cdc_from,
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238 |
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R => scndry_reset2
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239 |
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);
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240 |
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241 |
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242 |
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243 |
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------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
|
244 |
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------------------------------------ begin
|
245 |
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------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
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246 |
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------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
247 |
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------------------------------------ s_out_d2 <= '0';
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248 |
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------------------------------------ s_out_d3 <= '0';
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249 |
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------------------------------------ s_out_d4 <= '0';
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250 |
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------------------------------------ s_out_d5 <= '0';
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251 |
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------------------------------------ s_out_d6 <= '0';
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252 |
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------------------------------------ s_out_d7 <= '0';
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253 |
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------------------------------------ scndry_out <= '0';
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254 |
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------------------------------------ else
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255 |
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------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
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256 |
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------------------------------------ s_out_d3 <= s_out_d2;
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257 |
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------------------------------------ s_out_d4 <= s_out_d3;
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258 |
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------------------------------------ s_out_d5 <= s_out_d4;
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259 |
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------------------------------------ s_out_d6 <= s_out_d5;
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260 |
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------------------------------------ s_out_d7 <= s_out_d6;
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261 |
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------------------------------------ scndry_out <= s_out_re;
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262 |
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------------------------------------ end if;
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263 |
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------------------------------------ end if;
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264 |
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------------------------------------ end process P_IN_CROSS2SCNDRY;
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265 |
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266 |
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|
267 |
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|
268 |
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|
269 |
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P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
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270 |
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generic map(INIT => '0'
|
271 |
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)port map (
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272 |
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Q => s_out_d2,
|
273 |
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C => scndry_aclk,
|
274 |
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D => s_out_d1_cdc_to,
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275 |
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R => scndry_reset2
|
276 |
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);
|
277 |
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|
278 |
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279 |
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P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
|
280 |
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generic map(INIT => '0'
|
281 |
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)port map (
|
282 |
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Q => s_out_d3,
|
283 |
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C => scndry_aclk,
|
284 |
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D => s_out_d2,
|
285 |
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R => scndry_reset2
|
286 |
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);
|
287 |
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|
288 |
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|
289 |
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P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
|
290 |
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generic map(INIT => '0'
|
291 |
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)port map (
|
292 |
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Q => s_out_d4,
|
293 |
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C => scndry_aclk,
|
294 |
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D => s_out_d3,
|
295 |
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R => scndry_reset2
|
296 |
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);
|
297 |
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|
298 |
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|
299 |
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P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
|
300 |
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generic map(INIT => '0'
|
301 |
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)port map (
|
302 |
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Q => s_out_d5,
|
303 |
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C => scndry_aclk,
|
304 |
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D => s_out_d4,
|
305 |
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R => scndry_reset2
|
306 |
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);
|
307 |
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|
308 |
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|
309 |
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P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
|
310 |
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generic map(INIT => '0'
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311 |
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)port map (
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312 |
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Q => s_out_d6,
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313 |
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C => scndry_aclk,
|
314 |
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D => s_out_d5,
|
315 |
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R => scndry_reset2
|
316 |
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);
|
317 |
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|
318 |
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|
319 |
|
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|
320 |
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P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
|
321 |
|
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generic map(INIT => '0'
|
322 |
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)port map (
|
323 |
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Q => s_out_d7,
|
324 |
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C => scndry_aclk,
|
325 |
|
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D => s_out_d6,
|
326 |
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R => scndry_reset2
|
327 |
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);
|
328 |
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|
329 |
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|
330 |
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P_IN_CROSS2SCNDRY_scndry_out : component FDR
|
331 |
|
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generic map(INIT => '0'
|
332 |
|
|
)port map (
|
333 |
|
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Q => scndry_out,
|
334 |
|
|
C => scndry_aclk,
|
335 |
|
|
D => s_out_re,
|
336 |
|
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R => scndry_reset2
|
337 |
|
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);
|
338 |
|
|
|
339 |
|
|
s_rst_d1 : component FDR
|
340 |
|
|
generic map(INIT => '0'
|
341 |
|
|
)port map (
|
342 |
|
|
Q => srst_d1,
|
343 |
|
|
C => scndry_aclk,
|
344 |
|
|
D => '1',
|
345 |
|
|
R => scndry_reset2
|
346 |
|
|
);
|
347 |
|
|
s_rst_d2 : component FDR
|
348 |
|
|
generic map(INIT => '0'
|
349 |
|
|
)port map (
|
350 |
|
|
Q => srst_d2,
|
351 |
|
|
C => scndry_aclk,
|
352 |
|
|
D => srst_d1,
|
353 |
|
|
R => scndry_reset2
|
354 |
|
|
);
|
355 |
|
|
s_rst_d3 : component FDR
|
356 |
|
|
generic map(INIT => '0'
|
357 |
|
|
)port map (
|
358 |
|
|
Q => srst_d3,
|
359 |
|
|
C => scndry_aclk,
|
360 |
|
|
D => srst_d2,
|
361 |
|
|
R => scndry_reset2
|
362 |
|
|
);
|
363 |
|
|
|
364 |
|
|
s_rst_d4 : component FDR
|
365 |
|
|
generic map(INIT => '0'
|
366 |
|
|
)port map (
|
367 |
|
|
Q => srst_d4,
|
368 |
|
|
C => scndry_aclk,
|
369 |
|
|
D => srst_d3,
|
370 |
|
|
R => scndry_reset2
|
371 |
|
|
);
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
s_rst_d5 : component FDR
|
375 |
|
|
generic map(INIT => '0'
|
376 |
|
|
)port map (
|
377 |
|
|
Q => srst_d5,
|
378 |
|
|
C => scndry_aclk,
|
379 |
|
|
D => srst_d4,
|
380 |
|
|
R => scndry_reset2
|
381 |
|
|
);
|
382 |
|
|
|
383 |
|
|
s_rst_d6 : component FDR
|
384 |
|
|
generic map(INIT => '0'
|
385 |
|
|
)port map (
|
386 |
|
|
Q => srst_d6,
|
387 |
|
|
C => scndry_aclk,
|
388 |
|
|
D => srst_d5,
|
389 |
|
|
R => scndry_reset2
|
390 |
|
|
);
|
391 |
|
|
|
392 |
|
|
s_rst_d7 : component FDR
|
393 |
|
|
generic map(INIT => '0'
|
394 |
|
|
)port map (
|
395 |
|
|
Q => srst_d7,
|
396 |
|
|
C => scndry_aclk,
|
397 |
|
|
D => srst_d6,
|
398 |
|
|
R => scndry_reset2
|
399 |
|
|
);
|
400 |
|
|
|
401 |
|
|
MTBF_2 : if C_MTBF_STAGES = 2 generate
|
402 |
|
|
begin
|
403 |
|
|
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
|
404 |
|
|
|
405 |
|
|
end generate MTBF_2;
|
406 |
|
|
|
407 |
|
|
MTBF_3 : if C_MTBF_STAGES = 3 generate
|
408 |
|
|
begin
|
409 |
|
|
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
|
410 |
|
|
|
411 |
|
|
end generate MTBF_3;
|
412 |
|
|
|
413 |
|
|
MTBF_4 : if C_MTBF_STAGES = 4 generate
|
414 |
|
|
begin
|
415 |
|
|
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
|
416 |
|
|
|
417 |
|
|
end generate MTBF_4;
|
418 |
|
|
|
419 |
|
|
MTBF_5 : if C_MTBF_STAGES = 5 generate
|
420 |
|
|
begin
|
421 |
|
|
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
|
422 |
|
|
|
423 |
|
|
end generate MTBF_5;
|
424 |
|
|
|
425 |
|
|
MTBF_6 : if C_MTBF_STAGES = 6 generate
|
426 |
|
|
begin
|
427 |
|
|
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
|
428 |
|
|
|
429 |
|
|
end generate MTBF_6;
|
430 |
|
|
|
431 |
|
|
-- Feed secondary pulse out
|
432 |
|
|
|
433 |
|
|
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
-- Generate LEVEL clock domain crossing with reset state = 0
|
437 |
|
|
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
|
438 |
|
|
begin
|
439 |
|
|
-- Primary to Secondary
|
440 |
|
|
|
441 |
|
|
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
|
442 |
|
|
|
443 |
|
|
signal p_level_in_d1_cdc_from : std_logic := '0';
|
444 |
|
|
signal p_level_in_int : std_logic := '0';
|
445 |
|
|
signal s_level_out_d1_cdc_to : std_logic := '0';
|
446 |
|
|
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
|
447 |
|
|
signal s_level_out_d2 : std_logic := '0';
|
448 |
|
|
signal s_level_out_d3 : std_logic := '0';
|
449 |
|
|
signal s_level_out_d4 : std_logic := '0';
|
450 |
|
|
signal s_level_out_d5 : std_logic := '0';
|
451 |
|
|
signal s_level_out_d6 : std_logic := '0';
|
452 |
|
|
-----------------------------------------------------------------------------
|
453 |
|
|
-- ATTRIBUTE Declarations
|
454 |
|
|
-----------------------------------------------------------------------------
|
455 |
|
|
-- Prevent x-propagation on clock-domain crossing register
|
456 |
|
|
ATTRIBUTE async_reg : STRING;
|
457 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
|
458 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
|
459 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
|
460 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
|
461 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
|
462 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
|
463 |
|
|
|
464 |
|
|
begin
|
465 |
|
|
|
466 |
|
|
--*****************************************************************************
|
467 |
|
|
--** Asynchronous Level Clock Crossing **
|
468 |
|
|
--** PRIMARY TO SECONDARY **
|
469 |
|
|
--*****************************************************************************
|
470 |
|
|
-- register is scndry to provide clean ff output to clock crossing logic
|
471 |
|
|
|
472 |
|
|
scndry_vect_out <= (others => '0');
|
473 |
|
|
prmry_ack <= '0';
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
|
477 |
|
|
begin
|
478 |
|
|
|
479 |
|
|
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
|
480 |
|
|
---------------------------------- begin
|
481 |
|
|
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
|
482 |
|
|
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
483 |
|
|
---------------------------------- p_level_in_d1_cdc_from <= '0';
|
484 |
|
|
---------------------------------- else
|
485 |
|
|
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
|
486 |
|
|
---------------------------------- end if;
|
487 |
|
|
---------------------------------- end if;
|
488 |
|
|
---------------------------------- end process REG_PLEVEL_IN;
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
REG_PLEVEL_IN_cdc_from : component FDR
|
492 |
|
|
generic map(INIT => '0'
|
493 |
|
|
)port map (
|
494 |
|
|
Q => p_level_in_d1_cdc_from,
|
495 |
|
|
C => prmry_aclk,
|
496 |
|
|
D => prmry_in,
|
497 |
|
|
R => prmry_reset2
|
498 |
|
|
);
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
p_level_in_int <= p_level_in_d1_cdc_from;
|
502 |
|
|
|
503 |
|
|
end generate INPUT_FLOP;
|
504 |
|
|
|
505 |
|
|
|
506 |
|
|
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
|
507 |
|
|
begin
|
508 |
|
|
|
509 |
|
|
p_level_in_int <= prmry_in;
|
510 |
|
|
|
511 |
|
|
end generate NO_INPUT_FLOP;
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
|
515 |
|
|
generic map(INIT => '0'
|
516 |
|
|
)port map (
|
517 |
|
|
Q => s_level_out_d1_cdc_to,
|
518 |
|
|
C => scndry_aclk,
|
519 |
|
|
D => p_level_in_int,
|
520 |
|
|
R => scndry_reset2
|
521 |
|
|
);
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
|
525 |
|
|
------------------------------ begin
|
526 |
|
|
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
|
527 |
|
|
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
528 |
|
|
------------------------------ s_level_out_d2 <= '0';
|
529 |
|
|
------------------------------ s_level_out_d3 <= '0';
|
530 |
|
|
------------------------------ s_level_out_d4 <= '0';
|
531 |
|
|
------------------------------ s_level_out_d5 <= '0';
|
532 |
|
|
------------------------------ s_level_out_d6 <= '0';
|
533 |
|
|
------------------------------ else
|
534 |
|
|
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
|
535 |
|
|
------------------------------ s_level_out_d3 <= s_level_out_d2;
|
536 |
|
|
------------------------------ s_level_out_d4 <= s_level_out_d3;
|
537 |
|
|
------------------------------ s_level_out_d5 <= s_level_out_d4;
|
538 |
|
|
------------------------------ s_level_out_d6 <= s_level_out_d5;
|
539 |
|
|
------------------------------ end if;
|
540 |
|
|
------------------------------ end if;
|
541 |
|
|
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
|
542 |
|
|
|
543 |
|
|
|
544 |
|
|
|
545 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
|
546 |
|
|
generic map(INIT => '0'
|
547 |
|
|
)port map (
|
548 |
|
|
Q => s_level_out_d2,
|
549 |
|
|
C => scndry_aclk,
|
550 |
|
|
D => s_level_out_d1_cdc_to,
|
551 |
|
|
R => scndry_reset2
|
552 |
|
|
);
|
553 |
|
|
|
554 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
|
555 |
|
|
generic map(INIT => '0'
|
556 |
|
|
)port map (
|
557 |
|
|
Q => s_level_out_d3,
|
558 |
|
|
C => scndry_aclk,
|
559 |
|
|
D => s_level_out_d2,
|
560 |
|
|
R => scndry_reset2
|
561 |
|
|
);
|
562 |
|
|
|
563 |
|
|
|
564 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
|
565 |
|
|
generic map(INIT => '0'
|
566 |
|
|
)port map (
|
567 |
|
|
Q => s_level_out_d4,
|
568 |
|
|
C => scndry_aclk,
|
569 |
|
|
D => s_level_out_d3,
|
570 |
|
|
R => scndry_reset2
|
571 |
|
|
);
|
572 |
|
|
|
573 |
|
|
|
574 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
|
575 |
|
|
generic map(INIT => '0'
|
576 |
|
|
)port map (
|
577 |
|
|
Q => s_level_out_d5,
|
578 |
|
|
C => scndry_aclk,
|
579 |
|
|
D => s_level_out_d4,
|
580 |
|
|
R => scndry_reset2
|
581 |
|
|
);
|
582 |
|
|
|
583 |
|
|
|
584 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
|
585 |
|
|
generic map(INIT => '0'
|
586 |
|
|
)port map (
|
587 |
|
|
Q => s_level_out_d6,
|
588 |
|
|
C => scndry_aclk,
|
589 |
|
|
D => s_level_out_d5,
|
590 |
|
|
R => scndry_reset2
|
591 |
|
|
);
|
592 |
|
|
|
593 |
|
|
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
|
597 |
|
|
|
598 |
|
|
|
599 |
|
|
MTBF_L1 : if C_MTBF_STAGES = 1 generate
|
600 |
|
|
begin
|
601 |
|
|
scndry_out <= s_level_out_d1_cdc_to;
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
end generate MTBF_L1;
|
605 |
|
|
|
606 |
|
|
MTBF_L2 : if C_MTBF_STAGES = 2 generate
|
607 |
|
|
begin
|
608 |
|
|
|
609 |
|
|
scndry_out <= s_level_out_d2;
|
610 |
|
|
|
611 |
|
|
|
612 |
|
|
end generate MTBF_L2;
|
613 |
|
|
|
614 |
|
|
MTBF_L3 : if C_MTBF_STAGES = 3 generate
|
615 |
|
|
begin
|
616 |
|
|
|
617 |
|
|
scndry_out <= s_level_out_d3;
|
618 |
|
|
|
619 |
|
|
|
620 |
|
|
|
621 |
|
|
end generate MTBF_L3;
|
622 |
|
|
|
623 |
|
|
MTBF_L4 : if C_MTBF_STAGES = 4 generate
|
624 |
|
|
begin
|
625 |
|
|
scndry_out <= s_level_out_d4;
|
626 |
|
|
|
627 |
|
|
|
628 |
|
|
|
629 |
|
|
end generate MTBF_L4;
|
630 |
|
|
|
631 |
|
|
MTBF_L5 : if C_MTBF_STAGES = 5 generate
|
632 |
|
|
begin
|
633 |
|
|
|
634 |
|
|
scndry_out <= s_level_out_d5;
|
635 |
|
|
|
636 |
|
|
|
637 |
|
|
end generate MTBF_L5;
|
638 |
|
|
|
639 |
|
|
MTBF_L6 : if C_MTBF_STAGES = 6 generate
|
640 |
|
|
begin
|
641 |
|
|
|
642 |
|
|
scndry_out <= s_level_out_d6;
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
end generate MTBF_L6;
|
646 |
|
|
|
647 |
|
|
end generate SINGLE_BIT;
|
648 |
|
|
|
649 |
|
|
|
650 |
|
|
|
651 |
|
|
MULTI_BIT : if C_SINGLE_BIT = 0 generate
|
652 |
|
|
|
653 |
|
|
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
|
654 |
|
|
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
655 |
|
|
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
656 |
|
|
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
|
657 |
|
|
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
658 |
|
|
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
659 |
|
|
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
660 |
|
|
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
661 |
|
|
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
662 |
|
|
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
|
663 |
|
|
-----------------------------------------------------------------------------
|
664 |
|
|
-- ATTRIBUTE Declarations
|
665 |
|
|
-----------------------------------------------------------------------------
|
666 |
|
|
-- Prevent x-propagation on clock-domain crossing register
|
667 |
|
|
ATTRIBUTE async_reg : STRING;
|
668 |
|
|
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
|
669 |
|
|
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
|
670 |
|
|
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
|
671 |
|
|
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
|
672 |
|
|
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
|
673 |
|
|
|
674 |
|
|
begin
|
675 |
|
|
|
676 |
|
|
--*****************************************************************************
|
677 |
|
|
--** Asynchronous Level Clock Crossing **
|
678 |
|
|
--** PRIMARY TO SECONDARY **
|
679 |
|
|
--*****************************************************************************
|
680 |
|
|
-- register is scndry to provide clean ff output to clock crossing logic
|
681 |
|
|
|
682 |
|
|
scndry_out <= '0';
|
683 |
|
|
prmry_ack <= '0';
|
684 |
|
|
|
685 |
|
|
|
686 |
|
|
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
|
687 |
|
|
begin
|
688 |
|
|
|
689 |
|
|
|
690 |
|
|
|
691 |
|
|
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
|
692 |
|
|
----------------------------------- begin
|
693 |
|
|
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
|
694 |
|
|
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
695 |
|
|
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
|
696 |
|
|
----------------------------------- else
|
697 |
|
|
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
|
698 |
|
|
----------------------------------- end if;
|
699 |
|
|
----------------------------------- end if;
|
700 |
|
|
----------------------------------- end process REG_PLEVEL_IN;
|
701 |
|
|
|
702 |
|
|
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
703 |
|
|
begin
|
704 |
|
|
|
705 |
|
|
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
|
706 |
|
|
generic map(INIT => '0'
|
707 |
|
|
)port map (
|
708 |
|
|
Q => p_level_in_bus_d1_cdc_from (i),
|
709 |
|
|
C => prmry_aclk,
|
710 |
|
|
D => prmry_vect_in (i),
|
711 |
|
|
R => prmry_reset2
|
712 |
|
|
);
|
713 |
|
|
end generate FOR_REG_PLEVEL_IN;
|
714 |
|
|
|
715 |
|
|
|
716 |
|
|
|
717 |
|
|
|
718 |
|
|
|
719 |
|
|
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
|
720 |
|
|
|
721 |
|
|
end generate INPUT_FLOP_BUS;
|
722 |
|
|
|
723 |
|
|
|
724 |
|
|
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
|
725 |
|
|
begin
|
726 |
|
|
|
727 |
|
|
p_level_in_bus_int <= prmry_vect_in;
|
728 |
|
|
|
729 |
|
|
end generate NO_INPUT_FLOP_BUS;
|
730 |
|
|
|
731 |
|
|
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
732 |
|
|
|
733 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
|
734 |
|
|
begin
|
735 |
|
|
|
736 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
|
737 |
|
|
generic map(INIT => '0'
|
738 |
|
|
)port map (
|
739 |
|
|
Q => s_level_out_bus_d1_cdc_to (i),
|
740 |
|
|
C => scndry_aclk,
|
741 |
|
|
D => p_level_in_bus_int (i),
|
742 |
|
|
R => scndry_reset2
|
743 |
|
|
);
|
744 |
|
|
end generate FOR_IN_cdc_to;
|
745 |
|
|
|
746 |
|
|
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
|
747 |
|
|
----------------------------------------- begin
|
748 |
|
|
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
|
749 |
|
|
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
750 |
|
|
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
|
751 |
|
|
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
|
752 |
|
|
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
|
753 |
|
|
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
|
754 |
|
|
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
|
755 |
|
|
----------------------------------------- else
|
756 |
|
|
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
|
757 |
|
|
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
|
758 |
|
|
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
|
759 |
|
|
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
|
760 |
|
|
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
|
761 |
|
|
----------------------------------------- end if;
|
762 |
|
|
----------------------------------------- end if;
|
763 |
|
|
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
|
764 |
|
|
|
765 |
|
|
|
766 |
|
|
|
767 |
|
|
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
768 |
|
|
|
769 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
|
770 |
|
|
begin
|
771 |
|
|
|
772 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
|
773 |
|
|
generic map(INIT => '0'
|
774 |
|
|
)port map (
|
775 |
|
|
Q => s_level_out_bus_d2 (i),
|
776 |
|
|
C => scndry_aclk,
|
777 |
|
|
D => s_level_out_bus_d1_cdc_to (i),
|
778 |
|
|
R => scndry_reset2
|
779 |
|
|
);
|
780 |
|
|
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
|
781 |
|
|
|
782 |
|
|
|
783 |
|
|
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
784 |
|
|
|
785 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
|
786 |
|
|
begin
|
787 |
|
|
|
788 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
|
789 |
|
|
generic map(INIT => '0'
|
790 |
|
|
)port map (
|
791 |
|
|
Q => s_level_out_bus_d3 (i),
|
792 |
|
|
C => scndry_aclk,
|
793 |
|
|
D => s_level_out_bus_d2 (i),
|
794 |
|
|
R => scndry_reset2
|
795 |
|
|
);
|
796 |
|
|
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
|
797 |
|
|
|
798 |
|
|
|
799 |
|
|
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
800 |
|
|
|
801 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
|
802 |
|
|
begin
|
803 |
|
|
|
804 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
|
805 |
|
|
generic map(INIT => '0'
|
806 |
|
|
)port map (
|
807 |
|
|
Q => s_level_out_bus_d4 (i),
|
808 |
|
|
C => scndry_aclk,
|
809 |
|
|
D => s_level_out_bus_d3 (i),
|
810 |
|
|
R => scndry_reset2
|
811 |
|
|
);
|
812 |
|
|
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
|
816 |
|
|
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
817 |
|
|
|
818 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
|
819 |
|
|
begin
|
820 |
|
|
|
821 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
|
822 |
|
|
generic map(INIT => '0'
|
823 |
|
|
)port map (
|
824 |
|
|
Q => s_level_out_bus_d5 (i),
|
825 |
|
|
C => scndry_aclk,
|
826 |
|
|
D => s_level_out_bus_d4 (i),
|
827 |
|
|
R => scndry_reset2
|
828 |
|
|
);
|
829 |
|
|
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
|
830 |
|
|
|
831 |
|
|
|
832 |
|
|
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
|
833 |
|
|
|
834 |
|
|
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
|
835 |
|
|
begin
|
836 |
|
|
|
837 |
|
|
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
|
838 |
|
|
generic map(INIT => '0'
|
839 |
|
|
)port map (
|
840 |
|
|
Q => s_level_out_bus_d6 (i),
|
841 |
|
|
C => scndry_aclk,
|
842 |
|
|
D => s_level_out_bus_d5 (i),
|
843 |
|
|
R => scndry_reset2
|
844 |
|
|
);
|
845 |
|
|
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
|
846 |
|
|
|
847 |
|
|
|
848 |
|
|
|
849 |
|
|
MTBF_L1 : if C_MTBF_STAGES = 1 generate
|
850 |
|
|
begin
|
851 |
|
|
|
852 |
|
|
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
|
853 |
|
|
|
854 |
|
|
|
855 |
|
|
end generate MTBF_L1;
|
856 |
|
|
|
857 |
|
|
MTBF_L2 : if C_MTBF_STAGES = 2 generate
|
858 |
|
|
begin
|
859 |
|
|
|
860 |
|
|
scndry_vect_out <= s_level_out_bus_d2;
|
861 |
|
|
|
862 |
|
|
|
863 |
|
|
end generate MTBF_L2;
|
864 |
|
|
|
865 |
|
|
MTBF_L3 : if C_MTBF_STAGES = 3 generate
|
866 |
|
|
begin
|
867 |
|
|
|
868 |
|
|
scndry_vect_out <= s_level_out_bus_d3;
|
869 |
|
|
|
870 |
|
|
|
871 |
|
|
|
872 |
|
|
end generate MTBF_L3;
|
873 |
|
|
|
874 |
|
|
MTBF_L4 : if C_MTBF_STAGES = 4 generate
|
875 |
|
|
begin
|
876 |
|
|
scndry_vect_out <= s_level_out_bus_d4;
|
877 |
|
|
|
878 |
|
|
|
879 |
|
|
|
880 |
|
|
end generate MTBF_L4;
|
881 |
|
|
|
882 |
|
|
MTBF_L5 : if C_MTBF_STAGES = 5 generate
|
883 |
|
|
begin
|
884 |
|
|
|
885 |
|
|
scndry_vect_out <= s_level_out_bus_d5;
|
886 |
|
|
|
887 |
|
|
|
888 |
|
|
end generate MTBF_L5;
|
889 |
|
|
|
890 |
|
|
MTBF_L6 : if C_MTBF_STAGES = 6 generate
|
891 |
|
|
begin
|
892 |
|
|
|
893 |
|
|
scndry_vect_out <= s_level_out_bus_d6;
|
894 |
|
|
|
895 |
|
|
|
896 |
|
|
end generate MTBF_L6;
|
897 |
|
|
|
898 |
|
|
end generate MULTI_BIT;
|
899 |
|
|
|
900 |
|
|
|
901 |
|
|
end generate GENERATE_LEVEL_P_S_CDC;
|
902 |
|
|
|
903 |
|
|
|
904 |
|
|
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
|
905 |
|
|
-- Primary to Secondary
|
906 |
|
|
|
907 |
|
|
|
908 |
|
|
signal p_level_in_d1_cdc_from : std_logic := '0';
|
909 |
|
|
signal p_level_in_int : std_logic := '0';
|
910 |
|
|
signal s_level_out_d1_cdc_to : std_logic := '0';
|
911 |
|
|
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
|
912 |
|
|
signal s_level_out_d2 : std_logic := '0';
|
913 |
|
|
signal s_level_out_d3 : std_logic := '0';
|
914 |
|
|
signal s_level_out_d4 : std_logic := '0';
|
915 |
|
|
signal s_level_out_d5 : std_logic := '0';
|
916 |
|
|
signal s_level_out_d6 : std_logic := '0';
|
917 |
|
|
signal p_level_out_d1_cdc_to : std_logic := '0';
|
918 |
|
|
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
|
919 |
|
|
signal p_level_out_d2 : std_logic := '0';
|
920 |
|
|
signal p_level_out_d3 : std_logic := '0';
|
921 |
|
|
signal p_level_out_d4 : std_logic := '0';
|
922 |
|
|
signal p_level_out_d5 : std_logic := '0';
|
923 |
|
|
signal p_level_out_d6 : std_logic := '0';
|
924 |
|
|
signal p_level_out_d7 : std_logic := '0';
|
925 |
|
|
signal scndry_out_int : std_logic := '0';
|
926 |
|
|
signal prmry_pulse_ack : std_logic := '0';
|
927 |
|
|
-----------------------------------------------------------------------------
|
928 |
|
|
-- ATTRIBUTE Declarations
|
929 |
|
|
-----------------------------------------------------------------------------
|
930 |
|
|
-- Prevent x-propagation on clock-domain crossing register
|
931 |
|
|
ATTRIBUTE async_reg : STRING;
|
932 |
|
|
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
|
933 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
|
934 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
|
935 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
|
936 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
|
937 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
|
938 |
|
|
|
939 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
|
940 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
|
941 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
|
942 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
|
943 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
|
944 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
|
945 |
|
|
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
|
946 |
|
|
|
947 |
|
|
begin
|
948 |
|
|
|
949 |
|
|
--*****************************************************************************
|
950 |
|
|
--** Asynchronous Level Clock Crossing **
|
951 |
|
|
--** PRIMARY TO SECONDARY **
|
952 |
|
|
--*****************************************************************************
|
953 |
|
|
-- register is scndry to provide clean ff output to clock crossing logic
|
954 |
|
|
scndry_vect_out <= (others => '0');
|
955 |
|
|
|
956 |
|
|
|
957 |
|
|
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
|
958 |
|
|
begin
|
959 |
|
|
|
960 |
|
|
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
|
961 |
|
|
------------------------------------------ begin
|
962 |
|
|
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
|
963 |
|
|
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
964 |
|
|
------------------------------------------ p_level_in_d1_cdc_from <= '0';
|
965 |
|
|
------------------------------------------ else
|
966 |
|
|
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
|
967 |
|
|
------------------------------------------ end if;
|
968 |
|
|
------------------------------------------ end if;
|
969 |
|
|
------------------------------------------ end process REG_PLEVEL_IN;
|
970 |
|
|
|
971 |
|
|
|
972 |
|
|
|
973 |
|
|
REG_PLEVEL_IN_cdc_from : component FDR
|
974 |
|
|
generic map(INIT => '0'
|
975 |
|
|
)port map (
|
976 |
|
|
Q => p_level_in_d1_cdc_from,
|
977 |
|
|
C => prmry_aclk,
|
978 |
|
|
D => prmry_in,
|
979 |
|
|
R => prmry_reset2
|
980 |
|
|
);
|
981 |
|
|
|
982 |
|
|
|
983 |
|
|
p_level_in_int <= p_level_in_d1_cdc_from;
|
984 |
|
|
|
985 |
|
|
end generate INPUT_FLOP;
|
986 |
|
|
|
987 |
|
|
|
988 |
|
|
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
|
989 |
|
|
begin
|
990 |
|
|
|
991 |
|
|
p_level_in_int <= prmry_in;
|
992 |
|
|
|
993 |
|
|
end generate NO_INPUT_FLOP;
|
994 |
|
|
|
995 |
|
|
|
996 |
|
|
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
|
997 |
|
|
generic map(INIT => '0'
|
998 |
|
|
)port map (
|
999 |
|
|
Q => s_level_out_d1_cdc_to,
|
1000 |
|
|
C => scndry_aclk,
|
1001 |
|
|
D => p_level_in_int,
|
1002 |
|
|
R => scndry_reset2
|
1003 |
|
|
);
|
1004 |
|
|
|
1005 |
|
|
|
1006 |
|
|
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
|
1007 |
|
|
------------------------------------------------ begin
|
1008 |
|
|
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
|
1009 |
|
|
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
1010 |
|
|
------------------------------------------------ s_level_out_d2 <= '0';
|
1011 |
|
|
------------------------------------------------ s_level_out_d3 <= '0';
|
1012 |
|
|
------------------------------------------------ s_level_out_d4 <= '0';
|
1013 |
|
|
------------------------------------------------ s_level_out_d5 <= '0';
|
1014 |
|
|
------------------------------------------------ s_level_out_d6 <= '0';
|
1015 |
|
|
------------------------------------------------ else
|
1016 |
|
|
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
|
1017 |
|
|
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
|
1018 |
|
|
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
|
1019 |
|
|
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
|
1020 |
|
|
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
|
1021 |
|
|
------------------------------------------------ end if;
|
1022 |
|
|
------------------------------------------------ end if;
|
1023 |
|
|
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
|
1024 |
|
|
|
1025 |
|
|
|
1026 |
|
|
|
1027 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
|
1028 |
|
|
generic map(INIT => '0'
|
1029 |
|
|
)port map (
|
1030 |
|
|
Q => s_level_out_d2,
|
1031 |
|
|
C => scndry_aclk,
|
1032 |
|
|
D => s_level_out_d1_cdc_to,
|
1033 |
|
|
R => scndry_reset2
|
1034 |
|
|
);
|
1035 |
|
|
|
1036 |
|
|
|
1037 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
|
1038 |
|
|
generic map(INIT => '0'
|
1039 |
|
|
)port map (
|
1040 |
|
|
Q => s_level_out_d3,
|
1041 |
|
|
C => scndry_aclk,
|
1042 |
|
|
D => s_level_out_d2,
|
1043 |
|
|
R => scndry_reset2
|
1044 |
|
|
);
|
1045 |
|
|
|
1046 |
|
|
|
1047 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
|
1048 |
|
|
generic map(INIT => '0'
|
1049 |
|
|
)port map (
|
1050 |
|
|
Q => s_level_out_d4,
|
1051 |
|
|
C => scndry_aclk,
|
1052 |
|
|
D => s_level_out_d3,
|
1053 |
|
|
R => scndry_reset2
|
1054 |
|
|
);
|
1055 |
|
|
|
1056 |
|
|
|
1057 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
|
1058 |
|
|
generic map(INIT => '0'
|
1059 |
|
|
)port map (
|
1060 |
|
|
Q => s_level_out_d5,
|
1061 |
|
|
C => scndry_aclk,
|
1062 |
|
|
D => s_level_out_d4,
|
1063 |
|
|
R => scndry_reset2
|
1064 |
|
|
);
|
1065 |
|
|
|
1066 |
|
|
|
1067 |
|
|
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
|
1068 |
|
|
generic map(INIT => '0'
|
1069 |
|
|
)port map (
|
1070 |
|
|
Q => s_level_out_d6,
|
1071 |
|
|
C => scndry_aclk,
|
1072 |
|
|
D => s_level_out_d5,
|
1073 |
|
|
R => scndry_reset2
|
1074 |
|
|
);
|
1075 |
|
|
|
1076 |
|
|
|
1077 |
|
|
|
1078 |
|
|
|
1079 |
|
|
|
1080 |
|
|
|
1081 |
|
|
|
1082 |
|
|
|
1083 |
|
|
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
|
1084 |
|
|
--------------------------------------------------- begin
|
1085 |
|
|
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
|
1086 |
|
|
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
|
1087 |
|
|
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
|
1088 |
|
|
--------------------------------------------------- p_level_out_d2 <= '0';
|
1089 |
|
|
--------------------------------------------------- p_level_out_d3 <= '0';
|
1090 |
|
|
--------------------------------------------------- p_level_out_d4 <= '0';
|
1091 |
|
|
--------------------------------------------------- p_level_out_d5 <= '0';
|
1092 |
|
|
--------------------------------------------------- p_level_out_d6 <= '0';
|
1093 |
|
|
--------------------------------------------------- p_level_out_d7 <= '0';
|
1094 |
|
|
--------------------------------------------------- prmry_ack <= '0';
|
1095 |
|
|
--------------------------------------------------- else
|
1096 |
|
|
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
|
1097 |
|
|
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
|
1098 |
|
|
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
|
1099 |
|
|
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
|
1100 |
|
|
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
|
1101 |
|
|
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
|
1102 |
|
|
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
|
1103 |
|
|
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
|
1104 |
|
|
--------------------------------------------------- end if;
|
1105 |
|
|
--------------------------------------------------- end if;
|
1106 |
|
|
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
|
1107 |
|
|
|
1108 |
|
|
|
1109 |
|
|
|
1110 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
|
1111 |
|
|
generic map(INIT => '0'
|
1112 |
|
|
)port map (
|
1113 |
|
|
Q => p_level_out_d1_cdc_to,
|
1114 |
|
|
C => prmry_aclk,
|
1115 |
|
|
D => scndry_out_int,
|
1116 |
|
|
R => prmry_reset2
|
1117 |
|
|
);
|
1118 |
|
|
|
1119 |
|
|
|
1120 |
|
|
|
1121 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
|
1122 |
|
|
generic map(INIT => '0'
|
1123 |
|
|
)port map (
|
1124 |
|
|
Q => p_level_out_d2,
|
1125 |
|
|
C => prmry_aclk,
|
1126 |
|
|
D => p_level_out_d1_cdc_to,
|
1127 |
|
|
R => prmry_reset2
|
1128 |
|
|
);
|
1129 |
|
|
|
1130 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
|
1131 |
|
|
generic map(INIT => '0'
|
1132 |
|
|
)port map (
|
1133 |
|
|
Q => p_level_out_d3,
|
1134 |
|
|
C => prmry_aclk,
|
1135 |
|
|
D => p_level_out_d2,
|
1136 |
|
|
R => prmry_reset2
|
1137 |
|
|
);
|
1138 |
|
|
|
1139 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
|
1140 |
|
|
generic map(INIT => '0'
|
1141 |
|
|
)port map (
|
1142 |
|
|
Q => p_level_out_d4,
|
1143 |
|
|
C => prmry_aclk,
|
1144 |
|
|
D => p_level_out_d3,
|
1145 |
|
|
R => prmry_reset2
|
1146 |
|
|
);
|
1147 |
|
|
|
1148 |
|
|
|
1149 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
|
1150 |
|
|
generic map(INIT => '0'
|
1151 |
|
|
)port map (
|
1152 |
|
|
Q => p_level_out_d5,
|
1153 |
|
|
C => prmry_aclk,
|
1154 |
|
|
D => p_level_out_d4,
|
1155 |
|
|
R => prmry_reset2
|
1156 |
|
|
);
|
1157 |
|
|
|
1158 |
|
|
|
1159 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
|
1160 |
|
|
generic map(INIT => '0'
|
1161 |
|
|
)port map (
|
1162 |
|
|
Q => p_level_out_d6,
|
1163 |
|
|
C => prmry_aclk,
|
1164 |
|
|
D => p_level_out_d5,
|
1165 |
|
|
R => prmry_reset2
|
1166 |
|
|
);
|
1167 |
|
|
|
1168 |
|
|
|
1169 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
|
1170 |
|
|
generic map(INIT => '0'
|
1171 |
|
|
)port map (
|
1172 |
|
|
Q => p_level_out_d7,
|
1173 |
|
|
C => prmry_aclk,
|
1174 |
|
|
D => p_level_out_d6,
|
1175 |
|
|
R => prmry_reset2
|
1176 |
|
|
);
|
1177 |
|
|
|
1178 |
|
|
|
1179 |
|
|
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
|
1180 |
|
|
generic map(INIT => '0'
|
1181 |
|
|
)port map (
|
1182 |
|
|
Q => prmry_ack,
|
1183 |
|
|
C => prmry_aclk,
|
1184 |
|
|
D => prmry_pulse_ack,
|
1185 |
|
|
R => prmry_reset2
|
1186 |
|
|
);
|
1187 |
|
|
|
1188 |
|
|
|
1189 |
|
|
|
1190 |
|
|
|
1191 |
|
|
|
1192 |
|
|
|
1193 |
|
|
|
1194 |
|
|
|
1195 |
|
|
|
1196 |
|
|
|
1197 |
|
|
|
1198 |
|
|
|
1199 |
|
|
|
1200 |
|
|
|
1201 |
|
|
|
1202 |
|
|
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
|
1203 |
|
|
begin
|
1204 |
|
|
|
1205 |
|
|
scndry_out_int <= s_level_out_d2;
|
1206 |
|
|
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
|
1207 |
|
|
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
|
1208 |
|
|
|
1209 |
|
|
|
1210 |
|
|
end generate MTBF_L2;
|
1211 |
|
|
|
1212 |
|
|
MTBF_L3 : if C_MTBF_STAGES = 3 generate
|
1213 |
|
|
begin
|
1214 |
|
|
|
1215 |
|
|
scndry_out_int <= s_level_out_d3;
|
1216 |
|
|
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
|
1217 |
|
|
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
|
1218 |
|
|
|
1219 |
|
|
|
1220 |
|
|
|
1221 |
|
|
end generate MTBF_L3;
|
1222 |
|
|
|
1223 |
|
|
MTBF_L4 : if C_MTBF_STAGES = 4 generate
|
1224 |
|
|
begin
|
1225 |
|
|
scndry_out_int <= s_level_out_d4;
|
1226 |
|
|
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
|
1227 |
|
|
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
|
1228 |
|
|
|
1229 |
|
|
|
1230 |
|
|
|
1231 |
|
|
end generate MTBF_L4;
|
1232 |
|
|
|
1233 |
|
|
MTBF_L5 : if C_MTBF_STAGES = 5 generate
|
1234 |
|
|
begin
|
1235 |
|
|
|
1236 |
|
|
scndry_out_int <= s_level_out_d5;
|
1237 |
|
|
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
|
1238 |
|
|
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
|
1239 |
|
|
|
1240 |
|
|
|
1241 |
|
|
end generate MTBF_L5;
|
1242 |
|
|
|
1243 |
|
|
MTBF_L6 : if C_MTBF_STAGES = 6 generate
|
1244 |
|
|
begin
|
1245 |
|
|
|
1246 |
|
|
scndry_out_int <= s_level_out_d6;
|
1247 |
|
|
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
|
1248 |
|
|
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
|
1249 |
|
|
|
1250 |
|
|
|
1251 |
|
|
end generate MTBF_L6;
|
1252 |
|
|
|
1253 |
|
|
scndry_out <= scndry_out_int;
|
1254 |
|
|
|
1255 |
|
|
|
1256 |
|
|
end generate GENERATE_LEVEL_ACK_P_S_CDC;
|
1257 |
|
|
|
1258 |
|
|
|
1259 |
|
|
end implementation;
|
1260 |
|
|
|
1261 |
|
|
|
1262 |
|
|
|
1263 |
|
|
|