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vv_gulyaev |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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-- Date : Thu Jul 23 09:43:35 2020
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-- Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
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-- Command : write_vhdl -force -mode funcsim -rename_top clk_gen -prefix
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-- clk_gen_ clk_gen_sim_netlist.vhdl
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-- Design : clk_gen
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-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
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-- synthesized. This netlist cannot be used for SDF annotated simulation.
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-- Device : xc7k325tffg900-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity clk_gen_clk_gen_clk_wiz is
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port (
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clk_out1 : out STD_LOGIC;
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reset : in STD_LOGIC;
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locked : out STD_LOGIC;
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clk_in1_p : in STD_LOGIC;
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clk_in1_n : in STD_LOGIC
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);
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end clk_gen_clk_gen_clk_wiz;
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architecture STRUCTURE of clk_gen_clk_gen_clk_wiz is
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signal clk_in1_clk_gen : STD_LOGIC;
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signal clk_out1_clk_gen : STD_LOGIC;
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signal clkfbout_buf_clk_gen : STD_LOGIC;
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signal clkfbout_clk_gen : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
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signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
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attribute BOX_TYPE : string;
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attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
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attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE";
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attribute CAPACITANCE : string;
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attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE";
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attribute IBUF_DELAY_VALUE : string;
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attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0";
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attribute IFD_DELAY_VALUE : string;
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attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO";
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attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
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attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
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begin
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clkf_buf: unisim.vcomponents.BUFG
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port map (
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I => clkfbout_clk_gen,
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O => clkfbout_buf_clk_gen
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);
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clkin1_ibufgds: unisim.vcomponents.IBUFDS
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generic map(
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IOSTANDARD => "DEFAULT"
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)
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port map (
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I => clk_in1_p,
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IB => clk_in1_n,
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O => clk_in1_clk_gen
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);
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clkout1_buf: unisim.vcomponents.BUFG
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port map (
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I => clk_out1_clk_gen,
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O => clk_out1
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);
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mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
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generic map(
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BANDWIDTH => "OPTIMIZED",
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CLKFBOUT_MULT_F => 5.000000,
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CLKFBOUT_PHASE => 0.000000,
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CLKFBOUT_USE_FINE_PS => false,
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CLKIN1_PERIOD => 5.000000,
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CLKIN2_PERIOD => 0.000000,
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CLKOUT0_DIVIDE_F => 10.000000,
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CLKOUT0_DUTY_CYCLE => 0.500000,
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CLKOUT0_PHASE => 0.000000,
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CLKOUT0_USE_FINE_PS => false,
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CLKOUT1_DIVIDE => 1,
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CLKOUT1_DUTY_CYCLE => 0.500000,
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CLKOUT1_PHASE => 0.000000,
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CLKOUT1_USE_FINE_PS => false,
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CLKOUT2_DIVIDE => 1,
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CLKOUT2_DUTY_CYCLE => 0.500000,
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CLKOUT2_PHASE => 0.000000,
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CLKOUT2_USE_FINE_PS => false,
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CLKOUT3_DIVIDE => 1,
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CLKOUT3_DUTY_CYCLE => 0.500000,
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CLKOUT3_PHASE => 0.000000,
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CLKOUT3_USE_FINE_PS => false,
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CLKOUT4_CASCADE => false,
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CLKOUT4_DIVIDE => 1,
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CLKOUT4_DUTY_CYCLE => 0.500000,
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CLKOUT4_PHASE => 0.000000,
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CLKOUT4_USE_FINE_PS => false,
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CLKOUT5_DIVIDE => 1,
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CLKOUT5_DUTY_CYCLE => 0.500000,
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CLKOUT5_PHASE => 0.000000,
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CLKOUT5_USE_FINE_PS => false,
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CLKOUT6_DIVIDE => 1,
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CLKOUT6_DUTY_CYCLE => 0.500000,
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CLKOUT6_PHASE => 0.000000,
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CLKOUT6_USE_FINE_PS => false,
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COMPENSATION => "ZHOLD",
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DIVCLK_DIVIDE => 1,
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IS_CLKINSEL_INVERTED => '0',
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IS_PSEN_INVERTED => '0',
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IS_PSINCDEC_INVERTED => '0',
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IS_PWRDWN_INVERTED => '0',
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IS_RST_INVERTED => '0',
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REF_JITTER1 => 0.010000,
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REF_JITTER2 => 0.010000,
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SS_EN => "FALSE",
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SS_MODE => "CENTER_HIGH",
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SS_MOD_PERIOD => 10000,
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STARTUP_WAIT => false
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)
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port map (
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CLKFBIN => clkfbout_buf_clk_gen,
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CLKFBOUT => clkfbout_clk_gen,
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CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
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CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
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CLKIN1 => clk_in1_clk_gen,
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CLKIN2 => '0',
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CLKINSEL => '1',
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CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
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CLKOUT0 => clk_out1_clk_gen,
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CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
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CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
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CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
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CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
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CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
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CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
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CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
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CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
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CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
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CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
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DADDR(6 downto 0) => B"0000000",
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DCLK => '0',
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DEN => '0',
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DI(15 downto 0) => B"0000000000000000",
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DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
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DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
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DWE => '0',
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LOCKED => locked,
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PSCLK => '0',
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PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
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PSEN => '0',
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PSINCDEC => '0',
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PWRDWN => '0',
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RST => reset
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);
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end STRUCTURE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity clk_gen is
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port (
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clk_out1 : out STD_LOGIC;
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reset : in STD_LOGIC;
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locked : out STD_LOGIC;
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clk_in1_p : in STD_LOGIC;
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clk_in1_n : in STD_LOGIC
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);
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attribute NotValidForBitStream : boolean;
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attribute NotValidForBitStream of clk_gen : entity is true;
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end clk_gen;
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architecture STRUCTURE of clk_gen is
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begin
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inst: entity work.clk_gen_clk_gen_clk_wiz
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port map (
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clk_in1_n => clk_in1_n,
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clk_in1_p => clk_in1_p,
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clk_out1 => clk_out1,
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locked => locked,
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reset => reset
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);
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end STRUCTURE;
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