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vv_gulyaev |
///////////////////////////////////////////////////////////////////////////////
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//
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// Company: Xilinx
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// Engineer: Jim Tatsukawa
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// Date: 6/15/2015
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// Design Name: PLLE3 DRP
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// Module Name: plle3_drp_func.h
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// Version: 1.10
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// Target Devices: UltraScale Architecture
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// Tool versions: 2015.1
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// Description: This header provides the functions necessary to
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// calculate the DRP register values for the V6 PLL.
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//
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// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
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// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
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// PM_Rise bits have been removed for PLLE3
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//
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// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
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// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
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// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
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// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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// APPLICATION OR STANDARD, XILINX IS MAKING NO
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// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
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// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
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// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
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// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
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// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
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// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
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// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE.
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//
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// (c) Copyright 2009-2010 Xilinx, Inc.
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// All rights reserved.
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//
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///////////////////////////////////////////////////////////////////////////////
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// These are user functions that should not be modified. Changes to the defines
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// or code within the functions may alter the accuracy of the calculations.
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// Define debug to provide extra messages durring elaboration
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//`define DEBUG 1
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// FRAC_PRECISION describes the width of the fractional portion of the fixed
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// point numbers. These should not be modified, they are for development
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// only
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`define FRAC_PRECISION 10
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// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
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// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
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// greater than 32
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`define FIXED_WIDTH 32
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// This function takes a fixed point number and rounds it to the nearest
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// fractional precision bit.
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function [`FIXED_WIDTH:1] round_frac
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(
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// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
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input [`FIXED_WIDTH:1] decimal,
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// This describes the precision of the fraction, for example a value
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// of 1 would modify the fractional so that instead of being a .16
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// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
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input [`FIXED_WIDTH:1] precision
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);
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begin
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`ifdef DEBUG
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$display("round_frac - decimal: %h, precision: %h", decimal, precision);
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`endif
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// If the fractional precision bit is high then round up
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if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
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round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
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end else begin
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round_frac = decimal;
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end
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`ifdef DEBUG
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$display("round_frac: %h", round_frac);
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`endif
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end
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endfunction
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// This function calculates high_time, low_time, w_edge, and no_count
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// of a non-fractional counter based on the divide and duty cycle
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//
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// NOTE: high_time and low_time are returned as integers between 0 and 63
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// inclusive. 64 should equal 6'b000000 (in other words it is okay to
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// ignore the overflow)
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function [13:0] mmcm_pll_divider
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(
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input [7:0] divide, // Max divide is 128
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input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
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);
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reg [`FIXED_WIDTH:1] duty_cycle_fix;
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// High/Low time is initially calculated with a wider integer to prevent a
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// calculation error when it overflows to 64.
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reg [6:0] high_time;
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reg [6:0] low_time;
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reg w_edge;
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reg no_count;
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reg [`FIXED_WIDTH:1] temp;
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begin
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// Duty Cycle must be between 0 and 1,000
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if(duty_cycle <=0 || duty_cycle >= 100000) begin
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$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
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$finish;
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end
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// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
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duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
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`ifdef DEBUG
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$display("duty_cycle_fix: %h", duty_cycle_fix);
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`endif
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// If the divide is 1 nothing needs to be set except the no_count bit.
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// Other values are dummies
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if(divide == 7'h01) begin
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high_time = 7'h01;
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w_edge = 1'b0;
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low_time = 7'h01;
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no_count = 1'b1;
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end else begin
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temp = round_frac(duty_cycle_fix*divide, 1);
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// comes from above round_frac
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high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
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// If the duty cycle * divide rounded is .5 or greater then this bit
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// is set.
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w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
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// If the high time comes out to 0, it needs to be set to at least 1
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// and w_edge set to 0
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if(high_time == 7'h00) begin
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high_time = 7'h01;
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w_edge = 1'b0;
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end
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if(high_time == divide) begin
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high_time = divide - 1;
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w_edge = 1'b1;
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end
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// Calculate low_time based on the divide setting and set no_count to
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// 0 as it is only used when divide is 1.
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low_time = divide - high_time;
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no_count = 1'b0;
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end
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// Set the return value.
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mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
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end
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endfunction
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// This function calculates mx, delay_time, and phase_mux
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// of a non-fractional counter based on the divide and phase
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//
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// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
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// is used.
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function [10:0] mmcm_pll_phase
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(
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// divide must be an integer (use fractional if not)
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// assumed that divide already checked to be valid
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input [7:0] divide, // Max divide is 128
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// Phase is given in degrees (-360,000 to 360,000)
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input signed [31:0] phase
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);
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reg [`FIXED_WIDTH:1] phase_in_cycles;
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reg [`FIXED_WIDTH:1] phase_fixed;
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reg [1:0] mx;
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reg [5:0] delay_time;
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reg [2:0] phase_mux;
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reg [`FIXED_WIDTH:1] temp;
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begin
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`ifdef DEBUG
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$display("mmcm_pll_phase-divide:%d,phase:%d",
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divide, phase);
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`endif
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if ((phase < -360000) || (phase > 360000)) begin
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$display("ERROR: phase of $phase is not between -360000 and 360000");
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$finish;
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end
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// If phase is less than 0, convert it to a positive phase shift
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// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
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if(phase < 0) begin
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phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
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end else begin
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phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
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end
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// Put phase in terms of decimal number of vco clock cycles
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phase_in_cycles = ( phase_fixed * divide ) / 360;
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`ifdef DEBUG
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$display("phase_in_cycles: %h", phase_in_cycles);
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`endif
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temp = round_frac(phase_in_cycles, 3);
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// set mx to 2'b00 that the phase mux from the VCO is enabled
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mx = 2'b00;
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phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
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delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
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`ifdef DEBUG
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$display("temp: %h", temp);
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`endif
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// Setup the return value
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mmcm_pll_phase={mx, phase_mux, delay_time};
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end
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endfunction
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// This function takes the divide value and outputs the necessary lock values
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function [39:0] mmcm_pll_lock_lookup
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(
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input [6:0] divide // Max divide is 64
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);
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reg [759:0] lookup;
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begin
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lookup = {
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// This table is composed of:
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// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
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40'b00110_00110_1111101000_1111101001_0000000001, //1
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40'b00110_00110_1111101000_1111101001_0000000001, //2
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40'b01000_01000_1111101000_1111101001_0000000001, //3
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40'b01011_01011_1111101000_1111101001_0000000001, //4
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40'b01110_01110_1111101000_1111101001_0000000001, //5
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40'b10001_10001_1111101000_1111101001_0000000001, //6
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40'b10011_10011_1111101000_1111101001_0000000001, //7
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40'b10110_10110_1111101000_1111101001_0000000001, //8
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40'b11001_11001_1111101000_1111101001_0000000001, //9
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40'b11100_11100_1111101000_1111101001_0000000001, //10
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40'b11111_11111_1110000100_1111101001_0000000001, //11
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40'b11111_11111_1100111001_1111101001_0000000001, //12
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40'b11111_11111_1011101110_1111101001_0000000001, //13
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40'b11111_11111_1010111100_1111101001_0000000001, //14
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40'b11111_11111_1010001010_1111101001_0000000001, //15
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40'b11111_11111_1001110001_1111101001_0000000001, //16
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40'b11111_11111_1000111111_1111101001_0000000001, //17
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40'b11111_11111_1000100110_1111101001_0000000001, //18
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40'b11111_11111_1000001101_1111101001_0000000001 //19
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};
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// Set lookup_entry with the explicit bits from lookup with a part select
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mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
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`ifdef DEBUG
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$display("lock_lookup: %b", mmcm_pll_lock_lookup);
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`endif
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end
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endfunction
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// This function takes the divide value and the bandwidth setting of the PLL
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// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
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function [9:0] mmcm_pll_filter_lookup
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(
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input [6:0] divide // Max divide is 19
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);
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reg [639:0] lookup;
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reg [9:0] lookup_entry;
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begin
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lookup = {
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// CP_RES_LFHF
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10'b0010_1111_01, //1
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10'b0010_0011_11, //2
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10'b0011_0011_11, //3
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10'b0010_0001_11, //4
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10'b0010_0110_11, //5
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10'b0010_1010_11, //6
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10'b0010_1010_11, //7
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10'b0011_0110_11, //8
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10'b0010_1100_11, //9
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10'b0010_1100_11, //10
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10'b0010_1100_11, //11
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10'b0010_0010_11, //12
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10'b0011_1100_11, //13
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10'b0011_1100_11, //14
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10'b0011_1100_11, //15
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10'b0011_1100_11, //16
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10'b0011_0010_11, //17
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10'b0011_0010_11, //18
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10'b0011_0010_11 //19
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};
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mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
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`ifdef DEBUG
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$display("filter_lookup: %b", mmcm_pll_filter_lookup);
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`endif
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end
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endfunction
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// This function set the CLKOUTPHY divide settings to match
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// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
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// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
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// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
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function [9:0] mmcm_pll_clkoutphy_calc
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(
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input [8*9:0] CLKOUTPHY_MODE
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);
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if(CLKOUTPHY_MODE == "VCO_X2") begin
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mmcm_pll_clkoutphy_calc= 2'b00;
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end else if(CLKOUTPHY_MODE == "VCO") begin
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mmcm_pll_clkoutphy_calc= 2'b01;
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end else if(CLKOUTPHY_MODE == "CLKIN") begin
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mmcm_pll_clkoutphy_calc= 2'b11;
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end else begin // Assume "VCO_HALF"
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mmcm_pll_clkoutphy_calc= 2'b10;
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end
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endfunction
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// This function takes in the divide, phase, and duty cycle
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// setting to calculate the upper and lower counter registers.
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function [37:0] mmcm_pll_count_calc
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338 |
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(
|
339 |
|
|
input [7:0] divide, // Max divide is 128
|
340 |
|
|
input signed [31:0] phase,
|
341 |
|
|
input [31:0] duty_cycle // Multiplied by 100,000
|
342 |
|
|
);
|
343 |
|
|
|
344 |
|
|
reg [13:0] div_calc;
|
345 |
|
|
reg [16:0] phase_calc;
|
346 |
|
|
|
347 |
|
|
begin
|
348 |
|
|
`ifdef DEBUG
|
349 |
|
|
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
350 |
|
|
divide, phase, duty_cycle);
|
351 |
|
|
`endif
|
352 |
|
|
|
353 |
|
|
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
354 |
|
|
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
355 |
|
|
// mx[10:9], pm[8:6], dt[5:0]
|
356 |
|
|
phase_calc = mmcm_pll_phase(divide, phase);
|
357 |
|
|
|
358 |
|
|
// Return value is the upper and lower address of counter
|
359 |
|
|
// Upper address is:
|
360 |
|
|
// RESERVED [31:26]
|
361 |
|
|
// MX [25:24]
|
362 |
|
|
// EDGE [23]
|
363 |
|
|
// NOCOUNT [22]
|
364 |
|
|
// DELAY_TIME [21:16]
|
365 |
|
|
// Lower Address is:
|
366 |
|
|
// PHASE_MUX [15:13]
|
367 |
|
|
// RESERVED [12]
|
368 |
|
|
// HIGH_TIME [11:6]
|
369 |
|
|
// LOW_TIME [5:0]
|
370 |
|
|
|
371 |
|
|
`ifdef DEBUG
|
372 |
|
|
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
373 |
|
|
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
374 |
|
|
div_calc[13], div_calc[12],
|
375 |
|
|
phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
|
376 |
|
|
`endif
|
377 |
|
|
|
378 |
|
|
mmcm_pll_count_calc =
|
379 |
|
|
{
|
380 |
|
|
// Upper Address
|
381 |
|
|
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
382 |
|
|
// Lower Address
|
383 |
|
|
phase_calc[8:6], 1'b0, div_calc[11:0]
|
384 |
|
|
};
|
385 |
|
|
end
|
386 |
|
|
endfunction
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
// This function takes in the divide, phase, and duty cycle
|
390 |
|
|
// setting to calculate the upper and lower counter registers.
|
391 |
|
|
// for fractional multiply/divide functions.
|
392 |
|
|
//
|
393 |
|
|
//
|
394 |
|
|
function [37:0] mmcm_pll_frac_count_calc
|
395 |
|
|
(
|
396 |
|
|
input [7:0] divide, // Max divide is 128
|
397 |
|
|
input signed [31:0] phase,
|
398 |
|
|
input [31:0] duty_cycle, // Multiplied by 1,000
|
399 |
|
|
input [9:0] frac // Multiplied by 1000
|
400 |
|
|
);
|
401 |
|
|
|
402 |
|
|
//Required for fractional divide calculations
|
403 |
|
|
reg [7:0] lt_frac;
|
404 |
|
|
reg [7:0] ht_frac;
|
405 |
|
|
|
406 |
|
|
reg /*[7:0]*/ wf_fall_frac;
|
407 |
|
|
reg /*[7:0]*/ wf_rise_frac;
|
408 |
|
|
|
409 |
|
|
reg [31:0] a;
|
410 |
|
|
reg [7:0] pm_rise_frac_filtered ;
|
411 |
|
|
reg [7:0] pm_fall_frac_filtered ;
|
412 |
|
|
reg [7:0] clkout0_divide_int;
|
413 |
|
|
reg [2:0] clkout0_divide_frac;
|
414 |
|
|
reg [7:0] even_part_high;
|
415 |
|
|
reg [7:0] even_part_low;
|
416 |
|
|
|
417 |
|
|
reg [7:0] odd;
|
418 |
|
|
reg [7:0] odd_and_frac;
|
419 |
|
|
|
420 |
|
|
reg [7:0] pm_fall;
|
421 |
|
|
reg [7:0] pm_rise;
|
422 |
|
|
reg [7:0] dt;
|
423 |
|
|
reg [7:0] dt_int;
|
424 |
|
|
reg [63:0] dt_calc;
|
425 |
|
|
|
426 |
|
|
reg [7:0] pm_rise_frac;
|
427 |
|
|
reg [7:0] pm_fall_frac;
|
428 |
|
|
|
429 |
|
|
reg [31:0] a_per_in_octets;
|
430 |
|
|
reg [31:0] a_phase_in_cycles;
|
431 |
|
|
|
432 |
|
|
parameter precision = 0.125;
|
433 |
|
|
|
434 |
|
|
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
435 |
|
|
reg [31: 0] phase_pos;
|
436 |
|
|
reg [31: 0] phase_vco;
|
437 |
|
|
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
438 |
|
|
reg [13:0] div_calc;
|
439 |
|
|
reg [16:0] phase_calc;
|
440 |
|
|
|
441 |
|
|
begin
|
442 |
|
|
`ifdef DEBUG
|
443 |
|
|
$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
444 |
|
|
divide, phase, duty_cycle);
|
445 |
|
|
`endif
|
446 |
|
|
|
447 |
|
|
//convert phase to fixed
|
448 |
|
|
if ((phase < -360000) || (phase > 360000)) begin
|
449 |
|
|
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
450 |
|
|
$finish;
|
451 |
|
|
end
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
// Return value is
|
455 |
|
|
// Transfer data
|
456 |
|
|
// RESERVED [37:36]
|
457 |
|
|
// FRAC_TIME [35:33]
|
458 |
|
|
// FRAC_WF_FALL [32]
|
459 |
|
|
// Upper address is:
|
460 |
|
|
// RESERVED [31:26]
|
461 |
|
|
// MX [25:24]
|
462 |
|
|
// EDGE [23]
|
463 |
|
|
// NOCOUNT [22]
|
464 |
|
|
// DELAY_TIME [21:16]
|
465 |
|
|
// Lower Address is:
|
466 |
|
|
// PHASE_MUX [15:13]
|
467 |
|
|
// RESERVED [12]
|
468 |
|
|
// HIGH_TIME [11:6]
|
469 |
|
|
// LOW_TIME [5:0]
|
470 |
|
|
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
clkout0_divide_frac = frac / 125;
|
474 |
|
|
clkout0_divide_int = divide;
|
475 |
|
|
|
476 |
|
|
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
477 |
|
|
even_part_low = even_part_high;
|
478 |
|
|
|
479 |
|
|
odd = clkout0_divide_int - even_part_high - even_part_low;
|
480 |
|
|
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
481 |
|
|
|
482 |
|
|
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
483 |
|
|
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
484 |
|
|
|
485 |
|
|
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
486 |
|
|
pm_rise = 0; //0
|
487 |
|
|
|
488 |
|
|
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
489 |
|
|
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
//Calculate phase in fractional cycles
|
494 |
|
|
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
495 |
|
|
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
496 |
|
|
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
497 |
|
|
|
498 |
|
|
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
499 |
|
|
dt = dt_calc[7:0];
|
500 |
|
|
|
501 |
|
|
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
502 |
|
|
|
503 |
|
|
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
504 |
|
|
pm_fall_frac = pm_fall + pm_rise_frac;
|
505 |
|
|
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
506 |
|
|
|
507 |
|
|
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
508 |
|
|
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
509 |
|
|
|
510 |
|
|
mmcm_pll_frac_count_calc[37:0] =
|
511 |
|
|
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
512 |
|
|
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
513 |
|
|
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
514 |
|
|
// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
515 |
|
|
} ;
|
516 |
|
|
|
517 |
|
|
`ifdef DEBUG
|
518 |
|
|
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
519 |
|
|
`endif
|
520 |
|
|
|
521 |
|
|
end
|
522 |
|
|
endfunction
|
523 |
|
|
|
524 |
|
|
|