1 |
2 |
vv_gulyaev |
///////////////////////////////////////////////////////////////////////////////
|
2 |
|
|
//
|
3 |
|
|
// Company: Xilinx
|
4 |
|
|
// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
|
5 |
|
|
// Date: 6/15/2015
|
6 |
|
|
// Design Name: PLLE4 DRP
|
7 |
|
|
// Module Name: plle4_drp_func.h
|
8 |
|
|
// Version: 2.0
|
9 |
|
|
// Target Devices: UltraScale+ Architecture
|
10 |
|
|
// Tool versions: 2017.1
|
11 |
|
|
// Description: This header provides the functions necessary to
|
12 |
|
|
// calculate the DRP register values for the V6 PLL.
|
13 |
|
|
//
|
14 |
|
|
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
15 |
|
|
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
16 |
|
|
// M_Rise bits have been removed for PLLE3
|
17 |
|
|
// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
|
18 |
|
|
// Ultrascale+ and for max M of 21
|
19 |
|
|
//
|
20 |
|
|
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
21 |
|
|
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
22 |
|
|
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
23 |
|
|
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
24 |
|
|
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
25 |
|
|
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
26 |
|
|
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
27 |
|
|
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
28 |
|
|
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
29 |
|
|
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
30 |
|
|
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
31 |
|
|
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
32 |
|
|
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
33 |
|
|
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
34 |
|
|
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
35 |
|
|
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
36 |
|
|
// PURPOSE.
|
37 |
|
|
//
|
38 |
|
|
// (c) Copyright 2009-2017 Xilinx, Inc.
|
39 |
|
|
// All rights reserved.
|
40 |
|
|
//
|
41 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
42 |
|
|
|
43 |
|
|
// These are user functions that should not be modified. Changes to the defines
|
44 |
|
|
// or code within the functions may alter the accuracy of the calculations.
|
45 |
|
|
|
46 |
|
|
// Define debug to provide extra messages durring elaboration
|
47 |
|
|
//`define DEBUG 1
|
48 |
|
|
|
49 |
|
|
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
50 |
|
|
// point numbers. These should not be modified, they are for development
|
51 |
|
|
// only
|
52 |
|
|
`define FRAC_PRECISION 10
|
53 |
|
|
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
54 |
|
|
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
55 |
|
|
// greater than 32
|
56 |
|
|
`define FIXED_WIDTH 32
|
57 |
|
|
|
58 |
|
|
// This function takes a fixed point number and rounds it to the nearest
|
59 |
|
|
// fractional precision bit.
|
60 |
|
|
function [`FIXED_WIDTH:1] round_frac
|
61 |
|
|
(
|
62 |
|
|
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
63 |
|
|
input [`FIXED_WIDTH:1] decimal,
|
64 |
|
|
|
65 |
|
|
// This describes the precision of the fraction, for example a value
|
66 |
|
|
// of 1 would modify the fractional so that instead of being a .16
|
67 |
|
|
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
68 |
|
|
input [`FIXED_WIDTH:1] precision
|
69 |
|
|
);
|
70 |
|
|
|
71 |
|
|
begin
|
72 |
|
|
|
73 |
|
|
`ifdef DEBUG
|
74 |
|
|
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
75 |
|
|
`endif
|
76 |
|
|
// If the fractional precision bit is high then round up
|
77 |
|
|
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
78 |
|
|
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
79 |
|
|
end else begin
|
80 |
|
|
round_frac = decimal;
|
81 |
|
|
end
|
82 |
|
|
`ifdef DEBUG
|
83 |
|
|
$display("round_frac: %h", round_frac);
|
84 |
|
|
`endif
|
85 |
|
|
end
|
86 |
|
|
endfunction
|
87 |
|
|
|
88 |
|
|
// This function calculates high_time, low_time, w_edge, and no_count
|
89 |
|
|
// of a non-fractional counter based on the divide and duty cycle
|
90 |
|
|
//
|
91 |
|
|
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
92 |
|
|
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
93 |
|
|
// ignore the overflow)
|
94 |
|
|
function [13:0] mmcm_pll_divider
|
95 |
|
|
(
|
96 |
|
|
input [7:0] divide, // Max divide is 128
|
97 |
|
|
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
98 |
|
|
);
|
99 |
|
|
|
100 |
|
|
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
101 |
|
|
|
102 |
|
|
// High/Low time is initially calculated with a wider integer to prevent a
|
103 |
|
|
// calculation error when it overflows to 64.
|
104 |
|
|
reg [6:0] high_time;
|
105 |
|
|
reg [6:0] low_time;
|
106 |
|
|
reg w_edge;
|
107 |
|
|
reg no_count;
|
108 |
|
|
|
109 |
|
|
reg [`FIXED_WIDTH:1] temp;
|
110 |
|
|
|
111 |
|
|
begin
|
112 |
|
|
// Duty Cycle must be between 0 and 1,000
|
113 |
|
|
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
114 |
|
|
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
115 |
|
|
$finish;
|
116 |
|
|
end
|
117 |
|
|
|
118 |
|
|
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
119 |
|
|
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
120 |
|
|
|
121 |
|
|
`ifdef DEBUG
|
122 |
|
|
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
123 |
|
|
`endif
|
124 |
|
|
|
125 |
|
|
// If the divide is 1 nothing needs to be set except the no_count bit.
|
126 |
|
|
// Other values are dummies
|
127 |
|
|
if(divide == 7'h01) begin
|
128 |
|
|
high_time = 7'h01;
|
129 |
|
|
w_edge = 1'b0;
|
130 |
|
|
low_time = 7'h01;
|
131 |
|
|
no_count = 1'b1;
|
132 |
|
|
end else begin
|
133 |
|
|
temp = round_frac(duty_cycle_fix*divide, 1);
|
134 |
|
|
|
135 |
|
|
// comes from above round_frac
|
136 |
|
|
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
137 |
|
|
// If the duty cycle * divide rounded is .5 or greater then this bit
|
138 |
|
|
// is set.
|
139 |
|
|
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
140 |
|
|
|
141 |
|
|
// If the high time comes out to 0, it needs to be set to at least 1
|
142 |
|
|
// and w_edge set to 0
|
143 |
|
|
if(high_time == 7'h00) begin
|
144 |
|
|
high_time = 7'h01;
|
145 |
|
|
w_edge = 1'b0;
|
146 |
|
|
end
|
147 |
|
|
|
148 |
|
|
if(high_time == divide) begin
|
149 |
|
|
high_time = divide - 1;
|
150 |
|
|
w_edge = 1'b1;
|
151 |
|
|
end
|
152 |
|
|
|
153 |
|
|
// Calculate low_time based on the divide setting and set no_count to
|
154 |
|
|
// 0 as it is only used when divide is 1.
|
155 |
|
|
low_time = divide - high_time;
|
156 |
|
|
no_count = 1'b0;
|
157 |
|
|
end
|
158 |
|
|
|
159 |
|
|
// Set the return value.
|
160 |
|
|
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
161 |
|
|
end
|
162 |
|
|
endfunction
|
163 |
|
|
|
164 |
|
|
// This function calculates mx, delay_time, and phase_mux
|
165 |
|
|
// of a non-fractional counter based on the divide and phase
|
166 |
|
|
//
|
167 |
|
|
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
168 |
|
|
// is used.
|
169 |
|
|
function [10:0] mmcm_pll_phase
|
170 |
|
|
(
|
171 |
|
|
// divide must be an integer (use fractional if not)
|
172 |
|
|
// assumed that divide already checked to be valid
|
173 |
|
|
input [7:0] divide, // Max divide is 128
|
174 |
|
|
|
175 |
|
|
// Phase is given in degrees (-360,000 to 360,000)
|
176 |
|
|
input signed [31:0] phase
|
177 |
|
|
);
|
178 |
|
|
|
179 |
|
|
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
180 |
|
|
reg [`FIXED_WIDTH:1] phase_fixed;
|
181 |
|
|
reg [1:0] mx;
|
182 |
|
|
reg [5:0] delay_time;
|
183 |
|
|
reg [2:0] phase_mux;
|
184 |
|
|
|
185 |
|
|
reg [`FIXED_WIDTH:1] temp;
|
186 |
|
|
|
187 |
|
|
begin
|
188 |
|
|
`ifdef DEBUG
|
189 |
|
|
$display("pll_phase-divide:%d,phase:%d",
|
190 |
|
|
divide, phase);
|
191 |
|
|
`endif
|
192 |
|
|
|
193 |
|
|
if ((phase < -360000) || (phase > 360000)) begin
|
194 |
|
|
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
195 |
|
|
$finish;
|
196 |
|
|
end
|
197 |
|
|
|
198 |
|
|
// If phase is less than 0, convert it to a positive phase shift
|
199 |
|
|
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
200 |
|
|
if(phase < 0) begin
|
201 |
|
|
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
202 |
|
|
end else begin
|
203 |
|
|
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
204 |
|
|
end
|
205 |
|
|
|
206 |
|
|
// Put phase in terms of decimal number of vco clock cycles
|
207 |
|
|
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
208 |
|
|
|
209 |
|
|
`ifdef DEBUG
|
210 |
|
|
$display("phase_in_cycles: %h", phase_in_cycles);
|
211 |
|
|
`endif
|
212 |
|
|
|
213 |
|
|
|
214 |
|
|
temp = round_frac(phase_in_cycles, 3);
|
215 |
|
|
|
216 |
|
|
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
217 |
|
|
mx = 2'b00;
|
218 |
|
|
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
219 |
|
|
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
220 |
|
|
|
221 |
|
|
`ifdef DEBUG
|
222 |
|
|
$display("temp: %h", temp);
|
223 |
|
|
`endif
|
224 |
|
|
|
225 |
|
|
// Setup the return value
|
226 |
|
|
mmcm_pll_phase={mx, phase_mux, delay_time};
|
227 |
|
|
end
|
228 |
|
|
endfunction
|
229 |
|
|
|
230 |
|
|
// This function takes the divide value and outputs the necessary lock values
|
231 |
|
|
function [39:0] mmcm_pll_lock_lookup
|
232 |
|
|
(
|
233 |
|
|
input [6:0] divide // Max divide is 21
|
234 |
|
|
);
|
235 |
|
|
|
236 |
|
|
reg [839:0] lookup;
|
237 |
|
|
|
238 |
|
|
begin
|
239 |
|
|
lookup = {
|
240 |
|
|
// This table is composed of:
|
241 |
|
|
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
242 |
|
|
40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
|
243 |
|
|
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
244 |
|
|
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
245 |
|
|
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
246 |
|
|
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
247 |
|
|
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
248 |
|
|
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
249 |
|
|
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
250 |
|
|
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
251 |
|
|
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
252 |
|
|
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
253 |
|
|
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
254 |
|
|
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
255 |
|
|
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
256 |
|
|
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
257 |
|
|
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
258 |
|
|
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
259 |
|
|
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
260 |
|
|
40'b11111_11111_1000001101_1111101001_0000000001, //19
|
261 |
|
|
40'b11111_11111_0111110100_1111101001_0000000001, //20
|
262 |
|
|
40'b11111_11111_0111011011_1111101001_0000000001 //21
|
263 |
|
|
};
|
264 |
|
|
|
265 |
|
|
// Set lookup_entry with the explicit bits from lookup with a part select
|
266 |
|
|
mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
|
267 |
|
|
`ifdef DEBUG
|
268 |
|
|
$display("lock_lookup: %b", pll_lock_lookup);
|
269 |
|
|
`endif
|
270 |
|
|
end
|
271 |
|
|
endfunction
|
272 |
|
|
|
273 |
|
|
// This function takes the divide value and the bandwidth setting of the PLL
|
274 |
|
|
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
275 |
|
|
function [9:0] mmcm_pll_filter_lookup
|
276 |
|
|
(
|
277 |
|
|
input [6:0] divide // Max divide is 21
|
278 |
|
|
);
|
279 |
|
|
|
280 |
|
|
reg [209:0] lookup;
|
281 |
|
|
reg [9:0] lookup_entry;
|
282 |
|
|
|
283 |
|
|
begin
|
284 |
|
|
|
285 |
|
|
lookup = {
|
286 |
|
|
// CP_RES_LFHF
|
287 |
|
|
10'b0011_0111_11, //1 not legal in Ultrascale+
|
288 |
|
|
10'b0011_0111_11, //2
|
289 |
|
|
10'b0011_0011_11, //3
|
290 |
|
|
10'b0011_1001_11, //4
|
291 |
|
|
10'b0011_0001_11, //5
|
292 |
|
|
10'b0100_1110_11, //6
|
293 |
|
|
10'b0011_0110_11, //7
|
294 |
|
|
10'b0011_1010_11, //8
|
295 |
|
|
10'b0111_1001_11, //9
|
296 |
|
|
10'b0111_1001_11, //10
|
297 |
|
|
10'b0101_0110_11, //11
|
298 |
|
|
10'b1100_0101_11, //12
|
299 |
|
|
10'b0101_1010_11, //13
|
300 |
|
|
10'b0110_0110_11, //14
|
301 |
|
|
10'b0110_1010_11, //15
|
302 |
|
|
10'b0111_0110_11, //16
|
303 |
|
|
10'b1111_0101_11, //17
|
304 |
|
|
10'b1100_0110_11, //18
|
305 |
|
|
10'b1110_0001_11, //19
|
306 |
|
|
10'b1101_0110_11, //20
|
307 |
|
|
10'b1111_0001_11 //21
|
308 |
|
|
};
|
309 |
|
|
|
310 |
|
|
mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
|
311 |
|
|
|
312 |
|
|
`ifdef DEBUG
|
313 |
|
|
$display("filter_lookup: %b", pll_filter_lookup);
|
314 |
|
|
`endif
|
315 |
|
|
end
|
316 |
|
|
endfunction
|
317 |
|
|
|
318 |
|
|
// This function set the CLKOUTPHY divide settings to match
|
319 |
|
|
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
320 |
|
|
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
321 |
|
|
// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
|
322 |
|
|
// will need to divide the doubled clock VCO clock frequency by
|
323 |
|
|
// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
|
324 |
|
|
// need to divide the doubled VCO by 4, therefore 2'b10
|
325 |
|
|
function [9:0] mmcm_pll_clkoutphy_calc
|
326 |
|
|
(
|
327 |
|
|
input [8*9:0] CLKOUTPHY_MODE
|
328 |
|
|
);
|
329 |
|
|
|
330 |
|
|
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
331 |
|
|
mmcm_pll_clkoutphy_calc= 2'b00;
|
332 |
|
|
end else if(CLKOUTPHY_MODE == "VCO") begin
|
333 |
|
|
mmcm_pll_clkoutphy_calc= 2'b01;
|
334 |
|
|
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
335 |
|
|
mmcm_pll_clkoutphy_calc= 2'b11;
|
336 |
|
|
end else begin // Assume "VCO_HALF"
|
337 |
|
|
mmcm_pll_clkoutphy_calc= 2'b10;
|
338 |
|
|
end
|
339 |
|
|
|
340 |
|
|
endfunction
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
// This function takes in the divide, phase, and duty cycle
|
344 |
|
|
// setting to calculate the upper and lower counter registers.
|
345 |
|
|
function [37:0] mmcm_pll_count_calc
|
346 |
|
|
(
|
347 |
|
|
input [7:0] divide, // Max divide is 128
|
348 |
|
|
input signed [31:0] phase,
|
349 |
|
|
input [31:0] duty_cycle // Multiplied by 100,000
|
350 |
|
|
);
|
351 |
|
|
|
352 |
|
|
reg [13:0] div_calc;
|
353 |
|
|
reg [16:0] phase_calc;
|
354 |
|
|
|
355 |
|
|
begin
|
356 |
|
|
`ifdef DEBUG
|
357 |
|
|
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
358 |
|
|
divide, phase, duty_cycle);
|
359 |
|
|
`endif
|
360 |
|
|
|
361 |
|
|
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
362 |
|
|
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
363 |
|
|
// mx[10:9], pm[8:6], dt[5:0]
|
364 |
|
|
phase_calc = mmcm_pll_phase(divide, phase);
|
365 |
|
|
|
366 |
|
|
// Return value is the upper and lower address of counter
|
367 |
|
|
// Upper address is:
|
368 |
|
|
// RESERVED [31:26]
|
369 |
|
|
// MX [25:24]
|
370 |
|
|
// EDGE [23]
|
371 |
|
|
// NOCOUNT [22]
|
372 |
|
|
// DELAY_TIME [21:16]
|
373 |
|
|
// Lower Address is:
|
374 |
|
|
// PHASE_MUX [15:13]
|
375 |
|
|
// RESERVED [12]
|
376 |
|
|
// HIGH_TIME [11:6]
|
377 |
|
|
// LOW_TIME [5:0]
|
378 |
|
|
|
379 |
|
|
`ifdef DEBUG
|
380 |
|
|
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
381 |
|
|
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
382 |
|
|
div_calc[13], div_calc[12],
|
383 |
|
|
phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
|
384 |
|
|
`endif
|
385 |
|
|
|
386 |
|
|
mmcm_pll_count_calc =
|
387 |
|
|
{
|
388 |
|
|
// Upper Address
|
389 |
|
|
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
390 |
|
|
// Lower Address
|
391 |
|
|
phase_calc[8:6], 1'b0, div_calc[11:0]
|
392 |
|
|
};
|
393 |
|
|
end
|
394 |
|
|
endfunction
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
// This function takes in the divide, phase, and duty cycle
|
398 |
|
|
// setting to calculate the upper and lower counter registers.
|
399 |
|
|
// for fractional multiply/divide functions.
|
400 |
|
|
//
|
401 |
|
|
//
|
402 |
|
|
function [37:0] mmcm_pll_frac_count_calc
|
403 |
|
|
(
|
404 |
|
|
input [7:0] divide, // Max divide is 128
|
405 |
|
|
input signed [31:0] phase,
|
406 |
|
|
input [31:0] duty_cycle, // Multiplied by 1,000
|
407 |
|
|
input [9:0] frac // Multiplied by 1000
|
408 |
|
|
);
|
409 |
|
|
|
410 |
|
|
//Required for fractional divide calculations
|
411 |
|
|
reg [7:0] lt_frac;
|
412 |
|
|
reg [7:0] ht_frac;
|
413 |
|
|
|
414 |
|
|
reg /*[7:0]*/ wf_fall_frac;
|
415 |
|
|
reg /*[7:0]*/ wf_rise_frac;
|
416 |
|
|
|
417 |
|
|
reg [31:0] a;
|
418 |
|
|
reg [7:0] pm_rise_frac_filtered ;
|
419 |
|
|
reg [7:0] pm_fall_frac_filtered ;
|
420 |
|
|
reg [7:0] clkout0_divide_int;
|
421 |
|
|
reg [2:0] clkout0_divide_frac;
|
422 |
|
|
reg [7:0] even_part_high;
|
423 |
|
|
reg [7:0] even_part_low;
|
424 |
|
|
|
425 |
|
|
reg [7:0] odd;
|
426 |
|
|
reg [7:0] odd_and_frac;
|
427 |
|
|
|
428 |
|
|
reg [7:0] pm_fall;
|
429 |
|
|
reg [7:0] pm_rise;
|
430 |
|
|
reg [7:0] dt;
|
431 |
|
|
reg [7:0] dt_int;
|
432 |
|
|
reg [63:0] dt_calc;
|
433 |
|
|
|
434 |
|
|
reg [7:0] pm_rise_frac;
|
435 |
|
|
reg [7:0] pm_fall_frac;
|
436 |
|
|
|
437 |
|
|
reg [31:0] a_per_in_octets;
|
438 |
|
|
reg [31:0] a_phase_in_cycles;
|
439 |
|
|
|
440 |
|
|
parameter precision = 0.125;
|
441 |
|
|
|
442 |
|
|
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
443 |
|
|
reg [31: 0] phase_pos;
|
444 |
|
|
reg [31: 0] phase_vco;
|
445 |
|
|
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
446 |
|
|
reg [13:0] div_calc;
|
447 |
|
|
reg [16:0] phase_calc;
|
448 |
|
|
|
449 |
|
|
begin
|
450 |
|
|
`ifdef DEBUG
|
451 |
|
|
$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
452 |
|
|
divide, phase, duty_cycle);
|
453 |
|
|
`endif
|
454 |
|
|
|
455 |
|
|
//convert phase to fixed
|
456 |
|
|
if ((phase < -360000) || (phase > 360000)) begin
|
457 |
|
|
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
458 |
|
|
$finish;
|
459 |
|
|
end
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
// Return value is
|
463 |
|
|
// Transfer data
|
464 |
|
|
// RESERVED [37:36]
|
465 |
|
|
// FRAC_TIME [35:33]
|
466 |
|
|
// FRAC_WF_FALL [32]
|
467 |
|
|
// Upper address is:
|
468 |
|
|
// RESERVED [31:26]
|
469 |
|
|
// MX [25:24]
|
470 |
|
|
// EDGE [23]
|
471 |
|
|
// NOCOUNT [22]
|
472 |
|
|
// DELAY_TIME [21:16]
|
473 |
|
|
// Lower Address is:
|
474 |
|
|
// PHASE_MUX [15:13]
|
475 |
|
|
// RESERVED [12]
|
476 |
|
|
// HIGH_TIME [11:6]
|
477 |
|
|
// LOW_TIME [5:0]
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
clkout0_divide_frac = frac / 125;
|
482 |
|
|
clkout0_divide_int = divide;
|
483 |
|
|
|
484 |
|
|
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
485 |
|
|
even_part_low = even_part_high;
|
486 |
|
|
|
487 |
|
|
odd = clkout0_divide_int - even_part_high - even_part_low;
|
488 |
|
|
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
489 |
|
|
|
490 |
|
|
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
491 |
|
|
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
492 |
|
|
|
493 |
|
|
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
494 |
|
|
pm_rise = 0; //0
|
495 |
|
|
|
496 |
|
|
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
497 |
|
|
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
498 |
|
|
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
//Calculate phase in fractional cycles
|
502 |
|
|
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
503 |
|
|
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
504 |
|
|
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
505 |
|
|
|
506 |
|
|
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
507 |
|
|
dt = dt_calc[7:0];
|
508 |
|
|
|
509 |
|
|
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
510 |
|
|
|
511 |
|
|
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
512 |
|
|
pm_fall_frac = pm_fall + pm_rise_frac;
|
513 |
|
|
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
514 |
|
|
|
515 |
|
|
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
516 |
|
|
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
517 |
|
|
|
518 |
|
|
mmcm_pll_frac_count_calc[37:0] =
|
519 |
|
|
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
520 |
|
|
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
521 |
|
|
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
522 |
|
|
} ;
|
523 |
|
|
|
524 |
|
|
`ifdef DEBUG
|
525 |
|
|
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
526 |
|
|
`endif
|
527 |
|
|
|
528 |
|
|
end
|
529 |
|
|
endfunction
|
530 |
|
|
|