1 |
2 |
vv_gulyaev |
(DELAYFILE
|
2 |
|
|
(SDFVERSION "3.0" )
|
3 |
|
|
(DESIGN "axi_uartlite_module")
|
4 |
|
|
(DATE "Tue Jul 28 08:49:01 2020")
|
5 |
|
|
(VENDOR "XILINX")
|
6 |
|
|
(PROGRAM "Vivado")
|
7 |
|
|
(VERSION "2017.4")
|
8 |
|
|
(DIVIDER /)
|
9 |
|
|
(TIMESCALE 1ps)
|
10 |
|
|
(CELL
|
11 |
|
|
(CELLTYPE "LUT3")
|
12 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1)
|
13 |
|
|
(DELAY
|
14 |
|
|
(PATHPULSE (50.0))
|
15 |
|
|
(ABSOLUTE
|
16 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
17 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
18 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
19 |
|
|
)
|
20 |
|
|
)
|
21 |
|
|
)
|
22 |
|
|
(CELL
|
23 |
|
|
(CELLTYPE "FDRE")
|
24 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg)
|
25 |
|
|
(DELAY
|
26 |
|
|
(ABSOLUTE
|
27 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
28 |
|
|
)
|
29 |
|
|
)
|
30 |
|
|
(TIMINGCHECK
|
31 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
32 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
33 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
34 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
35 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
36 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
37 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
38 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
39 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
40 |
|
|
)
|
41 |
|
|
)
|
42 |
|
|
(CELL
|
43 |
|
|
(CELLTYPE "FDRE")
|
44 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\])
|
45 |
|
|
(DELAY
|
46 |
|
|
(ABSOLUTE
|
47 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
48 |
|
|
)
|
49 |
|
|
)
|
50 |
|
|
(TIMINGCHECK
|
51 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
52 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
53 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
54 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
55 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
56 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
57 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
58 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
59 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
60 |
|
|
)
|
61 |
|
|
)
|
62 |
|
|
(CELL
|
63 |
|
|
(CELLTYPE "LUT2")
|
64 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i\[1\]_i_1)
|
65 |
|
|
(DELAY
|
66 |
|
|
(PATHPULSE (50.0))
|
67 |
|
|
(ABSOLUTE
|
68 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
69 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
70 |
|
|
)
|
71 |
|
|
)
|
72 |
|
|
)
|
73 |
|
|
(CELL
|
74 |
|
|
(CELLTYPE "FDRE")
|
75 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\])
|
76 |
|
|
(DELAY
|
77 |
|
|
(ABSOLUTE
|
78 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
79 |
|
|
)
|
80 |
|
|
)
|
81 |
|
|
(TIMINGCHECK
|
82 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
83 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
84 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
85 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
86 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
87 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
88 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
89 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
90 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
91 |
|
|
)
|
92 |
|
|
)
|
93 |
|
|
(CELL
|
94 |
|
|
(CELLTYPE "FDRE")
|
95 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\])
|
96 |
|
|
(DELAY
|
97 |
|
|
(ABSOLUTE
|
98 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
99 |
|
|
)
|
100 |
|
|
)
|
101 |
|
|
(TIMINGCHECK
|
102 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
103 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
104 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
105 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
106 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
107 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
108 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
109 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
110 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
111 |
|
|
)
|
112 |
|
|
)
|
113 |
|
|
(CELL
|
114 |
|
|
(CELLTYPE "LUT5")
|
115 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1)
|
116 |
|
|
(DELAY
|
117 |
|
|
(PATHPULSE (50.0))
|
118 |
|
|
(ABSOLUTE
|
119 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
120 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
121 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
122 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
123 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
124 |
|
|
)
|
125 |
|
|
)
|
126 |
|
|
)
|
127 |
|
|
(CELL
|
128 |
|
|
(CELLTYPE "LUT2")
|
129 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_2)
|
130 |
|
|
(DELAY
|
131 |
|
|
(PATHPULSE (50.0))
|
132 |
|
|
(ABSOLUTE
|
133 |
|
|
(IOPATH I1 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
134 |
|
|
(IOPATH I0 O (44.0:54.0:54.0) (44.0:54.0:54.0))
|
135 |
|
|
)
|
136 |
|
|
)
|
137 |
|
|
)
|
138 |
|
|
(CELL
|
139 |
|
|
(CELLTYPE "FDRE")
|
140 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\])
|
141 |
|
|
(DELAY
|
142 |
|
|
(ABSOLUTE
|
143 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
144 |
|
|
)
|
145 |
|
|
)
|
146 |
|
|
(TIMINGCHECK
|
147 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
148 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
149 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
150 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
151 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
152 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
153 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
154 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
155 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
156 |
|
|
)
|
157 |
|
|
)
|
158 |
|
|
(CELL
|
159 |
|
|
(CELLTYPE "LUT3")
|
160 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2)
|
161 |
|
|
(DELAY
|
162 |
|
|
(PATHPULSE (50.0))
|
163 |
|
|
(ABSOLUTE
|
164 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
165 |
|
|
(IOPATH I1 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
166 |
|
|
(IOPATH I0 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
167 |
|
|
)
|
168 |
|
|
)
|
169 |
|
|
)
|
170 |
|
|
(CELL
|
171 |
|
|
(CELLTYPE "LUT2")
|
172 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_3)
|
173 |
|
|
(DELAY
|
174 |
|
|
(PATHPULSE (50.0))
|
175 |
|
|
(ABSOLUTE
|
176 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
177 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
178 |
|
|
)
|
179 |
|
|
)
|
180 |
|
|
)
|
181 |
|
|
(CELL
|
182 |
|
|
(CELLTYPE "LUT3")
|
183 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5)
|
184 |
|
|
(DELAY
|
185 |
|
|
(PATHPULSE (50.0))
|
186 |
|
|
(ABSOLUTE
|
187 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
188 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
189 |
|
|
(IOPATH I0 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
190 |
|
|
)
|
191 |
|
|
)
|
192 |
|
|
)
|
193 |
|
|
(CELL
|
194 |
|
|
(CELLTYPE "LUT3")
|
195 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1)
|
196 |
|
|
(DELAY
|
197 |
|
|
(PATHPULSE (50.0))
|
198 |
|
|
(ABSOLUTE
|
199 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
200 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
201 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
202 |
|
|
)
|
203 |
|
|
)
|
204 |
|
|
)
|
205 |
|
|
(CELL
|
206 |
|
|
(CELLTYPE "LUT2")
|
207 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[0\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS)
|
208 |
|
|
(DELAY
|
209 |
|
|
(PATHPULSE (50.0))
|
210 |
|
|
(ABSOLUTE
|
211 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
212 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
213 |
|
|
)
|
214 |
|
|
)
|
215 |
|
|
)
|
216 |
|
|
(CELL
|
217 |
|
|
(CELLTYPE "LUT2")
|
218 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[2\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS)
|
219 |
|
|
(DELAY
|
220 |
|
|
(PATHPULSE (50.0))
|
221 |
|
|
(ABSOLUTE
|
222 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
223 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
224 |
|
|
)
|
225 |
|
|
)
|
226 |
|
|
)
|
227 |
|
|
(CELL
|
228 |
|
|
(CELLTYPE "LUT2")
|
229 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/clr_Status_i_1)
|
230 |
|
|
(DELAY
|
231 |
|
|
(PATHPULSE (50.0))
|
232 |
|
|
(ABSOLUTE
|
233 |
|
|
(IOPATH I1 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
234 |
|
|
(IOPATH I0 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
235 |
|
|
)
|
236 |
|
|
)
|
237 |
|
|
)
|
238 |
|
|
(CELL
|
239 |
|
|
(CELLTYPE "LUT4")
|
240 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/enable_interrupts_i_1)
|
241 |
|
|
(DELAY
|
242 |
|
|
(PATHPULSE (50.0))
|
243 |
|
|
(ABSOLUTE
|
244 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
245 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
246 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
247 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
248 |
|
|
)
|
249 |
|
|
)
|
250 |
|
|
)
|
251 |
|
|
(CELL
|
252 |
|
|
(CELLTYPE "LUT3")
|
253 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_RX_FIFO_i_1)
|
254 |
|
|
(DELAY
|
255 |
|
|
(PATHPULSE (50.0))
|
256 |
|
|
(ABSOLUTE
|
257 |
|
|
(IOPATH I2 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
258 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
259 |
|
|
(IOPATH I0 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
260 |
|
|
)
|
261 |
|
|
)
|
262 |
|
|
)
|
263 |
|
|
(CELL
|
264 |
|
|
(CELLTYPE "LUT3")
|
265 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_TX_FIFO_i_1)
|
266 |
|
|
(DELAY
|
267 |
|
|
(PATHPULSE (50.0))
|
268 |
|
|
(ABSOLUTE
|
269 |
|
|
(IOPATH I2 O (46.0:55.0:55.0) (46.0:55.0:55.0))
|
270 |
|
|
(IOPATH I1 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
271 |
|
|
(IOPATH I0 O (44.0:54.0:54.0) (44.0:54.0:54.0))
|
272 |
|
|
)
|
273 |
|
|
)
|
274 |
|
|
)
|
275 |
|
|
(CELL
|
276 |
|
|
(CELLTYPE "LUT4")
|
277 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/rx_Data_Present_Pre_i_1)
|
278 |
|
|
(DELAY
|
279 |
|
|
(PATHPULSE (50.0))
|
280 |
|
|
(ABSOLUTE
|
281 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
282 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
283 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
284 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
285 |
|
|
)
|
286 |
|
|
)
|
287 |
|
|
)
|
288 |
|
|
(CELL
|
289 |
|
|
(CELLTYPE "LUT5")
|
290 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0)
|
291 |
|
|
(DELAY
|
292 |
|
|
(PATHPULSE (50.0))
|
293 |
|
|
(ABSOLUTE
|
294 |
|
|
(IOPATH I4 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
295 |
|
|
(IOPATH I3 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
296 |
|
|
(IOPATH I2 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
297 |
|
|
(IOPATH I1 O (46.0:55.0:55.0) (46.0:55.0:55.0))
|
298 |
|
|
(IOPATH I0 O (44.0:54.0:54.0) (44.0:54.0:54.0))
|
299 |
|
|
)
|
300 |
|
|
)
|
301 |
|
|
)
|
302 |
|
|
(CELL
|
303 |
|
|
(CELLTYPE "LUT4")
|
304 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1)
|
305 |
|
|
(DELAY
|
306 |
|
|
(PATHPULSE (50.0))
|
307 |
|
|
(ABSOLUTE
|
308 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
309 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
310 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
311 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
312 |
|
|
)
|
313 |
|
|
)
|
314 |
|
|
)
|
315 |
|
|
(CELL
|
316 |
|
|
(CELLTYPE "LUT5")
|
317 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1)
|
318 |
|
|
(DELAY
|
319 |
|
|
(PATHPULSE (50.0))
|
320 |
|
|
(ABSOLUTE
|
321 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
322 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
323 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
324 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
325 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
326 |
|
|
)
|
327 |
|
|
)
|
328 |
|
|
)
|
329 |
|
|
(CELL
|
330 |
|
|
(CELLTYPE "LUT5")
|
331 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1)
|
332 |
|
|
(DELAY
|
333 |
|
|
(PATHPULSE (50.0))
|
334 |
|
|
(ABSOLUTE
|
335 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
336 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
337 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
338 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
339 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
340 |
|
|
)
|
341 |
|
|
)
|
342 |
|
|
)
|
343 |
|
|
(CELL
|
344 |
|
|
(CELLTYPE "LUT5")
|
345 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1)
|
346 |
|
|
(DELAY
|
347 |
|
|
(PATHPULSE (50.0))
|
348 |
|
|
(ABSOLUTE
|
349 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
350 |
|
|
(IOPATH I3 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
351 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
352 |
|
|
(IOPATH I1 O (39.0:47.0:47.0) (39.0:47.0:47.0))
|
353 |
|
|
(IOPATH I0 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
354 |
|
|
)
|
355 |
|
|
)
|
356 |
|
|
)
|
357 |
|
|
(CELL
|
358 |
|
|
(CELLTYPE "LUT5")
|
359 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1)
|
360 |
|
|
(DELAY
|
361 |
|
|
(PATHPULSE (50.0))
|
362 |
|
|
(ABSOLUTE
|
363 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
364 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
365 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
366 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
367 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
368 |
|
|
)
|
369 |
|
|
)
|
370 |
|
|
)
|
371 |
|
|
(CELL
|
372 |
|
|
(CELLTYPE "LUT5")
|
373 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1)
|
374 |
|
|
(DELAY
|
375 |
|
|
(PATHPULSE (50.0))
|
376 |
|
|
(ABSOLUTE
|
377 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
378 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
379 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
380 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
381 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
382 |
|
|
)
|
383 |
|
|
)
|
384 |
|
|
)
|
385 |
|
|
(CELL
|
386 |
|
|
(CELLTYPE "LUT5")
|
387 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1)
|
388 |
|
|
(DELAY
|
389 |
|
|
(PATHPULSE (50.0))
|
390 |
|
|
(ABSOLUTE
|
391 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
392 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
393 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
394 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
395 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
396 |
|
|
)
|
397 |
|
|
)
|
398 |
|
|
)
|
399 |
|
|
(CELL
|
400 |
|
|
(CELLTYPE "LUT5")
|
401 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1)
|
402 |
|
|
(DELAY
|
403 |
|
|
(PATHPULSE (50.0))
|
404 |
|
|
(ABSOLUTE
|
405 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
406 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
407 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
408 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
409 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
410 |
|
|
)
|
411 |
|
|
)
|
412 |
|
|
)
|
413 |
|
|
(CELL
|
414 |
|
|
(CELLTYPE "LUT5")
|
415 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1)
|
416 |
|
|
(DELAY
|
417 |
|
|
(PATHPULSE (50.0))
|
418 |
|
|
(ABSOLUTE
|
419 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
420 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
421 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
422 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
423 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
424 |
|
|
)
|
425 |
|
|
)
|
426 |
|
|
)
|
427 |
|
|
(CELL
|
428 |
|
|
(CELLTYPE "LUT4")
|
429 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2)
|
430 |
|
|
(DELAY
|
431 |
|
|
(PATHPULSE (50.0))
|
432 |
|
|
(ABSOLUTE
|
433 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
434 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
435 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
436 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
437 |
|
|
)
|
438 |
|
|
)
|
439 |
|
|
)
|
440 |
|
|
(CELL
|
441 |
|
|
(CELLTYPE "LUT5")
|
442 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1)
|
443 |
|
|
(DELAY
|
444 |
|
|
(PATHPULSE (50.0))
|
445 |
|
|
(ABSOLUTE
|
446 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
447 |
|
|
(IOPATH I3 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
448 |
|
|
(IOPATH I2 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
449 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
450 |
|
|
(IOPATH I0 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
451 |
|
|
)
|
452 |
|
|
)
|
453 |
|
|
)
|
454 |
|
|
(CELL
|
455 |
|
|
(CELLTYPE "LUT5")
|
456 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1)
|
457 |
|
|
(DELAY
|
458 |
|
|
(PATHPULSE (50.0))
|
459 |
|
|
(ABSOLUTE
|
460 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
461 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
462 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
463 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
464 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
465 |
|
|
)
|
466 |
|
|
)
|
467 |
|
|
)
|
468 |
|
|
(CELL
|
469 |
|
|
(CELLTYPE "LUT5")
|
470 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0)
|
471 |
|
|
(DELAY
|
472 |
|
|
(PATHPULSE (50.0))
|
473 |
|
|
(ABSOLUTE
|
474 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
475 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
476 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
477 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
478 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
479 |
|
|
)
|
480 |
|
|
)
|
481 |
|
|
)
|
482 |
|
|
(CELL
|
483 |
|
|
(CELLTYPE "LUT5")
|
484 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1)
|
485 |
|
|
(DELAY
|
486 |
|
|
(PATHPULSE (50.0))
|
487 |
|
|
(ABSOLUTE
|
488 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
489 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
490 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
491 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
492 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
493 |
|
|
)
|
494 |
|
|
)
|
495 |
|
|
)
|
496 |
|
|
(CELL
|
497 |
|
|
(CELLTYPE "LUT6")
|
498 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1)
|
499 |
|
|
(DELAY
|
500 |
|
|
(PATHPULSE (50.0))
|
501 |
|
|
(ABSOLUTE
|
502 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
503 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
504 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
505 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
506 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
507 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
508 |
|
|
)
|
509 |
|
|
)
|
510 |
|
|
)
|
511 |
|
|
(CELL
|
512 |
|
|
(CELLTYPE "LUT4")
|
513 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/tx_Buffer_Empty_Pre_i_1)
|
514 |
|
|
(DELAY
|
515 |
|
|
(PATHPULSE (50.0))
|
516 |
|
|
(ABSOLUTE
|
517 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
518 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
519 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
520 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
521 |
|
|
)
|
522 |
|
|
)
|
523 |
|
|
)
|
524 |
|
|
(CELL
|
525 |
|
|
(CELLTYPE "LUT5")
|
526 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[2\]_i_1)
|
527 |
|
|
(DELAY
|
528 |
|
|
(PATHPULSE (50.0))
|
529 |
|
|
(ABSOLUTE
|
530 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
531 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
532 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
533 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
534 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
535 |
|
|
)
|
536 |
|
|
)
|
537 |
|
|
)
|
538 |
|
|
(CELL
|
539 |
|
|
(CELLTYPE "LUT5")
|
540 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_1)
|
541 |
|
|
(DELAY
|
542 |
|
|
(PATHPULSE (50.0))
|
543 |
|
|
(ABSOLUTE
|
544 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
545 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
546 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
547 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
548 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
549 |
|
|
)
|
550 |
|
|
)
|
551 |
|
|
)
|
552 |
|
|
(CELL
|
553 |
|
|
(CELLTYPE "LUT3")
|
554 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_2)
|
555 |
|
|
(DELAY
|
556 |
|
|
(PATHPULSE (50.0))
|
557 |
|
|
(ABSOLUTE
|
558 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
559 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
560 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
561 |
|
|
)
|
562 |
|
|
)
|
563 |
|
|
)
|
564 |
|
|
(CELL
|
565 |
|
|
(CELLTYPE "FDRE")
|
566 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\])
|
567 |
|
|
(DELAY
|
568 |
|
|
(ABSOLUTE
|
569 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
570 |
|
|
)
|
571 |
|
|
)
|
572 |
|
|
(TIMINGCHECK
|
573 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
574 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
575 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
576 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
577 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
578 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
579 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
580 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
581 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
582 |
|
|
)
|
583 |
|
|
)
|
584 |
|
|
(CELL
|
585 |
|
|
(CELLTYPE "FDRE")
|
586 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\])
|
587 |
|
|
(DELAY
|
588 |
|
|
(ABSOLUTE
|
589 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
590 |
|
|
)
|
591 |
|
|
)
|
592 |
|
|
(TIMINGCHECK
|
593 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
594 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
595 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
596 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
597 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
598 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
599 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
600 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
601 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
602 |
|
|
)
|
603 |
|
|
)
|
604 |
|
|
(CELL
|
605 |
|
|
(CELLTYPE "LUT5")
|
606 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_i_1)
|
607 |
|
|
(DELAY
|
608 |
|
|
(PATHPULSE (50.0))
|
609 |
|
|
(ABSOLUTE
|
610 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
611 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
612 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
613 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
614 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
615 |
|
|
)
|
616 |
|
|
)
|
617 |
|
|
)
|
618 |
|
|
(CELL
|
619 |
|
|
(CELLTYPE "FDRE")
|
620 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_reg)
|
621 |
|
|
(DELAY
|
622 |
|
|
(ABSOLUTE
|
623 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
624 |
|
|
)
|
625 |
|
|
)
|
626 |
|
|
(TIMINGCHECK
|
627 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
628 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
629 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
630 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
631 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
632 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
633 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
634 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
635 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
636 |
|
|
)
|
637 |
|
|
)
|
638 |
|
|
(CELL
|
639 |
|
|
(CELLTYPE "FDRE")
|
640 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg)
|
641 |
|
|
(DELAY
|
642 |
|
|
(ABSOLUTE
|
643 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
644 |
|
|
)
|
645 |
|
|
)
|
646 |
|
|
(TIMINGCHECK
|
647 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
648 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
649 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
650 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
651 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
652 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
653 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
654 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
655 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
656 |
|
|
)
|
657 |
|
|
)
|
658 |
|
|
(CELL
|
659 |
|
|
(CELLTYPE "FDRE")
|
660 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\])
|
661 |
|
|
(DELAY
|
662 |
|
|
(ABSOLUTE
|
663 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
664 |
|
|
)
|
665 |
|
|
)
|
666 |
|
|
(TIMINGCHECK
|
667 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
668 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
669 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
670 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
671 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
672 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
673 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
674 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
675 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
676 |
|
|
)
|
677 |
|
|
)
|
678 |
|
|
(CELL
|
679 |
|
|
(CELLTYPE "FDRE")
|
680 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg)
|
681 |
|
|
(DELAY
|
682 |
|
|
(ABSOLUTE
|
683 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
684 |
|
|
)
|
685 |
|
|
)
|
686 |
|
|
(TIMINGCHECK
|
687 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
688 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
689 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
690 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
691 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
692 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
693 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
694 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
695 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
696 |
|
|
)
|
697 |
|
|
)
|
698 |
|
|
(CELL
|
699 |
|
|
(CELLTYPE "LUT2")
|
700 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1)
|
701 |
|
|
(DELAY
|
702 |
|
|
(PATHPULSE (50.0))
|
703 |
|
|
(ABSOLUTE
|
704 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
705 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
706 |
|
|
)
|
707 |
|
|
)
|
708 |
|
|
)
|
709 |
|
|
(CELL
|
710 |
|
|
(CELLTYPE "FDRE")
|
711 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\])
|
712 |
|
|
(DELAY
|
713 |
|
|
(ABSOLUTE
|
714 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
715 |
|
|
)
|
716 |
|
|
)
|
717 |
|
|
(TIMINGCHECK
|
718 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
719 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
720 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
721 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
722 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
723 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
724 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
725 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
726 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
727 |
|
|
)
|
728 |
|
|
)
|
729 |
|
|
(CELL
|
730 |
|
|
(CELLTYPE "FDRE")
|
731 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\])
|
732 |
|
|
(DELAY
|
733 |
|
|
(ABSOLUTE
|
734 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
735 |
|
|
)
|
736 |
|
|
)
|
737 |
|
|
(TIMINGCHECK
|
738 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
739 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
740 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
741 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
742 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
743 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
744 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
745 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
746 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
747 |
|
|
)
|
748 |
|
|
)
|
749 |
|
|
(CELL
|
750 |
|
|
(CELLTYPE "FDRE")
|
751 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\])
|
752 |
|
|
(DELAY
|
753 |
|
|
(ABSOLUTE
|
754 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
755 |
|
|
)
|
756 |
|
|
)
|
757 |
|
|
(TIMINGCHECK
|
758 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
759 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
760 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
761 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
762 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
763 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
764 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
765 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
766 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
767 |
|
|
)
|
768 |
|
|
)
|
769 |
|
|
(CELL
|
770 |
|
|
(CELLTYPE "FDRE")
|
771 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\])
|
772 |
|
|
(DELAY
|
773 |
|
|
(ABSOLUTE
|
774 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
775 |
|
|
)
|
776 |
|
|
)
|
777 |
|
|
(TIMINGCHECK
|
778 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
779 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
780 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
781 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
782 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
783 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
784 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
785 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
786 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
787 |
|
|
)
|
788 |
|
|
)
|
789 |
|
|
(CELL
|
790 |
|
|
(CELLTYPE "FDRE")
|
791 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\])
|
792 |
|
|
(DELAY
|
793 |
|
|
(ABSOLUTE
|
794 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
795 |
|
|
)
|
796 |
|
|
)
|
797 |
|
|
(TIMINGCHECK
|
798 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
799 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
800 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
801 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
802 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
803 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
804 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
805 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
806 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
807 |
|
|
)
|
808 |
|
|
)
|
809 |
|
|
(CELL
|
810 |
|
|
(CELLTYPE "FDRE")
|
811 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\])
|
812 |
|
|
(DELAY
|
813 |
|
|
(ABSOLUTE
|
814 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
815 |
|
|
)
|
816 |
|
|
)
|
817 |
|
|
(TIMINGCHECK
|
818 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
819 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
820 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
821 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
822 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
823 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
824 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
825 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
826 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
827 |
|
|
)
|
828 |
|
|
)
|
829 |
|
|
(CELL
|
830 |
|
|
(CELLTYPE "FDRE")
|
831 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\])
|
832 |
|
|
(DELAY
|
833 |
|
|
(ABSOLUTE
|
834 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
835 |
|
|
)
|
836 |
|
|
)
|
837 |
|
|
(TIMINGCHECK
|
838 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
839 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
840 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
841 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
842 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
843 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
844 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
845 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
846 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
847 |
|
|
)
|
848 |
|
|
)
|
849 |
|
|
(CELL
|
850 |
|
|
(CELLTYPE "FDRE")
|
851 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\])
|
852 |
|
|
(DELAY
|
853 |
|
|
(ABSOLUTE
|
854 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
855 |
|
|
)
|
856 |
|
|
)
|
857 |
|
|
(TIMINGCHECK
|
858 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
859 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
860 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
861 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
862 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
863 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
864 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
865 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
866 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
867 |
|
|
)
|
868 |
|
|
)
|
869 |
|
|
(CELL
|
870 |
|
|
(CELLTYPE "FDRE")
|
871 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\])
|
872 |
|
|
(DELAY
|
873 |
|
|
(ABSOLUTE
|
874 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
875 |
|
|
)
|
876 |
|
|
)
|
877 |
|
|
(TIMINGCHECK
|
878 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
879 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
880 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
881 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
882 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
883 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
884 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
885 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
886 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
887 |
|
|
)
|
888 |
|
|
)
|
889 |
|
|
(CELL
|
890 |
|
|
(CELLTYPE "FDRE")
|
891 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg)
|
892 |
|
|
(DELAY
|
893 |
|
|
(ABSOLUTE
|
894 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
895 |
|
|
)
|
896 |
|
|
)
|
897 |
|
|
(TIMINGCHECK
|
898 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
899 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
900 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
901 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
902 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
903 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
904 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
905 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
906 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
907 |
|
|
)
|
908 |
|
|
)
|
909 |
|
|
(CELL
|
910 |
|
|
(CELLTYPE "LUT4")
|
911 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1)
|
912 |
|
|
(DELAY
|
913 |
|
|
(PATHPULSE (50.0))
|
914 |
|
|
(ABSOLUTE
|
915 |
|
|
(IOPATH I3 O (39.0:48.0:48.0) (39.0:48.0:48.0))
|
916 |
|
|
(IOPATH I2 O (42.0:50.0:50.0) (42.0:50.0:50.0))
|
917 |
|
|
(IOPATH I1 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
918 |
|
|
(IOPATH I0 O (42.0:50.0:50.0) (42.0:50.0:50.0))
|
919 |
|
|
)
|
920 |
|
|
)
|
921 |
|
|
)
|
922 |
|
|
(CELL
|
923 |
|
|
(CELLTYPE "FDRE")
|
924 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg)
|
925 |
|
|
(DELAY
|
926 |
|
|
(ABSOLUTE
|
927 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
928 |
|
|
)
|
929 |
|
|
)
|
930 |
|
|
(TIMINGCHECK
|
931 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
932 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
933 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
934 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
935 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
936 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
937 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
938 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
939 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
940 |
|
|
)
|
941 |
|
|
)
|
942 |
|
|
(CELL
|
943 |
|
|
(CELLTYPE "LUT5")
|
944 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[0\]_i_2)
|
945 |
|
|
(DELAY
|
946 |
|
|
(PATHPULSE (50.0))
|
947 |
|
|
(ABSOLUTE
|
948 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
949 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
950 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
951 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
952 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
953 |
|
|
)
|
954 |
|
|
)
|
955 |
|
|
)
|
956 |
|
|
(CELL
|
957 |
|
|
(CELLTYPE "LUT5")
|
958 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[1\]_i_2)
|
959 |
|
|
(DELAY
|
960 |
|
|
(PATHPULSE (50.0))
|
961 |
|
|
(ABSOLUTE
|
962 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
963 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
964 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
965 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
966 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
967 |
|
|
)
|
968 |
|
|
)
|
969 |
|
|
)
|
970 |
|
|
(CELL
|
971 |
|
|
(CELLTYPE "FDRE")
|
972 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\])
|
973 |
|
|
(DELAY
|
974 |
|
|
(ABSOLUTE
|
975 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
976 |
|
|
)
|
977 |
|
|
)
|
978 |
|
|
(TIMINGCHECK
|
979 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
980 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
981 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
982 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
983 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
984 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
985 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
986 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
987 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
988 |
|
|
)
|
989 |
|
|
)
|
990 |
|
|
(CELL
|
991 |
|
|
(CELLTYPE "FDRE")
|
992 |
|
|
(INSTANCE U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\])
|
993 |
|
|
(DELAY
|
994 |
|
|
(ABSOLUTE
|
995 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
996 |
|
|
)
|
997 |
|
|
)
|
998 |
|
|
(TIMINGCHECK
|
999 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1000 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1001 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1002 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1003 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1004 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1005 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1006 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1007 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1008 |
|
|
)
|
1009 |
|
|
)
|
1010 |
|
|
(CELL
|
1011 |
|
|
(CELLTYPE "LUT4")
|
1012 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1)
|
1013 |
|
|
(DELAY
|
1014 |
|
|
(PATHPULSE (50.0))
|
1015 |
|
|
(ABSOLUTE
|
1016 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1017 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1018 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1019 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1020 |
|
|
)
|
1021 |
|
|
)
|
1022 |
|
|
)
|
1023 |
|
|
(CELL
|
1024 |
|
|
(CELLTYPE "FDRE")
|
1025 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg)
|
1026 |
|
|
(DELAY
|
1027 |
|
|
(ABSOLUTE
|
1028 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1029 |
|
|
)
|
1030 |
|
|
)
|
1031 |
|
|
(TIMINGCHECK
|
1032 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1033 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1034 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1035 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1036 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1037 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1038 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1039 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1040 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1041 |
|
|
)
|
1042 |
|
|
)
|
1043 |
|
|
(CELL
|
1044 |
|
|
(CELLTYPE "LUT6")
|
1045 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1)
|
1046 |
|
|
(DELAY
|
1047 |
|
|
(PATHPULSE (50.0))
|
1048 |
|
|
(ABSOLUTE
|
1049 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1050 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1051 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1052 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1053 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1054 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1055 |
|
|
)
|
1056 |
|
|
)
|
1057 |
|
|
)
|
1058 |
|
|
(CELL
|
1059 |
|
|
(CELLTYPE "LUT2")
|
1060 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[1\]_i_1)
|
1061 |
|
|
(DELAY
|
1062 |
|
|
(PATHPULSE (50.0))
|
1063 |
|
|
(ABSOLUTE
|
1064 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1065 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1066 |
|
|
)
|
1067 |
|
|
)
|
1068 |
|
|
)
|
1069 |
|
|
(CELL
|
1070 |
|
|
(CELLTYPE "LUT6")
|
1071 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1)
|
1072 |
|
|
(DELAY
|
1073 |
|
|
(PATHPULSE (50.0))
|
1074 |
|
|
(ABSOLUTE
|
1075 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1076 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1077 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1078 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1079 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1080 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1081 |
|
|
)
|
1082 |
|
|
)
|
1083 |
|
|
)
|
1084 |
|
|
(CELL
|
1085 |
|
|
(CELLTYPE "LUT3")
|
1086 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2)
|
1087 |
|
|
(DELAY
|
1088 |
|
|
(PATHPULSE (50.0))
|
1089 |
|
|
(ABSOLUTE
|
1090 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1091 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1092 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1093 |
|
|
)
|
1094 |
|
|
)
|
1095 |
|
|
)
|
1096 |
|
|
(CELL
|
1097 |
|
|
(CELLTYPE "LUT6")
|
1098 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1)
|
1099 |
|
|
(DELAY
|
1100 |
|
|
(PATHPULSE (50.0))
|
1101 |
|
|
(ABSOLUTE
|
1102 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1103 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1104 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1105 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1106 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1107 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1108 |
|
|
)
|
1109 |
|
|
)
|
1110 |
|
|
)
|
1111 |
|
|
(CELL
|
1112 |
|
|
(CELLTYPE "LUT3")
|
1113 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_2)
|
1114 |
|
|
(DELAY
|
1115 |
|
|
(PATHPULSE (50.0))
|
1116 |
|
|
(ABSOLUTE
|
1117 |
|
|
(IOPATH I2 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
1118 |
|
|
(IOPATH I1 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
1119 |
|
|
(IOPATH I0 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1120 |
|
|
)
|
1121 |
|
|
)
|
1122 |
|
|
)
|
1123 |
|
|
(CELL
|
1124 |
|
|
(CELLTYPE "LUT5")
|
1125 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1)
|
1126 |
|
|
(DELAY
|
1127 |
|
|
(PATHPULSE (50.0))
|
1128 |
|
|
(ABSOLUTE
|
1129 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1130 |
|
|
(IOPATH I3 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
1131 |
|
|
(IOPATH I2 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
1132 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1133 |
|
|
(IOPATH I0 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
1134 |
|
|
)
|
1135 |
|
|
)
|
1136 |
|
|
)
|
1137 |
|
|
(CELL
|
1138 |
|
|
(CELLTYPE "LUT4")
|
1139 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2)
|
1140 |
|
|
(DELAY
|
1141 |
|
|
(PATHPULSE (50.0))
|
1142 |
|
|
(ABSOLUTE
|
1143 |
|
|
(IOPATH I3 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
1144 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1145 |
|
|
(IOPATH I1 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
1146 |
|
|
(IOPATH I0 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
1147 |
|
|
)
|
1148 |
|
|
)
|
1149 |
|
|
)
|
1150 |
|
|
(CELL
|
1151 |
|
|
(CELLTYPE "LUT6")
|
1152 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1)
|
1153 |
|
|
(DELAY
|
1154 |
|
|
(PATHPULSE (50.0))
|
1155 |
|
|
(ABSOLUTE
|
1156 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1157 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1158 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1159 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1160 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1161 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1162 |
|
|
)
|
1163 |
|
|
)
|
1164 |
|
|
)
|
1165 |
|
|
(CELL
|
1166 |
|
|
(CELLTYPE "LUT4")
|
1167 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1)
|
1168 |
|
|
(DELAY
|
1169 |
|
|
(PATHPULSE (50.0))
|
1170 |
|
|
(ABSOLUTE
|
1171 |
|
|
(IOPATH I3 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1172 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1173 |
|
|
(IOPATH I1 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
1174 |
|
|
(IOPATH I0 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
1175 |
|
|
)
|
1176 |
|
|
)
|
1177 |
|
|
)
|
1178 |
|
|
(CELL
|
1179 |
|
|
(CELLTYPE "LUT4")
|
1180 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1)
|
1181 |
|
|
(DELAY
|
1182 |
|
|
(PATHPULSE (50.0))
|
1183 |
|
|
(ABSOLUTE
|
1184 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1185 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1186 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1187 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1188 |
|
|
)
|
1189 |
|
|
)
|
1190 |
|
|
)
|
1191 |
|
|
(CELL
|
1192 |
|
|
(CELLTYPE "LUT5")
|
1193 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2)
|
1194 |
|
|
(DELAY
|
1195 |
|
|
(PATHPULSE (50.0))
|
1196 |
|
|
(ABSOLUTE
|
1197 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1198 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1199 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1200 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1201 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1202 |
|
|
)
|
1203 |
|
|
)
|
1204 |
|
|
)
|
1205 |
|
|
(CELL
|
1206 |
|
|
(CELLTYPE "FDRE")
|
1207 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\])
|
1208 |
|
|
(DELAY
|
1209 |
|
|
(ABSOLUTE
|
1210 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1211 |
|
|
)
|
1212 |
|
|
)
|
1213 |
|
|
(TIMINGCHECK
|
1214 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1215 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1216 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1217 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1218 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1219 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1220 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1221 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1222 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1223 |
|
|
)
|
1224 |
|
|
)
|
1225 |
|
|
(CELL
|
1226 |
|
|
(CELLTYPE "FDRE")
|
1227 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\])
|
1228 |
|
|
(DELAY
|
1229 |
|
|
(ABSOLUTE
|
1230 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1231 |
|
|
)
|
1232 |
|
|
)
|
1233 |
|
|
(TIMINGCHECK
|
1234 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1235 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1236 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1237 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1238 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1239 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1240 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1241 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1242 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1243 |
|
|
)
|
1244 |
|
|
)
|
1245 |
|
|
(CELL
|
1246 |
|
|
(CELLTYPE "FDRE")
|
1247 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\])
|
1248 |
|
|
(DELAY
|
1249 |
|
|
(ABSOLUTE
|
1250 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1251 |
|
|
)
|
1252 |
|
|
)
|
1253 |
|
|
(TIMINGCHECK
|
1254 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1255 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1256 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1257 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1258 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1259 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1260 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1261 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1262 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1263 |
|
|
)
|
1264 |
|
|
)
|
1265 |
|
|
(CELL
|
1266 |
|
|
(CELLTYPE "FDRE")
|
1267 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\])
|
1268 |
|
|
(DELAY
|
1269 |
|
|
(ABSOLUTE
|
1270 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1271 |
|
|
)
|
1272 |
|
|
)
|
1273 |
|
|
(TIMINGCHECK
|
1274 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1275 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1276 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1277 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1278 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1279 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1280 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1281 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1282 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1283 |
|
|
)
|
1284 |
|
|
)
|
1285 |
|
|
(CELL
|
1286 |
|
|
(CELLTYPE "FDRE")
|
1287 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\])
|
1288 |
|
|
(DELAY
|
1289 |
|
|
(ABSOLUTE
|
1290 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1291 |
|
|
)
|
1292 |
|
|
)
|
1293 |
|
|
(TIMINGCHECK
|
1294 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1295 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1296 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1297 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1298 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1299 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1300 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1301 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1302 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1303 |
|
|
)
|
1304 |
|
|
)
|
1305 |
|
|
(CELL
|
1306 |
|
|
(CELLTYPE "FDRE")
|
1307 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\])
|
1308 |
|
|
(DELAY
|
1309 |
|
|
(ABSOLUTE
|
1310 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1311 |
|
|
)
|
1312 |
|
|
)
|
1313 |
|
|
(TIMINGCHECK
|
1314 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1315 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1316 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1317 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1318 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1319 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1320 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1321 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1322 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1323 |
|
|
)
|
1324 |
|
|
)
|
1325 |
|
|
(CELL
|
1326 |
|
|
(CELLTYPE "FDRE")
|
1327 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\])
|
1328 |
|
|
(DELAY
|
1329 |
|
|
(ABSOLUTE
|
1330 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
1331 |
|
|
)
|
1332 |
|
|
)
|
1333 |
|
|
(TIMINGCHECK
|
1334 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1335 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1336 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
1337 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
1338 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1339 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1340 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
1341 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1342 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
1343 |
|
|
)
|
1344 |
|
|
)
|
1345 |
|
|
(CELL
|
1346 |
|
|
(CELLTYPE "FDRE")
|
1347 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\])
|
1348 |
|
|
(DELAY
|
1349 |
|
|
(ABSOLUTE
|
1350 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1351 |
|
|
)
|
1352 |
|
|
)
|
1353 |
|
|
(TIMINGCHECK
|
1354 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1355 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1356 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1357 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1358 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1359 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1360 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1361 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1362 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1363 |
|
|
)
|
1364 |
|
|
)
|
1365 |
|
|
(CELL
|
1366 |
|
|
(CELLTYPE "FDRE")
|
1367 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/Interrupt_reg)
|
1368 |
|
|
(DELAY
|
1369 |
|
|
(ABSOLUTE
|
1370 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1371 |
|
|
)
|
1372 |
|
|
)
|
1373 |
|
|
(TIMINGCHECK
|
1374 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1375 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1376 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1377 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1378 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1379 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1380 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1381 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1382 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1383 |
|
|
)
|
1384 |
|
|
)
|
1385 |
|
|
(CELL
|
1386 |
|
|
(CELLTYPE "SRL16E")
|
1387 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15)
|
1388 |
|
|
(DELAY
|
1389 |
|
|
(ABSOLUTE
|
1390 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
1391 |
|
|
(IOPATH A3 Q (39.0:47.0:47.0) (39.0:47.0:47.0))
|
1392 |
|
|
(IOPATH A2 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1393 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1394 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
1395 |
|
|
)
|
1396 |
|
|
)
|
1397 |
|
|
(TIMINGCHECK
|
1398 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
1399 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
1400 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
1401 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
1402 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
1403 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
1404 |
|
|
)
|
1405 |
|
|
)
|
1406 |
|
|
(CELL
|
1407 |
|
|
(CELLTYPE "LUT4")
|
1408 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1)
|
1409 |
|
|
(DELAY
|
1410 |
|
|
(PATHPULSE (50.0))
|
1411 |
|
|
(ABSOLUTE
|
1412 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1413 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1414 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1415 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1416 |
|
|
)
|
1417 |
|
|
)
|
1418 |
|
|
)
|
1419 |
|
|
(CELL
|
1420 |
|
|
(CELLTYPE "FDRE")
|
1421 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\])
|
1422 |
|
|
(DELAY
|
1423 |
|
|
(ABSOLUTE
|
1424 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
1425 |
|
|
)
|
1426 |
|
|
)
|
1427 |
|
|
(TIMINGCHECK
|
1428 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1429 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1430 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1431 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1432 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1433 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1434 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
1435 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1436 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
1437 |
|
|
)
|
1438 |
|
|
)
|
1439 |
|
|
(CELL
|
1440 |
|
|
(CELLTYPE "LUT5")
|
1441 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1)
|
1442 |
|
|
(DELAY
|
1443 |
|
|
(PATHPULSE (50.0))
|
1444 |
|
|
(ABSOLUTE
|
1445 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1446 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1447 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1448 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1449 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1450 |
|
|
)
|
1451 |
|
|
)
|
1452 |
|
|
)
|
1453 |
|
|
(CELL
|
1454 |
|
|
(CELLTYPE "LUT5")
|
1455 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1)
|
1456 |
|
|
(DELAY
|
1457 |
|
|
(PATHPULSE (50.0))
|
1458 |
|
|
(ABSOLUTE
|
1459 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1460 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1461 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1462 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1463 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1464 |
|
|
)
|
1465 |
|
|
)
|
1466 |
|
|
)
|
1467 |
|
|
(CELL
|
1468 |
|
|
(CELLTYPE "LUT5")
|
1469 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1)
|
1470 |
|
|
(DELAY
|
1471 |
|
|
(PATHPULSE (50.0))
|
1472 |
|
|
(ABSOLUTE
|
1473 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1474 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1475 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1476 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1477 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1478 |
|
|
)
|
1479 |
|
|
)
|
1480 |
|
|
)
|
1481 |
|
|
(CELL
|
1482 |
|
|
(CELLTYPE "LUT5")
|
1483 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1)
|
1484 |
|
|
(DELAY
|
1485 |
|
|
(PATHPULSE (50.0))
|
1486 |
|
|
(ABSOLUTE
|
1487 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1488 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1489 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1490 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1491 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1492 |
|
|
)
|
1493 |
|
|
)
|
1494 |
|
|
)
|
1495 |
|
|
(CELL
|
1496 |
|
|
(CELLTYPE "LUT5")
|
1497 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1)
|
1498 |
|
|
(DELAY
|
1499 |
|
|
(PATHPULSE (50.0))
|
1500 |
|
|
(ABSOLUTE
|
1501 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1502 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1503 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1504 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1505 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1506 |
|
|
)
|
1507 |
|
|
)
|
1508 |
|
|
)
|
1509 |
|
|
(CELL
|
1510 |
|
|
(CELLTYPE "LUT5")
|
1511 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1)
|
1512 |
|
|
(DELAY
|
1513 |
|
|
(PATHPULSE (50.0))
|
1514 |
|
|
(ABSOLUTE
|
1515 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1516 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1517 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1518 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1519 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1520 |
|
|
)
|
1521 |
|
|
)
|
1522 |
|
|
)
|
1523 |
|
|
(CELL
|
1524 |
|
|
(CELLTYPE "LUT5")
|
1525 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1)
|
1526 |
|
|
(DELAY
|
1527 |
|
|
(PATHPULSE (50.0))
|
1528 |
|
|
(ABSOLUTE
|
1529 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1530 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1531 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1532 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1533 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1534 |
|
|
)
|
1535 |
|
|
)
|
1536 |
|
|
)
|
1537 |
|
|
(CELL
|
1538 |
|
|
(CELLTYPE "LUT3")
|
1539 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2)
|
1540 |
|
|
(DELAY
|
1541 |
|
|
(PATHPULSE (50.0))
|
1542 |
|
|
(ABSOLUTE
|
1543 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1544 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1545 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1546 |
|
|
)
|
1547 |
|
|
)
|
1548 |
|
|
)
|
1549 |
|
|
(CELL
|
1550 |
|
|
(CELLTYPE "LUT4")
|
1551 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1)
|
1552 |
|
|
(DELAY
|
1553 |
|
|
(PATHPULSE (50.0))
|
1554 |
|
|
(ABSOLUTE
|
1555 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1556 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1557 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1558 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1559 |
|
|
)
|
1560 |
|
|
)
|
1561 |
|
|
)
|
1562 |
|
|
(CELL
|
1563 |
|
|
(CELLTYPE "LUT5")
|
1564 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1)
|
1565 |
|
|
(DELAY
|
1566 |
|
|
(PATHPULSE (50.0))
|
1567 |
|
|
(ABSOLUTE
|
1568 |
|
|
(IOPATH I4 O (46.0:55.0:55.0) (46.0:55.0:55.0))
|
1569 |
|
|
(IOPATH I3 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
1570 |
|
|
(IOPATH I2 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
1571 |
|
|
(IOPATH I1 O (44.0:54.0:54.0) (44.0:54.0:54.0))
|
1572 |
|
|
(IOPATH I0 O (45.0:54.0:54.0) (45.0:54.0:54.0))
|
1573 |
|
|
)
|
1574 |
|
|
)
|
1575 |
|
|
)
|
1576 |
|
|
(CELL
|
1577 |
|
|
(CELLTYPE "LUT5")
|
1578 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1)
|
1579 |
|
|
(DELAY
|
1580 |
|
|
(PATHPULSE (50.0))
|
1581 |
|
|
(ABSOLUTE
|
1582 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1583 |
|
|
(IOPATH I3 O (42.0:49.0:49.0) (42.0:49.0:49.0))
|
1584 |
|
|
(IOPATH I2 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
1585 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1586 |
|
|
(IOPATH I0 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
1587 |
|
|
)
|
1588 |
|
|
)
|
1589 |
|
|
)
|
1590 |
|
|
(CELL
|
1591 |
|
|
(CELLTYPE "LUT5")
|
1592 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1)
|
1593 |
|
|
(DELAY
|
1594 |
|
|
(PATHPULSE (50.0))
|
1595 |
|
|
(ABSOLUTE
|
1596 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1597 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1598 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1599 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1600 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1601 |
|
|
)
|
1602 |
|
|
)
|
1603 |
|
|
)
|
1604 |
|
|
(CELL
|
1605 |
|
|
(CELLTYPE "LUT3")
|
1606 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_2)
|
1607 |
|
|
(DELAY
|
1608 |
|
|
(PATHPULSE (50.0))
|
1609 |
|
|
(ABSOLUTE
|
1610 |
|
|
(IOPATH I2 O (42.0:50.0:50.0) (42.0:50.0:50.0))
|
1611 |
|
|
(IOPATH I1 O (39.0:48.0:48.0) (39.0:48.0:48.0))
|
1612 |
|
|
(IOPATH I0 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
1613 |
|
|
)
|
1614 |
|
|
)
|
1615 |
|
|
)
|
1616 |
|
|
(CELL
|
1617 |
|
|
(CELLTYPE "LUT4")
|
1618 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1)
|
1619 |
|
|
(DELAY
|
1620 |
|
|
(PATHPULSE (50.0))
|
1621 |
|
|
(ABSOLUTE
|
1622 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1623 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1624 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1625 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1626 |
|
|
)
|
1627 |
|
|
)
|
1628 |
|
|
)
|
1629 |
|
|
(CELL
|
1630 |
|
|
(CELLTYPE "FDRE")
|
1631 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)
|
1632 |
|
|
(DELAY
|
1633 |
|
|
(ABSOLUTE
|
1634 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1635 |
|
|
)
|
1636 |
|
|
)
|
1637 |
|
|
(TIMINGCHECK
|
1638 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1639 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1640 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1641 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1642 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1643 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1644 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1645 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1646 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1647 |
|
|
)
|
1648 |
|
|
)
|
1649 |
|
|
(CELL
|
1650 |
|
|
(CELLTYPE "FDRE")
|
1651 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)
|
1652 |
|
|
(DELAY
|
1653 |
|
|
(ABSOLUTE
|
1654 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
1655 |
|
|
)
|
1656 |
|
|
)
|
1657 |
|
|
(TIMINGCHECK
|
1658 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1659 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1660 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1661 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1662 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1663 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1664 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
1665 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1666 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
1667 |
|
|
)
|
1668 |
|
|
)
|
1669 |
|
|
(CELL
|
1670 |
|
|
(CELLTYPE "FDRE")
|
1671 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)
|
1672 |
|
|
(DELAY
|
1673 |
|
|
(ABSOLUTE
|
1674 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
1675 |
|
|
)
|
1676 |
|
|
)
|
1677 |
|
|
(TIMINGCHECK
|
1678 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1679 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1680 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1681 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
1682 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1683 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1684 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
1685 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1686 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
1687 |
|
|
)
|
1688 |
|
|
)
|
1689 |
|
|
(CELL
|
1690 |
|
|
(CELLTYPE "FDRE")
|
1691 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)
|
1692 |
|
|
(DELAY
|
1693 |
|
|
(ABSOLUTE
|
1694 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1695 |
|
|
)
|
1696 |
|
|
)
|
1697 |
|
|
(TIMINGCHECK
|
1698 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1699 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1700 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1701 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1702 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1703 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1704 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1705 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1706 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1707 |
|
|
)
|
1708 |
|
|
)
|
1709 |
|
|
(CELL
|
1710 |
|
|
(CELLTYPE "LUT5")
|
1711 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1)
|
1712 |
|
|
(DELAY
|
1713 |
|
|
(PATHPULSE (50.0))
|
1714 |
|
|
(ABSOLUTE
|
1715 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1716 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1717 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1718 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1719 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1720 |
|
|
)
|
1721 |
|
|
)
|
1722 |
|
|
)
|
1723 |
|
|
(CELL
|
1724 |
|
|
(CELLTYPE "FDRE")
|
1725 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[1\]\.fifo_din_reg\[1\])
|
1726 |
|
|
(DELAY
|
1727 |
|
|
(ABSOLUTE
|
1728 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1729 |
|
|
)
|
1730 |
|
|
)
|
1731 |
|
|
(TIMINGCHECK
|
1732 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1733 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1734 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1735 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1736 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1737 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1738 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1739 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1740 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1741 |
|
|
)
|
1742 |
|
|
)
|
1743 |
|
|
(CELL
|
1744 |
|
|
(CELLTYPE "FDRE")
|
1745 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din_reg\[2\])
|
1746 |
|
|
(DELAY
|
1747 |
|
|
(ABSOLUTE
|
1748 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1749 |
|
|
)
|
1750 |
|
|
)
|
1751 |
|
|
(TIMINGCHECK
|
1752 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1753 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1754 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1755 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1756 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1757 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1758 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1759 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1760 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1761 |
|
|
)
|
1762 |
|
|
)
|
1763 |
|
|
(CELL
|
1764 |
|
|
(CELLTYPE "FDRE")
|
1765 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din_reg\[3\])
|
1766 |
|
|
(DELAY
|
1767 |
|
|
(ABSOLUTE
|
1768 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
1769 |
|
|
)
|
1770 |
|
|
)
|
1771 |
|
|
(TIMINGCHECK
|
1772 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1773 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
1774 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1775 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
1776 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1777 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
1778 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1779 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1780 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1781 |
|
|
)
|
1782 |
|
|
)
|
1783 |
|
|
(CELL
|
1784 |
|
|
(CELLTYPE "FDRE")
|
1785 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din_reg\[4\])
|
1786 |
|
|
(DELAY
|
1787 |
|
|
(ABSOLUTE
|
1788 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1789 |
|
|
)
|
1790 |
|
|
)
|
1791 |
|
|
(TIMINGCHECK
|
1792 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1793 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1794 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1795 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1796 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1797 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1798 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1799 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1800 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1801 |
|
|
)
|
1802 |
|
|
)
|
1803 |
|
|
(CELL
|
1804 |
|
|
(CELLTYPE "FDRE")
|
1805 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din_reg\[5\])
|
1806 |
|
|
(DELAY
|
1807 |
|
|
(ABSOLUTE
|
1808 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1809 |
|
|
)
|
1810 |
|
|
)
|
1811 |
|
|
(TIMINGCHECK
|
1812 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1813 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1814 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1815 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1816 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1817 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1818 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1819 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1820 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1821 |
|
|
)
|
1822 |
|
|
)
|
1823 |
|
|
(CELL
|
1824 |
|
|
(CELLTYPE "FDRE")
|
1825 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din_reg\[6\])
|
1826 |
|
|
(DELAY
|
1827 |
|
|
(ABSOLUTE
|
1828 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1829 |
|
|
)
|
1830 |
|
|
)
|
1831 |
|
|
(TIMINGCHECK
|
1832 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1833 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1834 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1835 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1836 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1837 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1838 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1839 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1840 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1841 |
|
|
)
|
1842 |
|
|
)
|
1843 |
|
|
(CELL
|
1844 |
|
|
(CELLTYPE "FDRE")
|
1845 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din_reg\[7\])
|
1846 |
|
|
(DELAY
|
1847 |
|
|
(ABSOLUTE
|
1848 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1849 |
|
|
)
|
1850 |
|
|
)
|
1851 |
|
|
(TIMINGCHECK
|
1852 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1853 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1854 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1855 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1856 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1857 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1858 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1859 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1860 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1861 |
|
|
)
|
1862 |
|
|
)
|
1863 |
|
|
(CELL
|
1864 |
|
|
(CELLTYPE "FDRE")
|
1865 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din_reg\[8\])
|
1866 |
|
|
(DELAY
|
1867 |
|
|
(ABSOLUTE
|
1868 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
1869 |
|
|
)
|
1870 |
|
|
)
|
1871 |
|
|
(TIMINGCHECK
|
1872 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1873 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
1874 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1875 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
1876 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1877 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
1878 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
1879 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1880 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
1881 |
|
|
)
|
1882 |
|
|
)
|
1883 |
|
|
(CELL
|
1884 |
|
|
(CELLTYPE "LUT6")
|
1885 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1)
|
1886 |
|
|
(DELAY
|
1887 |
|
|
(PATHPULSE (50.0))
|
1888 |
|
|
(ABSOLUTE
|
1889 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1890 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1891 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1892 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1893 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1894 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1895 |
|
|
)
|
1896 |
|
|
)
|
1897 |
|
|
)
|
1898 |
|
|
(CELL
|
1899 |
|
|
(CELLTYPE "LUT2")
|
1900 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2)
|
1901 |
|
|
(DELAY
|
1902 |
|
|
(PATHPULSE (50.0))
|
1903 |
|
|
(ABSOLUTE
|
1904 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1905 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1906 |
|
|
)
|
1907 |
|
|
)
|
1908 |
|
|
)
|
1909 |
|
|
(CELL
|
1910 |
|
|
(CELLTYPE "LUT5")
|
1911 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1)
|
1912 |
|
|
(DELAY
|
1913 |
|
|
(PATHPULSE (50.0))
|
1914 |
|
|
(ABSOLUTE
|
1915 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1916 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1917 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1918 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1919 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1920 |
|
|
)
|
1921 |
|
|
)
|
1922 |
|
|
)
|
1923 |
|
|
(CELL
|
1924 |
|
|
(CELLTYPE "LUT6")
|
1925 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1)
|
1926 |
|
|
(DELAY
|
1927 |
|
|
(PATHPULSE (50.0))
|
1928 |
|
|
(ABSOLUTE
|
1929 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1930 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1931 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1932 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1933 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1934 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1935 |
|
|
)
|
1936 |
|
|
)
|
1937 |
|
|
)
|
1938 |
|
|
(CELL
|
1939 |
|
|
(CELLTYPE "LUT5")
|
1940 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1)
|
1941 |
|
|
(DELAY
|
1942 |
|
|
(PATHPULSE (50.0))
|
1943 |
|
|
(ABSOLUTE
|
1944 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1945 |
|
|
(IOPATH I3 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
1946 |
|
|
(IOPATH I2 O (39.0:47.0:47.0) (39.0:47.0:47.0))
|
1947 |
|
|
(IOPATH I1 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
1948 |
|
|
(IOPATH I0 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
1949 |
|
|
)
|
1950 |
|
|
)
|
1951 |
|
|
)
|
1952 |
|
|
(CELL
|
1953 |
|
|
(CELLTYPE "LUT6")
|
1954 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1)
|
1955 |
|
|
(DELAY
|
1956 |
|
|
(PATHPULSE (50.0))
|
1957 |
|
|
(ABSOLUTE
|
1958 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1959 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1960 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1961 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1962 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1963 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1964 |
|
|
)
|
1965 |
|
|
)
|
1966 |
|
|
)
|
1967 |
|
|
(CELL
|
1968 |
|
|
(CELLTYPE "LUT2")
|
1969 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1)
|
1970 |
|
|
(DELAY
|
1971 |
|
|
(PATHPULSE (50.0))
|
1972 |
|
|
(ABSOLUTE
|
1973 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1974 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1975 |
|
|
)
|
1976 |
|
|
)
|
1977 |
|
|
)
|
1978 |
|
|
(CELL
|
1979 |
|
|
(CELLTYPE "LUT6")
|
1980 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2)
|
1981 |
|
|
(DELAY
|
1982 |
|
|
(PATHPULSE (50.0))
|
1983 |
|
|
(ABSOLUTE
|
1984 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1985 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1986 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1987 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1988 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1989 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
1990 |
|
|
)
|
1991 |
|
|
)
|
1992 |
|
|
)
|
1993 |
|
|
(CELL
|
1994 |
|
|
(CELLTYPE "LUT3")
|
1995 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4)
|
1996 |
|
|
(DELAY
|
1997 |
|
|
(PATHPULSE (50.0))
|
1998 |
|
|
(ABSOLUTE
|
1999 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2000 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2001 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2002 |
|
|
)
|
2003 |
|
|
)
|
2004 |
|
|
)
|
2005 |
|
|
(CELL
|
2006 |
|
|
(CELLTYPE "LUT3")
|
2007 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_5__0)
|
2008 |
|
|
(DELAY
|
2009 |
|
|
(PATHPULSE (50.0))
|
2010 |
|
|
(ABSOLUTE
|
2011 |
|
|
(IOPATH I2 O (44.0:52.0:52.0) (44.0:52.0:52.0))
|
2012 |
|
|
(IOPATH I1 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2013 |
|
|
(IOPATH I0 O (40.0:49.0:49.0) (40.0:49.0:49.0))
|
2014 |
|
|
)
|
2015 |
|
|
)
|
2016 |
|
|
)
|
2017 |
|
|
(CELL
|
2018 |
|
|
(CELLTYPE "LUT3")
|
2019 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6)
|
2020 |
|
|
(DELAY
|
2021 |
|
|
(PATHPULSE (50.0))
|
2022 |
|
|
(ABSOLUTE
|
2023 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2024 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2025 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2026 |
|
|
)
|
2027 |
|
|
)
|
2028 |
|
|
)
|
2029 |
|
|
(CELL
|
2030 |
|
|
(CELLTYPE "FDSE")
|
2031 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\])
|
2032 |
|
|
(DELAY
|
2033 |
|
|
(ABSOLUTE
|
2034 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2035 |
|
|
)
|
2036 |
|
|
)
|
2037 |
|
|
(TIMINGCHECK
|
2038 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2039 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2040 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2041 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2042 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2043 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2044 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2045 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2046 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2047 |
|
|
)
|
2048 |
|
|
)
|
2049 |
|
|
(CELL
|
2050 |
|
|
(CELLTYPE "FDSE")
|
2051 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\])
|
2052 |
|
|
(DELAY
|
2053 |
|
|
(ABSOLUTE
|
2054 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2055 |
|
|
)
|
2056 |
|
|
)
|
2057 |
|
|
(TIMINGCHECK
|
2058 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2059 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2060 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2061 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2062 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2063 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2064 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2065 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2066 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2067 |
|
|
)
|
2068 |
|
|
)
|
2069 |
|
|
(CELL
|
2070 |
|
|
(CELLTYPE "FDSE")
|
2071 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\])
|
2072 |
|
|
(DELAY
|
2073 |
|
|
(ABSOLUTE
|
2074 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2075 |
|
|
)
|
2076 |
|
|
)
|
2077 |
|
|
(TIMINGCHECK
|
2078 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2079 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2080 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2081 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2082 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2083 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2084 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2085 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2086 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2087 |
|
|
)
|
2088 |
|
|
)
|
2089 |
|
|
(CELL
|
2090 |
|
|
(CELLTYPE "FDSE")
|
2091 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\])
|
2092 |
|
|
(DELAY
|
2093 |
|
|
(ABSOLUTE
|
2094 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2095 |
|
|
)
|
2096 |
|
|
)
|
2097 |
|
|
(TIMINGCHECK
|
2098 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2099 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2100 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2101 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2102 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2103 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2104 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2105 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2106 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2107 |
|
|
)
|
2108 |
|
|
)
|
2109 |
|
|
(CELL
|
2110 |
|
|
(CELLTYPE "FDSE")
|
2111 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\])
|
2112 |
|
|
(DELAY
|
2113 |
|
|
(ABSOLUTE
|
2114 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2115 |
|
|
)
|
2116 |
|
|
)
|
2117 |
|
|
(TIMINGCHECK
|
2118 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2119 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2120 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2121 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2122 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2123 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2124 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2125 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2126 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2127 |
|
|
)
|
2128 |
|
|
)
|
2129 |
|
|
(CELL
|
2130 |
|
|
(CELLTYPE "LUT5")
|
2131 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2)
|
2132 |
|
|
(DELAY
|
2133 |
|
|
(PATHPULSE (50.0))
|
2134 |
|
|
(ABSOLUTE
|
2135 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2136 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2137 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2138 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2139 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2140 |
|
|
)
|
2141 |
|
|
)
|
2142 |
|
|
)
|
2143 |
|
|
(CELL
|
2144 |
|
|
(CELLTYPE "SRL16E")
|
2145 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16)
|
2146 |
|
|
(DELAY
|
2147 |
|
|
(ABSOLUTE
|
2148 |
|
|
(IOPATH CLK Q (731.0:916.0:916.0) (731.0:916.0:916.0))
|
2149 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2150 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2151 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2152 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2153 |
|
|
)
|
2154 |
|
|
)
|
2155 |
|
|
(TIMINGCHECK
|
2156 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2157 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2158 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (79.0:98.0:98.0) (71.0:71.0:71.0))
|
2159 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (79.0:98.0:98.0) (71.0:71.0:71.0))
|
2160 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2161 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2162 |
|
|
)
|
2163 |
|
|
)
|
2164 |
|
|
(CELL
|
2165 |
|
|
(CELLTYPE "SRL16E")
|
2166 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16)
|
2167 |
|
|
(DELAY
|
2168 |
|
|
(ABSOLUTE
|
2169 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
2170 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2171 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2172 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2173 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2174 |
|
|
)
|
2175 |
|
|
)
|
2176 |
|
|
(TIMINGCHECK
|
2177 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2178 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2179 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (77.0:97.0:97.0) (81.0:81.0:81.0))
|
2180 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (77.0:97.0:97.0) (81.0:81.0:81.0))
|
2181 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2182 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2183 |
|
|
)
|
2184 |
|
|
)
|
2185 |
|
|
(CELL
|
2186 |
|
|
(CELLTYPE "SRL16E")
|
2187 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16)
|
2188 |
|
|
(DELAY
|
2189 |
|
|
(ABSOLUTE
|
2190 |
|
|
(IOPATH CLK Q (715.0:896.0:896.0) (715.0:896.0:896.0))
|
2191 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2192 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2193 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2194 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2195 |
|
|
)
|
2196 |
|
|
)
|
2197 |
|
|
(TIMINGCHECK
|
2198 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2199 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2200 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (91.0:114.0:114.0) (60.0:60.0:60.0))
|
2201 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (91.0:114.0:114.0) (60.0:60.0:60.0))
|
2202 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2203 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2204 |
|
|
)
|
2205 |
|
|
)
|
2206 |
|
|
(CELL
|
2207 |
|
|
(CELLTYPE "SRL16E")
|
2208 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16)
|
2209 |
|
|
(DELAY
|
2210 |
|
|
(ABSOLUTE
|
2211 |
|
|
(IOPATH CLK Q (719.0:901.0:901.0) (719.0:901.0:901.0))
|
2212 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2213 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2214 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2215 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2216 |
|
|
)
|
2217 |
|
|
)
|
2218 |
|
|
(TIMINGCHECK
|
2219 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2220 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2221 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (81.0:101.0:101.0) (76.0:76.0:76.0))
|
2222 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (81.0:101.0:101.0) (76.0:76.0:76.0))
|
2223 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2224 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2225 |
|
|
)
|
2226 |
|
|
)
|
2227 |
|
|
(CELL
|
2228 |
|
|
(CELLTYPE "SRL16E")
|
2229 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16)
|
2230 |
|
|
(DELAY
|
2231 |
|
|
(ABSOLUTE
|
2232 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
2233 |
|
|
(IOPATH A3 Q (39.0:47.0:47.0) (39.0:47.0:47.0))
|
2234 |
|
|
(IOPATH A2 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2235 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2236 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2237 |
|
|
)
|
2238 |
|
|
)
|
2239 |
|
|
(TIMINGCHECK
|
2240 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2241 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2242 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
2243 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
2244 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2245 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2246 |
|
|
)
|
2247 |
|
|
)
|
2248 |
|
|
(CELL
|
2249 |
|
|
(CELLTYPE "SRL16E")
|
2250 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16)
|
2251 |
|
|
(DELAY
|
2252 |
|
|
(ABSOLUTE
|
2253 |
|
|
(IOPATH CLK Q (725.0:909.0:909.0) (725.0:909.0:909.0))
|
2254 |
|
|
(IOPATH A3 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2255 |
|
|
(IOPATH A2 Q (45.0:53.0:53.0) (45.0:53.0:53.0))
|
2256 |
|
|
(IOPATH A1 Q (45.0:53.0:53.0) (45.0:53.0:53.0))
|
2257 |
|
|
(IOPATH A0 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2258 |
|
|
)
|
2259 |
|
|
)
|
2260 |
|
|
(TIMINGCHECK
|
2261 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2262 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2263 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (74.0:93.0:93.0) (82.0:82.0:82.0))
|
2264 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (74.0:93.0:93.0) (82.0:82.0:82.0))
|
2265 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2266 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2267 |
|
|
)
|
2268 |
|
|
)
|
2269 |
|
|
(CELL
|
2270 |
|
|
(CELLTYPE "SRL16E")
|
2271 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16)
|
2272 |
|
|
(DELAY
|
2273 |
|
|
(ABSOLUTE
|
2274 |
|
|
(IOPATH CLK Q (716.0:897.0:897.0) (716.0:897.0:897.0))
|
2275 |
|
|
(IOPATH A3 Q (38.0:45.0:45.0) (38.0:45.0:45.0))
|
2276 |
|
|
(IOPATH A2 Q (42.0:49.0:49.0) (42.0:49.0:49.0))
|
2277 |
|
|
(IOPATH A1 Q (42.0:50.0:50.0) (42.0:50.0:50.0))
|
2278 |
|
|
(IOPATH A0 Q (39.0:46.0:46.0) (39.0:46.0:46.0))
|
2279 |
|
|
)
|
2280 |
|
|
)
|
2281 |
|
|
(TIMINGCHECK
|
2282 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2283 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2284 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (82.0:103.0:103.0) (70.0:70.0:70.0))
|
2285 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (82.0:103.0:103.0) (70.0:70.0:70.0))
|
2286 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2287 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2288 |
|
|
)
|
2289 |
|
|
)
|
2290 |
|
|
(CELL
|
2291 |
|
|
(CELLTYPE "SRL16E")
|
2292 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16)
|
2293 |
|
|
(DELAY
|
2294 |
|
|
(ABSOLUTE
|
2295 |
|
|
(IOPATH CLK Q (727.0:911.0:911.0) (727.0:911.0:911.0))
|
2296 |
|
|
(IOPATH A3 Q (38.0:46.0:46.0) (38.0:46.0:46.0))
|
2297 |
|
|
(IOPATH A2 Q (42.0:50.0:50.0) (42.0:50.0:50.0))
|
2298 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2299 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2300 |
|
|
)
|
2301 |
|
|
)
|
2302 |
|
|
(TIMINGCHECK
|
2303 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2304 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2305 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (-3.0:-2.0:-2.0) (176.0:176.0:176.0))
|
2306 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (-3.0:-2.0:-2.0) (176.0:176.0:176.0))
|
2307 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2308 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2309 |
|
|
)
|
2310 |
|
|
)
|
2311 |
|
|
(CELL
|
2312 |
|
|
(CELLTYPE "LUT3")
|
2313 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0)
|
2314 |
|
|
(DELAY
|
2315 |
|
|
(PATHPULSE (50.0))
|
2316 |
|
|
(ABSOLUTE
|
2317 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2318 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2319 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2320 |
|
|
)
|
2321 |
|
|
)
|
2322 |
|
|
)
|
2323 |
|
|
(CELL
|
2324 |
|
|
(CELLTYPE "FDRE")
|
2325 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg)
|
2326 |
|
|
(DELAY
|
2327 |
|
|
(ABSOLUTE
|
2328 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2329 |
|
|
)
|
2330 |
|
|
)
|
2331 |
|
|
(TIMINGCHECK
|
2332 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2333 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2334 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2335 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2336 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2337 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2338 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2339 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2340 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2341 |
|
|
)
|
2342 |
|
|
)
|
2343 |
|
|
(CELL
|
2344 |
|
|
(CELLTYPE "LUT5")
|
2345 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1)
|
2346 |
|
|
(DELAY
|
2347 |
|
|
(PATHPULSE (50.0))
|
2348 |
|
|
(ABSOLUTE
|
2349 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2350 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2351 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2352 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2353 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2354 |
|
|
)
|
2355 |
|
|
)
|
2356 |
|
|
)
|
2357 |
|
|
(CELL
|
2358 |
|
|
(CELLTYPE "FDRE")
|
2359 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg)
|
2360 |
|
|
(DELAY
|
2361 |
|
|
(ABSOLUTE
|
2362 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2363 |
|
|
)
|
2364 |
|
|
)
|
2365 |
|
|
(TIMINGCHECK
|
2366 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2367 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2368 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2369 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2370 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2371 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2372 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2373 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2374 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2375 |
|
|
)
|
2376 |
|
|
)
|
2377 |
|
|
(CELL
|
2378 |
|
|
(CELLTYPE "FDRE")
|
2379 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/frame_err_ocrd_reg)
|
2380 |
|
|
(DELAY
|
2381 |
|
|
(ABSOLUTE
|
2382 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
2383 |
|
|
)
|
2384 |
|
|
)
|
2385 |
|
|
(TIMINGCHECK
|
2386 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2387 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2388 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
2389 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
2390 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2391 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2392 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
2393 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2394 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
2395 |
|
|
)
|
2396 |
|
|
)
|
2397 |
|
|
(CELL
|
2398 |
|
|
(CELLTYPE "FDRE")
|
2399 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/running_reg)
|
2400 |
|
|
(DELAY
|
2401 |
|
|
(ABSOLUTE
|
2402 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2403 |
|
|
)
|
2404 |
|
|
)
|
2405 |
|
|
(TIMINGCHECK
|
2406 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2407 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2408 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2409 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2410 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2411 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2412 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2413 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2414 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2415 |
|
|
)
|
2416 |
|
|
)
|
2417 |
|
|
(CELL
|
2418 |
|
|
(CELLTYPE "FDRE")
|
2419 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_1_reg)
|
2420 |
|
|
(DELAY
|
2421 |
|
|
(ABSOLUTE
|
2422 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2423 |
|
|
)
|
2424 |
|
|
)
|
2425 |
|
|
(TIMINGCHECK
|
2426 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2427 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2428 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2429 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2430 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2431 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2432 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2433 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2434 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2435 |
|
|
)
|
2436 |
|
|
)
|
2437 |
|
|
(CELL
|
2438 |
|
|
(CELLTYPE "FDRE")
|
2439 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2_reg)
|
2440 |
|
|
(DELAY
|
2441 |
|
|
(ABSOLUTE
|
2442 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
2443 |
|
|
)
|
2444 |
|
|
)
|
2445 |
|
|
(TIMINGCHECK
|
2446 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2447 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2448 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2449 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2450 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2451 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2452 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
2453 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2454 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
2455 |
|
|
)
|
2456 |
|
|
)
|
2457 |
|
|
(CELL
|
2458 |
|
|
(CELLTYPE "FDRE")
|
2459 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_3_reg)
|
2460 |
|
|
(DELAY
|
2461 |
|
|
(ABSOLUTE
|
2462 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2463 |
|
|
)
|
2464 |
|
|
)
|
2465 |
|
|
(TIMINGCHECK
|
2466 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2467 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2468 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2469 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2470 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2471 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2472 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2473 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2474 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2475 |
|
|
)
|
2476 |
|
|
)
|
2477 |
|
|
(CELL
|
2478 |
|
|
(CELLTYPE "FDRE")
|
2479 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_4_reg)
|
2480 |
|
|
(DELAY
|
2481 |
|
|
(ABSOLUTE
|
2482 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2483 |
|
|
)
|
2484 |
|
|
)
|
2485 |
|
|
(TIMINGCHECK
|
2486 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2487 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2488 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2489 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2490 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2491 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2492 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2493 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2494 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2495 |
|
|
)
|
2496 |
|
|
)
|
2497 |
|
|
(CELL
|
2498 |
|
|
(CELLTYPE "FDRE")
|
2499 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_5_reg)
|
2500 |
|
|
(DELAY
|
2501 |
|
|
(ABSOLUTE
|
2502 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2503 |
|
|
)
|
2504 |
|
|
)
|
2505 |
|
|
(TIMINGCHECK
|
2506 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2507 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2508 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2509 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2510 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2511 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2512 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2513 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2514 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2515 |
|
|
)
|
2516 |
|
|
)
|
2517 |
|
|
(CELL
|
2518 |
|
|
(CELLTYPE "FDRE")
|
2519 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_6_reg)
|
2520 |
|
|
(DELAY
|
2521 |
|
|
(ABSOLUTE
|
2522 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
2523 |
|
|
)
|
2524 |
|
|
)
|
2525 |
|
|
(TIMINGCHECK
|
2526 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2527 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2528 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2529 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2530 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2531 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2532 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
2533 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2534 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
2535 |
|
|
)
|
2536 |
|
|
)
|
2537 |
|
|
(CELL
|
2538 |
|
|
(CELLTYPE "FDRE")
|
2539 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_7_reg)
|
2540 |
|
|
(DELAY
|
2541 |
|
|
(ABSOLUTE
|
2542 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2543 |
|
|
)
|
2544 |
|
|
)
|
2545 |
|
|
(TIMINGCHECK
|
2546 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2547 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2548 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2549 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2550 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2551 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2552 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2553 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2554 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2555 |
|
|
)
|
2556 |
|
|
)
|
2557 |
|
|
(CELL
|
2558 |
|
|
(CELLTYPE "FDRE")
|
2559 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_8_reg)
|
2560 |
|
|
(DELAY
|
2561 |
|
|
(ABSOLUTE
|
2562 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2563 |
|
|
)
|
2564 |
|
|
)
|
2565 |
|
|
(TIMINGCHECK
|
2566 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2567 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2568 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2569 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2570 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2571 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2572 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2573 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2574 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2575 |
|
|
)
|
2576 |
|
|
)
|
2577 |
|
|
(CELL
|
2578 |
|
|
(CELLTYPE "FDRE")
|
2579 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_9_reg)
|
2580 |
|
|
(DELAY
|
2581 |
|
|
(ABSOLUTE
|
2582 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2583 |
|
|
)
|
2584 |
|
|
)
|
2585 |
|
|
(TIMINGCHECK
|
2586 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2587 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2588 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2589 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2590 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2591 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2592 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2593 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2594 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2595 |
|
|
)
|
2596 |
|
|
)
|
2597 |
|
|
(CELL
|
2598 |
|
|
(CELLTYPE "LUT6")
|
2599 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1)
|
2600 |
|
|
(DELAY
|
2601 |
|
|
(PATHPULSE (50.0))
|
2602 |
|
|
(ABSOLUTE
|
2603 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2604 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2605 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2606 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2607 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2608 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2609 |
|
|
)
|
2610 |
|
|
)
|
2611 |
|
|
)
|
2612 |
|
|
(CELL
|
2613 |
|
|
(CELLTYPE "LUT6")
|
2614 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2)
|
2615 |
|
|
(DELAY
|
2616 |
|
|
(PATHPULSE (50.0))
|
2617 |
|
|
(ABSOLUTE
|
2618 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2619 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2620 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2621 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2622 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2623 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2624 |
|
|
)
|
2625 |
|
|
)
|
2626 |
|
|
)
|
2627 |
|
|
(CELL
|
2628 |
|
|
(CELLTYPE "FDRE")
|
2629 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg)
|
2630 |
|
|
(DELAY
|
2631 |
|
|
(ABSOLUTE
|
2632 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2633 |
|
|
)
|
2634 |
|
|
)
|
2635 |
|
|
(TIMINGCHECK
|
2636 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2637 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2638 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2639 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2640 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2641 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2642 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2643 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2644 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2645 |
|
|
)
|
2646 |
|
|
)
|
2647 |
|
|
(CELL
|
2648 |
|
|
(CELLTYPE "FDRE")
|
2649 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg)
|
2650 |
|
|
(DELAY
|
2651 |
|
|
(ABSOLUTE
|
2652 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2653 |
|
|
)
|
2654 |
|
|
)
|
2655 |
|
|
(TIMINGCHECK
|
2656 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2657 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2658 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2659 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2660 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2661 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2662 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2663 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2664 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2665 |
|
|
)
|
2666 |
|
|
)
|
2667 |
|
|
(CELL
|
2668 |
|
|
(CELLTYPE "LUT3")
|
2669 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_i_1)
|
2670 |
|
|
(DELAY
|
2671 |
|
|
(PATHPULSE (50.0))
|
2672 |
|
|
(ABSOLUTE
|
2673 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2674 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2675 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2676 |
|
|
)
|
2677 |
|
|
)
|
2678 |
|
|
)
|
2679 |
|
|
(CELL
|
2680 |
|
|
(CELLTYPE "FDRE")
|
2681 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg)
|
2682 |
|
|
(DELAY
|
2683 |
|
|
(ABSOLUTE
|
2684 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2685 |
|
|
)
|
2686 |
|
|
)
|
2687 |
|
|
(TIMINGCHECK
|
2688 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2689 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2690 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2691 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2692 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2693 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2694 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2695 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2696 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2697 |
|
|
)
|
2698 |
|
|
)
|
2699 |
|
|
(CELL
|
2700 |
|
|
(CELLTYPE "SRL16E")
|
2701 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15)
|
2702 |
|
|
(DELAY
|
2703 |
|
|
(ABSOLUTE
|
2704 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
2705 |
|
|
(IOPATH A3 Q (39.0:47.0:47.0) (39.0:47.0:47.0))
|
2706 |
|
|
(IOPATH A2 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2707 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
2708 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2709 |
|
|
)
|
2710 |
|
|
)
|
2711 |
|
|
(TIMINGCHECK
|
2712 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2713 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
2714 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
2715 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
2716 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2717 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
2718 |
|
|
)
|
2719 |
|
|
)
|
2720 |
|
|
(CELL
|
2721 |
|
|
(CELLTYPE "FDRE")
|
2722 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[15\]\[0\])
|
2723 |
|
|
(DELAY
|
2724 |
|
|
(ABSOLUTE
|
2725 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
2726 |
|
|
)
|
2727 |
|
|
)
|
2728 |
|
|
(TIMINGCHECK
|
2729 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2730 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2731 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2732 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
2733 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2734 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2735 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
2736 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2737 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
2738 |
|
|
)
|
2739 |
|
|
)
|
2740 |
|
|
(CELL
|
2741 |
|
|
(CELLTYPE "LUT3")
|
2742 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/tx_Data_Enable_i_1)
|
2743 |
|
|
(DELAY
|
2744 |
|
|
(PATHPULSE (50.0))
|
2745 |
|
|
(ABSOLUTE
|
2746 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2747 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2748 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2749 |
|
|
)
|
2750 |
|
|
)
|
2751 |
|
|
)
|
2752 |
|
|
(CELL
|
2753 |
|
|
(CELLTYPE "LUT6")
|
2754 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0)
|
2755 |
|
|
(DELAY
|
2756 |
|
|
(PATHPULSE (50.0))
|
2757 |
|
|
(ABSOLUTE
|
2758 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2759 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2760 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2761 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2762 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2763 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2764 |
|
|
)
|
2765 |
|
|
)
|
2766 |
|
|
)
|
2767 |
|
|
(CELL
|
2768 |
|
|
(CELLTYPE "LUT2")
|
2769 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2__0)
|
2770 |
|
|
(DELAY
|
2771 |
|
|
(PATHPULSE (50.0))
|
2772 |
|
|
(ABSOLUTE
|
2773 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2774 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2775 |
|
|
)
|
2776 |
|
|
)
|
2777 |
|
|
)
|
2778 |
|
|
(CELL
|
2779 |
|
|
(CELLTYPE "LUT6")
|
2780 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0)
|
2781 |
|
|
(DELAY
|
2782 |
|
|
(PATHPULSE (50.0))
|
2783 |
|
|
(ABSOLUTE
|
2784 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2785 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2786 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2787 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2788 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2789 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2790 |
|
|
)
|
2791 |
|
|
)
|
2792 |
|
|
)
|
2793 |
|
|
(CELL
|
2794 |
|
|
(CELLTYPE "LUT5")
|
2795 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0)
|
2796 |
|
|
(DELAY
|
2797 |
|
|
(PATHPULSE (50.0))
|
2798 |
|
|
(ABSOLUTE
|
2799 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2800 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2801 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2802 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2803 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2804 |
|
|
)
|
2805 |
|
|
)
|
2806 |
|
|
)
|
2807 |
|
|
(CELL
|
2808 |
|
|
(CELLTYPE "LUT6")
|
2809 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0)
|
2810 |
|
|
(DELAY
|
2811 |
|
|
(PATHPULSE (50.0))
|
2812 |
|
|
(ABSOLUTE
|
2813 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2814 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2815 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2816 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2817 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2818 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2819 |
|
|
)
|
2820 |
|
|
)
|
2821 |
|
|
)
|
2822 |
|
|
(CELL
|
2823 |
|
|
(CELLTYPE "LUT6")
|
2824 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0)
|
2825 |
|
|
(DELAY
|
2826 |
|
|
(PATHPULSE (50.0))
|
2827 |
|
|
(ABSOLUTE
|
2828 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2829 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2830 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2831 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2832 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2833 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2834 |
|
|
)
|
2835 |
|
|
)
|
2836 |
|
|
)
|
2837 |
|
|
(CELL
|
2838 |
|
|
(CELLTYPE "LUT2")
|
2839 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_2__0)
|
2840 |
|
|
(DELAY
|
2841 |
|
|
(PATHPULSE (50.0))
|
2842 |
|
|
(ABSOLUTE
|
2843 |
|
|
(IOPATH I1 O (39.0:47.0:47.0) (39.0:47.0:47.0))
|
2844 |
|
|
(IOPATH I0 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2845 |
|
|
)
|
2846 |
|
|
)
|
2847 |
|
|
)
|
2848 |
|
|
(CELL
|
2849 |
|
|
(CELLTYPE "LUT2")
|
2850 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0)
|
2851 |
|
|
(DELAY
|
2852 |
|
|
(PATHPULSE (50.0))
|
2853 |
|
|
(ABSOLUTE
|
2854 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2855 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2856 |
|
|
)
|
2857 |
|
|
)
|
2858 |
|
|
)
|
2859 |
|
|
(CELL
|
2860 |
|
|
(CELLTYPE "LUT6")
|
2861 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0)
|
2862 |
|
|
(DELAY
|
2863 |
|
|
(PATHPULSE (50.0))
|
2864 |
|
|
(ABSOLUTE
|
2865 |
|
|
(IOPATH I5 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2866 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2867 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2868 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2869 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2870 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2871 |
|
|
)
|
2872 |
|
|
)
|
2873 |
|
|
)
|
2874 |
|
|
(CELL
|
2875 |
|
|
(CELLTYPE "LUT4")
|
2876 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0)
|
2877 |
|
|
(DELAY
|
2878 |
|
|
(PATHPULSE (50.0))
|
2879 |
|
|
(ABSOLUTE
|
2880 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2881 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2882 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2883 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
2884 |
|
|
)
|
2885 |
|
|
)
|
2886 |
|
|
)
|
2887 |
|
|
(CELL
|
2888 |
|
|
(CELLTYPE "LUT3")
|
2889 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4__0)
|
2890 |
|
|
(DELAY
|
2891 |
|
|
(PATHPULSE (50.0))
|
2892 |
|
|
(ABSOLUTE
|
2893 |
|
|
(IOPATH I2 O (38.0:46.0:46.0) (38.0:46.0:46.0))
|
2894 |
|
|
(IOPATH I1 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2895 |
|
|
(IOPATH I0 O (40.0:47.0:47.0) (40.0:47.0:47.0))
|
2896 |
|
|
)
|
2897 |
|
|
)
|
2898 |
|
|
)
|
2899 |
|
|
(CELL
|
2900 |
|
|
(CELLTYPE "FDSE")
|
2901 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\])
|
2902 |
|
|
(DELAY
|
2903 |
|
|
(ABSOLUTE
|
2904 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2905 |
|
|
)
|
2906 |
|
|
)
|
2907 |
|
|
(TIMINGCHECK
|
2908 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2909 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2910 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2911 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2912 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2913 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2914 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2915 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2916 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2917 |
|
|
)
|
2918 |
|
|
)
|
2919 |
|
|
(CELL
|
2920 |
|
|
(CELLTYPE "FDSE")
|
2921 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\])
|
2922 |
|
|
(DELAY
|
2923 |
|
|
(ABSOLUTE
|
2924 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2925 |
|
|
)
|
2926 |
|
|
)
|
2927 |
|
|
(TIMINGCHECK
|
2928 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2929 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2930 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2931 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2932 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2933 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2934 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2935 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2936 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2937 |
|
|
)
|
2938 |
|
|
)
|
2939 |
|
|
(CELL
|
2940 |
|
|
(CELLTYPE "FDSE")
|
2941 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\])
|
2942 |
|
|
(DELAY
|
2943 |
|
|
(ABSOLUTE
|
2944 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
2945 |
|
|
)
|
2946 |
|
|
)
|
2947 |
|
|
(TIMINGCHECK
|
2948 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2949 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
2950 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2951 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
2952 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2953 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
2954 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2955 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2956 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2957 |
|
|
)
|
2958 |
|
|
)
|
2959 |
|
|
(CELL
|
2960 |
|
|
(CELLTYPE "FDSE")
|
2961 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\])
|
2962 |
|
|
(DELAY
|
2963 |
|
|
(ABSOLUTE
|
2964 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2965 |
|
|
)
|
2966 |
|
|
)
|
2967 |
|
|
(TIMINGCHECK
|
2968 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2969 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2970 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2971 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2972 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2973 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2974 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2975 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2976 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2977 |
|
|
)
|
2978 |
|
|
)
|
2979 |
|
|
(CELL
|
2980 |
|
|
(CELLTYPE "FDSE")
|
2981 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\])
|
2982 |
|
|
(DELAY
|
2983 |
|
|
(ABSOLUTE
|
2984 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
2985 |
|
|
)
|
2986 |
|
|
)
|
2987 |
|
|
(TIMINGCHECK
|
2988 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2989 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
2990 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2991 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
2992 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2993 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
2994 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
2995 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2996 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
2997 |
|
|
)
|
2998 |
|
|
)
|
2999 |
|
|
(CELL
|
3000 |
|
|
(CELLTYPE "LUT4")
|
3001 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1)
|
3002 |
|
|
(DELAY
|
3003 |
|
|
(PATHPULSE (50.0))
|
3004 |
|
|
(ABSOLUTE
|
3005 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3006 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3007 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3008 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3009 |
|
|
)
|
3010 |
|
|
)
|
3011 |
|
|
)
|
3012 |
|
|
(CELL
|
3013 |
|
|
(CELLTYPE "SRL16E")
|
3014 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16)
|
3015 |
|
|
(DELAY
|
3016 |
|
|
(ABSOLUTE
|
3017 |
|
|
(IOPATH CLK Q (731.0:916.0:916.0) (731.0:916.0:916.0))
|
3018 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3019 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3020 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3021 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3022 |
|
|
)
|
3023 |
|
|
)
|
3024 |
|
|
(TIMINGCHECK
|
3025 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3026 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3027 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (79.0:98.0:98.0) (71.0:71.0:71.0))
|
3028 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (79.0:98.0:98.0) (71.0:71.0:71.0))
|
3029 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3030 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3031 |
|
|
)
|
3032 |
|
|
)
|
3033 |
|
|
(CELL
|
3034 |
|
|
(CELLTYPE "SRL16E")
|
3035 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16)
|
3036 |
|
|
(DELAY
|
3037 |
|
|
(ABSOLUTE
|
3038 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
3039 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3040 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3041 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3042 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3043 |
|
|
)
|
3044 |
|
|
)
|
3045 |
|
|
(TIMINGCHECK
|
3046 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3047 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3048 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (77.0:97.0:97.0) (81.0:81.0:81.0))
|
3049 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (77.0:97.0:97.0) (81.0:81.0:81.0))
|
3050 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3051 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3052 |
|
|
)
|
3053 |
|
|
)
|
3054 |
|
|
(CELL
|
3055 |
|
|
(CELLTYPE "SRL16E")
|
3056 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16)
|
3057 |
|
|
(DELAY
|
3058 |
|
|
(ABSOLUTE
|
3059 |
|
|
(IOPATH CLK Q (715.0:896.0:896.0) (715.0:896.0:896.0))
|
3060 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3061 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3062 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3063 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3064 |
|
|
)
|
3065 |
|
|
)
|
3066 |
|
|
(TIMINGCHECK
|
3067 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3068 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3069 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (91.0:114.0:114.0) (60.0:60.0:60.0))
|
3070 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (91.0:114.0:114.0) (60.0:60.0:60.0))
|
3071 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3072 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3073 |
|
|
)
|
3074 |
|
|
)
|
3075 |
|
|
(CELL
|
3076 |
|
|
(CELLTYPE "SRL16E")
|
3077 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16)
|
3078 |
|
|
(DELAY
|
3079 |
|
|
(ABSOLUTE
|
3080 |
|
|
(IOPATH CLK Q (719.0:901.0:901.0) (719.0:901.0:901.0))
|
3081 |
|
|
(IOPATH A3 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3082 |
|
|
(IOPATH A2 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3083 |
|
|
(IOPATH A1 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3084 |
|
|
(IOPATH A0 Q (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3085 |
|
|
)
|
3086 |
|
|
)
|
3087 |
|
|
(TIMINGCHECK
|
3088 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3089 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3090 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (81.0:101.0:101.0) (76.0:76.0:76.0))
|
3091 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (81.0:101.0:101.0) (76.0:76.0:76.0))
|
3092 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3093 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3094 |
|
|
)
|
3095 |
|
|
)
|
3096 |
|
|
(CELL
|
3097 |
|
|
(CELLTYPE "SRL16E")
|
3098 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16)
|
3099 |
|
|
(DELAY
|
3100 |
|
|
(ABSOLUTE
|
3101 |
|
|
(IOPATH CLK Q (721.0:903.0:903.0) (721.0:903.0:903.0))
|
3102 |
|
|
(IOPATH A3 Q (39.0:47.0:47.0) (39.0:47.0:47.0))
|
3103 |
|
|
(IOPATH A2 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3104 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3105 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
3106 |
|
|
)
|
3107 |
|
|
)
|
3108 |
|
|
(TIMINGCHECK
|
3109 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3110 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3111 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
3112 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (71.0:89.0:89.0) (87.0:87.0:87.0))
|
3113 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3114 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3115 |
|
|
)
|
3116 |
|
|
)
|
3117 |
|
|
(CELL
|
3118 |
|
|
(CELLTYPE "SRL16E")
|
3119 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16)
|
3120 |
|
|
(DELAY
|
3121 |
|
|
(ABSOLUTE
|
3122 |
|
|
(IOPATH CLK Q (725.0:909.0:909.0) (725.0:909.0:909.0))
|
3123 |
|
|
(IOPATH A3 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3124 |
|
|
(IOPATH A2 Q (45.0:53.0:53.0) (45.0:53.0:53.0))
|
3125 |
|
|
(IOPATH A1 Q (45.0:53.0:53.0) (45.0:53.0:53.0))
|
3126 |
|
|
(IOPATH A0 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3127 |
|
|
)
|
3128 |
|
|
)
|
3129 |
|
|
(TIMINGCHECK
|
3130 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3131 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3132 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (74.0:93.0:93.0) (82.0:82.0:82.0))
|
3133 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (74.0:93.0:93.0) (82.0:82.0:82.0))
|
3134 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3135 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3136 |
|
|
)
|
3137 |
|
|
)
|
3138 |
|
|
(CELL
|
3139 |
|
|
(CELLTYPE "SRL16E")
|
3140 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16)
|
3141 |
|
|
(DELAY
|
3142 |
|
|
(ABSOLUTE
|
3143 |
|
|
(IOPATH CLK Q (716.0:897.0:897.0) (716.0:897.0:897.0))
|
3144 |
|
|
(IOPATH A3 Q (38.0:45.0:45.0) (38.0:45.0:45.0))
|
3145 |
|
|
(IOPATH A2 Q (42.0:49.0:49.0) (42.0:49.0:49.0))
|
3146 |
|
|
(IOPATH A1 Q (42.0:50.0:50.0) (42.0:50.0:50.0))
|
3147 |
|
|
(IOPATH A0 Q (39.0:46.0:46.0) (39.0:46.0:46.0))
|
3148 |
|
|
)
|
3149 |
|
|
)
|
3150 |
|
|
(TIMINGCHECK
|
3151 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3152 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3153 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (82.0:103.0:103.0) (70.0:70.0:70.0))
|
3154 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (82.0:103.0:103.0) (70.0:70.0:70.0))
|
3155 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3156 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3157 |
|
|
)
|
3158 |
|
|
)
|
3159 |
|
|
(CELL
|
3160 |
|
|
(CELLTYPE "SRL16E")
|
3161 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16)
|
3162 |
|
|
(DELAY
|
3163 |
|
|
(ABSOLUTE
|
3164 |
|
|
(IOPATH CLK Q (727.0:911.0:911.0) (727.0:911.0:911.0))
|
3165 |
|
|
(IOPATH A3 Q (38.0:46.0:46.0) (38.0:46.0:46.0))
|
3166 |
|
|
(IOPATH A2 Q (42.0:50.0:50.0) (42.0:50.0:50.0))
|
3167 |
|
|
(IOPATH A1 Q (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3168 |
|
|
(IOPATH A0 Q (40.0:47.0:47.0) (40.0:47.0:47.0))
|
3169 |
|
|
)
|
3170 |
|
|
)
|
3171 |
|
|
(TIMINGCHECK
|
3172 |
|
|
(SETUPHOLD (posedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3173 |
|
|
(SETUPHOLD (negedge CE) (posedge CLK) (270.0:339.0:339.0) (-5.0:-5.0:-5.0))
|
3174 |
|
|
(SETUPHOLD (posedge D) (posedge CLK) (-3.0:-2.0:-2.0) (176.0:176.0:176.0))
|
3175 |
|
|
(SETUPHOLD (negedge D) (posedge CLK) (-3.0:-2.0:-2.0) (176.0:176.0:176.0))
|
3176 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3177 |
|
|
(WIDTH (posedge CLK) (559.0:642.0:642.0))
|
3178 |
|
|
)
|
3179 |
|
|
)
|
3180 |
|
|
(CELL
|
3181 |
|
|
(CELLTYPE "LUT4")
|
3182 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1)
|
3183 |
|
|
(DELAY
|
3184 |
|
|
(PATHPULSE (50.0))
|
3185 |
|
|
(ABSOLUTE
|
3186 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3187 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3188 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3189 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3190 |
|
|
)
|
3191 |
|
|
)
|
3192 |
|
|
)
|
3193 |
|
|
(CELL
|
3194 |
|
|
(CELLTYPE "LUT5")
|
3195 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2)
|
3196 |
|
|
(DELAY
|
3197 |
|
|
(PATHPULSE (50.0))
|
3198 |
|
|
(ABSOLUTE
|
3199 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3200 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3201 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3202 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3203 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3204 |
|
|
)
|
3205 |
|
|
)
|
3206 |
|
|
)
|
3207 |
|
|
(CELL
|
3208 |
|
|
(CELLTYPE "LUT5")
|
3209 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3)
|
3210 |
|
|
(DELAY
|
3211 |
|
|
(PATHPULSE (50.0))
|
3212 |
|
|
(ABSOLUTE
|
3213 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3214 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3215 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3216 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3217 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3218 |
|
|
)
|
3219 |
|
|
)
|
3220 |
|
|
)
|
3221 |
|
|
(CELL
|
3222 |
|
|
(CELLTYPE "LUT5")
|
3223 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4)
|
3224 |
|
|
(DELAY
|
3225 |
|
|
(PATHPULSE (50.0))
|
3226 |
|
|
(ABSOLUTE
|
3227 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3228 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3229 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3230 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3231 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3232 |
|
|
)
|
3233 |
|
|
)
|
3234 |
|
|
)
|
3235 |
|
|
(CELL
|
3236 |
|
|
(CELLTYPE "LUT5")
|
3237 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5)
|
3238 |
|
|
(DELAY
|
3239 |
|
|
(PATHPULSE (50.0))
|
3240 |
|
|
(ABSOLUTE
|
3241 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3242 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3243 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3244 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3245 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3246 |
|
|
)
|
3247 |
|
|
)
|
3248 |
|
|
)
|
3249 |
|
|
(CELL
|
3250 |
|
|
(CELLTYPE "FDRE")
|
3251 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg)
|
3252 |
|
|
(DELAY
|
3253 |
|
|
(ABSOLUTE
|
3254 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
3255 |
|
|
)
|
3256 |
|
|
)
|
3257 |
|
|
(TIMINGCHECK
|
3258 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3259 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3260 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3261 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3262 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3263 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3264 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3265 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3266 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3267 |
|
|
)
|
3268 |
|
|
)
|
3269 |
|
|
(CELL
|
3270 |
|
|
(CELLTYPE "LUT3")
|
3271 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_i_1)
|
3272 |
|
|
(DELAY
|
3273 |
|
|
(PATHPULSE (50.0))
|
3274 |
|
|
(ABSOLUTE
|
3275 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3276 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3277 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3278 |
|
|
)
|
3279 |
|
|
)
|
3280 |
|
|
)
|
3281 |
|
|
(CELL
|
3282 |
|
|
(CELLTYPE "FDSE")
|
3283 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg)
|
3284 |
|
|
(DELAY
|
3285 |
|
|
(ABSOLUTE
|
3286 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3287 |
|
|
)
|
3288 |
|
|
)
|
3289 |
|
|
(TIMINGCHECK
|
3290 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3291 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3292 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3293 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3294 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3295 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3296 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3297 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3298 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3299 |
|
|
)
|
3300 |
|
|
)
|
3301 |
|
|
(CELL
|
3302 |
|
|
(CELLTYPE "LUT4")
|
3303 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1)
|
3304 |
|
|
(DELAY
|
3305 |
|
|
(PATHPULSE (50.0))
|
3306 |
|
|
(ABSOLUTE
|
3307 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3308 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3309 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3310 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3311 |
|
|
)
|
3312 |
|
|
)
|
3313 |
|
|
)
|
3314 |
|
|
(CELL
|
3315 |
|
|
(CELLTYPE "FDRE")
|
3316 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg)
|
3317 |
|
|
(DELAY
|
3318 |
|
|
(ABSOLUTE
|
3319 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3320 |
|
|
)
|
3321 |
|
|
)
|
3322 |
|
|
(TIMINGCHECK
|
3323 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3324 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3325 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3326 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3327 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3328 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3329 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3330 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3331 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3332 |
|
|
)
|
3333 |
|
|
)
|
3334 |
|
|
(CELL
|
3335 |
|
|
(CELLTYPE "LUT5")
|
3336 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1)
|
3337 |
|
|
(DELAY
|
3338 |
|
|
(PATHPULSE (50.0))
|
3339 |
|
|
(ABSOLUTE
|
3340 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3341 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3342 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3343 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3344 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3345 |
|
|
)
|
3346 |
|
|
)
|
3347 |
|
|
)
|
3348 |
|
|
(CELL
|
3349 |
|
|
(CELLTYPE "LUT5")
|
3350 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1)
|
3351 |
|
|
(DELAY
|
3352 |
|
|
(PATHPULSE (50.0))
|
3353 |
|
|
(ABSOLUTE
|
3354 |
|
|
(IOPATH I4 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3355 |
|
|
(IOPATH I3 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
3356 |
|
|
(IOPATH I2 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3357 |
|
|
(IOPATH I1 O (45.0:53.0:53.0) (45.0:53.0:53.0))
|
3358 |
|
|
(IOPATH I0 O (43.0:51.0:51.0) (43.0:51.0:51.0))
|
3359 |
|
|
)
|
3360 |
|
|
)
|
3361 |
|
|
)
|
3362 |
|
|
(CELL
|
3363 |
|
|
(CELLTYPE "LUT5")
|
3364 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1)
|
3365 |
|
|
(DELAY
|
3366 |
|
|
(PATHPULSE (50.0))
|
3367 |
|
|
(ABSOLUTE
|
3368 |
|
|
(IOPATH I4 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3369 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3370 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3371 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3372 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3373 |
|
|
)
|
3374 |
|
|
)
|
3375 |
|
|
)
|
3376 |
|
|
(CELL
|
3377 |
|
|
(CELLTYPE "FDSE")
|
3378 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\])
|
3379 |
|
|
(DELAY
|
3380 |
|
|
(ABSOLUTE
|
3381 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3382 |
|
|
)
|
3383 |
|
|
)
|
3384 |
|
|
(TIMINGCHECK
|
3385 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3386 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3387 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3388 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3389 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3390 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3391 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3392 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3393 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3394 |
|
|
)
|
3395 |
|
|
)
|
3396 |
|
|
(CELL
|
3397 |
|
|
(CELLTYPE "FDSE")
|
3398 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\])
|
3399 |
|
|
(DELAY
|
3400 |
|
|
(ABSOLUTE
|
3401 |
|
|
(IOPATH C Q (122.0:152.0:152.0) (122.0:152.0:152.0))
|
3402 |
|
|
)
|
3403 |
|
|
)
|
3404 |
|
|
(TIMINGCHECK
|
3405 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3406 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3407 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
3408 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-60.0:-50.0:-50.0) (133.0:133.0:133.0))
|
3409 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3410 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3411 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
3412 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3413 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
3414 |
|
|
)
|
3415 |
|
|
)
|
3416 |
|
|
(CELL
|
3417 |
|
|
(CELLTYPE "FDSE")
|
3418 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\])
|
3419 |
|
|
(DELAY
|
3420 |
|
|
(ABSOLUTE
|
3421 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3422 |
|
|
)
|
3423 |
|
|
)
|
3424 |
|
|
(TIMINGCHECK
|
3425 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3426 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3427 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3428 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3429 |
|
|
(SETUPHOLD (posedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3430 |
|
|
(SETUPHOLD (negedge S) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3431 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3432 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3433 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3434 |
|
|
)
|
3435 |
|
|
)
|
3436 |
|
|
(CELL
|
3437 |
|
|
(CELLTYPE "FDRE")
|
3438 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/serial_Data_reg)
|
3439 |
|
|
(DELAY
|
3440 |
|
|
(ABSOLUTE
|
3441 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3442 |
|
|
)
|
3443 |
|
|
)
|
3444 |
|
|
(TIMINGCHECK
|
3445 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3446 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3447 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3448 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3449 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3450 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3451 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3452 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3453 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3454 |
|
|
)
|
3455 |
|
|
)
|
3456 |
|
|
(CELL
|
3457 |
|
|
(CELLTYPE "LUT4")
|
3458 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1)
|
3459 |
|
|
(DELAY
|
3460 |
|
|
(PATHPULSE (50.0))
|
3461 |
|
|
(ABSOLUTE
|
3462 |
|
|
(IOPATH I3 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3463 |
|
|
(IOPATH I2 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3464 |
|
|
(IOPATH I1 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3465 |
|
|
(IOPATH I0 O (36.0:43.0:43.0) (36.0:43.0:43.0))
|
3466 |
|
|
)
|
3467 |
|
|
)
|
3468 |
|
|
)
|
3469 |
|
|
(CELL
|
3470 |
|
|
(CELLTYPE "FDRE")
|
3471 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg)
|
3472 |
|
|
(DELAY
|
3473 |
|
|
(ABSOLUTE
|
3474 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3475 |
|
|
)
|
3476 |
|
|
)
|
3477 |
|
|
(TIMINGCHECK
|
3478 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3479 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3480 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3481 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3482 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3483 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3484 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3485 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3486 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3487 |
|
|
)
|
3488 |
|
|
)
|
3489 |
|
|
(CELL
|
3490 |
|
|
(CELLTYPE "FDRE")
|
3491 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg)
|
3492 |
|
|
(DELAY
|
3493 |
|
|
(ABSOLUTE
|
3494 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3495 |
|
|
)
|
3496 |
|
|
)
|
3497 |
|
|
(TIMINGCHECK
|
3498 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3499 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3500 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3501 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3502 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3503 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3504 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3505 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3506 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3507 |
|
|
)
|
3508 |
|
|
)
|
3509 |
|
|
(CELL
|
3510 |
|
|
(CELLTYPE "FDRE")
|
3511 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Start_reg)
|
3512 |
|
|
(DELAY
|
3513 |
|
|
(ABSOLUTE
|
3514 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3515 |
|
|
)
|
3516 |
|
|
)
|
3517 |
|
|
(TIMINGCHECK
|
3518 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3519 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3520 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3521 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3522 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3523 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3524 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3525 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3526 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3527 |
|
|
)
|
3528 |
|
|
)
|
3529 |
|
|
(CELL
|
3530 |
|
|
(CELLTYPE "FDRE")
|
3531 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/clr_Status_reg)
|
3532 |
|
|
(DELAY
|
3533 |
|
|
(ABSOLUTE
|
3534 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3535 |
|
|
)
|
3536 |
|
|
)
|
3537 |
|
|
(TIMINGCHECK
|
3538 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3539 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3540 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3541 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3542 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3543 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3544 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3545 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3546 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3547 |
|
|
)
|
3548 |
|
|
)
|
3549 |
|
|
(CELL
|
3550 |
|
|
(CELLTYPE "FDRE")
|
3551 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/enable_interrupts_reg)
|
3552 |
|
|
(DELAY
|
3553 |
|
|
(ABSOLUTE
|
3554 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
3555 |
|
|
)
|
3556 |
|
|
)
|
3557 |
|
|
(TIMINGCHECK
|
3558 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3559 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3560 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3561 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3562 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3563 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3564 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3565 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3566 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3567 |
|
|
)
|
3568 |
|
|
)
|
3569 |
|
|
(CELL
|
3570 |
|
|
(CELLTYPE "FDSE")
|
3571 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/reset_RX_FIFO_reg)
|
3572 |
|
|
(DELAY
|
3573 |
|
|
(ABSOLUTE
|
3574 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
3575 |
|
|
)
|
3576 |
|
|
)
|
3577 |
|
|
(TIMINGCHECK
|
3578 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3579 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3580 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3581 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3582 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3583 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3584 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3585 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3586 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3587 |
|
|
)
|
3588 |
|
|
)
|
3589 |
|
|
(CELL
|
3590 |
|
|
(CELLTYPE "FDSE")
|
3591 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/reset_TX_FIFO_reg)
|
3592 |
|
|
(DELAY
|
3593 |
|
|
(ABSOLUTE
|
3594 |
|
|
(IOPATH C Q (116.0:146.0:146.0) (116.0:146.0:146.0))
|
3595 |
|
|
)
|
3596 |
|
|
)
|
3597 |
|
|
(TIMINGCHECK
|
3598 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3599 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3600 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
3601 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-52.0:-42.0:-42.0) (126.0:126.0:126.0))
|
3602 |
|
|
(SETUPHOLD (posedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3603 |
|
|
(SETUPHOLD (negedge S) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3604 |
|
|
(PERIOD (posedge C) (653.0:750.0:750.0))
|
3605 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3606 |
|
|
(WIDTH (posedge C) (348.0:400.0:400.0))
|
3607 |
|
|
)
|
3608 |
|
|
)
|
3609 |
|
|
(CELL
|
3610 |
|
|
(CELLTYPE "FDRE")
|
3611 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg)
|
3612 |
|
|
(DELAY
|
3613 |
|
|
(ABSOLUTE
|
3614 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3615 |
|
|
)
|
3616 |
|
|
)
|
3617 |
|
|
(TIMINGCHECK
|
3618 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3619 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3620 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3621 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3622 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3623 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3624 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3625 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3626 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3627 |
|
|
)
|
3628 |
|
|
)
|
3629 |
|
|
(CELL
|
3630 |
|
|
(CELLTYPE "FDRE")
|
3631 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/status_reg_reg\[1\])
|
3632 |
|
|
(DELAY
|
3633 |
|
|
(ABSOLUTE
|
3634 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
3635 |
|
|
)
|
3636 |
|
|
)
|
3637 |
|
|
(TIMINGCHECK
|
3638 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3639 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3640 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3641 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3642 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3643 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3644 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3645 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3646 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3647 |
|
|
)
|
3648 |
|
|
)
|
3649 |
|
|
(CELL
|
3650 |
|
|
(CELLTYPE "FDRE")
|
3651 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/status_reg_reg\[2\])
|
3652 |
|
|
(DELAY
|
3653 |
|
|
(ABSOLUTE
|
3654 |
|
|
(IOPATH C Q (139.0:175.0:175.0) (139.0:175.0:175.0))
|
3655 |
|
|
)
|
3656 |
|
|
)
|
3657 |
|
|
(TIMINGCHECK
|
3658 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3659 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (34.0:34.0:34.0))
|
3660 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3661 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-53.0:-47.0:-47.0) (143.0:143.0:143.0))
|
3662 |
|
|
(SETUPHOLD (posedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3663 |
|
|
(SETUPHOLD (negedge R) (posedge C) (236.0:295.0:295.0) (17.0:17.0:17.0))
|
3664 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3665 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3666 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3667 |
|
|
)
|
3668 |
|
|
)
|
3669 |
|
|
(CELL
|
3670 |
|
|
(CELLTYPE "FDRE")
|
3671 |
|
|
(INSTANCE U0/UARTLITE_CORE_I/tx_Buffer_Empty_Pre_reg)
|
3672 |
|
|
(DELAY
|
3673 |
|
|
(ABSOLUTE
|
3674 |
|
|
(IOPATH C Q (132.0:165.0:165.0) (132.0:165.0:165.0))
|
3675 |
|
|
)
|
3676 |
|
|
)
|
3677 |
|
|
(TIMINGCHECK
|
3678 |
|
|
(SETUPHOLD (posedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3679 |
|
|
(SETUPHOLD (negedge CE) (posedge C) (118.0:148.0:148.0) (49.0:49.0:49.0))
|
3680 |
|
|
(SETUPHOLD (posedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3681 |
|
|
(SETUPHOLD (negedge D) (posedge C) (-45.0:-40.0:-40.0) (136.0:136.0:136.0))
|
3682 |
|
|
(SETUPHOLD (posedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3683 |
|
|
(SETUPHOLD (negedge R) (posedge C) (239.0:299.0:299.0) (9.0:9.0:9.0))
|
3684 |
|
|
(PERIOD (posedge C) (610.0:700.0:700.0))
|
3685 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3686 |
|
|
(WIDTH (posedge C) (305.0:350.0:350.0))
|
3687 |
|
|
)
|
3688 |
|
|
)
|
3689 |
|
|
(CELL
|
3690 |
|
|
(CELLTYPE "axi_uartlite_module")
|
3691 |
|
|
(INSTANCE )
|
3692 |
|
|
(DELAY
|
3693 |
|
|
(ABSOLUTE
|
3694 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3695 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/I0 (588.0:685.0:685.0) (588.0:685.0:685.0))
|
3696 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I1 (589.0:686.0:686.0) (589.0:686.0:686.0))
|
3697 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I3 (237.3:276.3:276.3) (237.3:276.3:276.3))
|
3698 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2/I0 (594.2:691.2:691.2) (594.2:691.2:691.2))
|
3699 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_RX_FIFO_i_1/I0 (244.1:285.1:285.1) (244.1:285.1:285.1))
|
3700 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_TX_FIFO_i_1/I0 (247.2:285.2:285.2) (247.2:285.2:285.2))
|
3701 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_3/I1 (711.3:833.3:833.3) (711.3:833.3:833.3))
|
3702 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/I1 (400.4:470.4:470.4) (400.4:470.4:470.4))
|
3703 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/I1 (317.2:368.2:368.2) (317.2:368.2:368.2))
|
3704 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/clr_Status_i_1/I1 (779.0:913.0:913.0) (779.0:913.0:913.0))
|
3705 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1/I2 (244.1:285.1:285.1) (244.1:285.1:285.1))
|
3706 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/enable_interrupts_i_1/I2 (247.2:285.2:285.2) (247.2:285.2:285.2))
|
3707 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/rx_Data_Present_Pre_i_1/I2 (420.2:490.2:490.2) (420.2:490.2:490.2))
|
3708 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/I2 (392.2:462.2:462.2) (392.2:462.2:462.2))
|
3709 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/I2 (594.2:691.2:691.2) (594.2:691.2:691.2))
|
3710 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/I2 (711.3:833.3:833.3) (711.3:833.3:833.3))
|
3711 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/I2 (779.0:913.0:913.0) (779.0:913.0:913.0))
|
3712 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/I2 (675.9:789.9:789.9) (675.9:789.9:789.9))
|
3713 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/I2 (472.2:548.2:548.2) (472.2:548.2:548.2))
|
3714 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/I2 (779.0:913.0:913.0) (779.0:913.0:913.0))
|
3715 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/I2 (674.9:787.9:787.9) (674.9:787.9:787.9))
|
3716 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2/I2 (594.2:691.2:691.2) (594.2:691.2:691.2))
|
3717 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/I2 (392.2:462.2:462.2) (392.2:462.2:462.2))
|
3718 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/I3 (317.2:368.2:368.2) (317.2:368.2:368.2))
|
3719 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/tx_Buffer_Empty_Pre_i_1/I3 (400.4:470.4:470.4) (400.4:470.4:470.4))
|
3720 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/I1 (402.2:471.2:471.2) (402.2:471.2:471.2))
|
3721 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I2 (473.2:555.2:555.2) (473.2:555.2:555.2))
|
3722 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_3/I0 (669.3:787.3:787.3) (669.3:787.3:787.3))
|
3723 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/I0 (210.7:248.7:248.7) (210.7:248.7:248.7))
|
3724 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2/I1 (604.3:710.3:710.3) (604.3:710.3:710.3))
|
3725 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2/I1 (423.0:497.0:497.0) (423.0:497.0:497.0))
|
3726 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/I2 (281.7:333.7:333.7) (281.7:333.7:333.7))
|
3727 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/I2 (475.6:561.6:561.6) (475.6:561.6:561.6))
|
3728 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/rx_Data_Present_Pre_i_1/I3 (241.5:282.5:282.5) (241.5:282.5:282.5))
|
3729 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/I3 (604.3:710.3:710.3) (604.3:710.3:710.3))
|
3730 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/I3 (669.3:787.3:787.3) (669.3:787.3:787.3))
|
3731 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/I3 (478.3:560.3:560.3) (478.3:560.3:560.3))
|
3732 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/I3 (367.3:429.3:429.3) (367.3:429.3:429.3))
|
3733 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/I3 (495.3:581.3:581.3) (495.3:581.3:581.3))
|
3734 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/I3 (478.3:560.3:560.3) (478.3:560.3:560.3))
|
3735 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/I3 (566.4:665.4:665.4) (566.4:665.4:665.4))
|
3736 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/I3 (210.7:248.7:248.7) (210.7:248.7:248.7))
|
3737 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3738 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I4 (171.1:201.1:201.1) (171.1:201.1:201.1))
|
3739 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/I0 (464.8:547.8:547.8) (464.8:547.8:547.8))
|
3740 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/I0 (458.2:542.2:542.2) (458.2:542.2:542.2))
|
3741 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/I0 (284.2:336.2:336.2) (284.2:336.2:336.2))
|
3742 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/I0 (465.8:548.8:548.8) (465.8:548.8:548.8))
|
3743 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/I2 (284.2:336.2:336.2) (284.2:336.2:336.2))
|
3744 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/tx_Buffer_Empty_Pre_i_1/I2 (458.2:542.2:542.2) (458.2:542.2:542.2))
|
3745 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/I3 (465.8:548.8:548.8) (465.8:548.8:548.8))
|
3746 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/clr_Status_i_1/I0 (329.7:385.7:385.7) (329.7:385.7:385.7))
|
3747 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2/I0 (750.9:887.9:887.9) (750.9:887.9:887.9))
|
3748 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/I1 (279.7:330.7:330.7) (279.7:330.7:330.7))
|
3749 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/I3 (311.6:366.6:366.6) (311.6:366.6:366.6))
|
3750 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/I4 (666.8:785.8:785.8) (666.8:785.8:785.8))
|
3751 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/I4 (494.5:580.5:580.5) (494.5:580.5:580.5))
|
3752 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/I4 (329.7:385.7:385.7) (329.7:385.7:385.7))
|
3753 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/I4 (508.7:597.7:597.7) (508.7:597.7:597.7))
|
3754 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/I4 (582.5:684.5:684.5) (582.5:684.5:684.5))
|
3755 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/I4 (330.7:386.7:386.7) (330.7:386.7:386.7))
|
3756 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/I4 (287.7:335.7:335.7) (287.7:335.7:335.7))
|
3757 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/I4 (279.7:330.7:330.7) (279.7:330.7:330.7))
|
3758 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/R (235.1:286.1:286.1) (235.1:286.1:286.1))
|
3759 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/R (235.1:286.1:286.1) (235.1:286.1:286.1))
|
3760 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/R (235.1:286.1:286.1) (235.1:286.1:286.1))
|
3761 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/R (235.1:286.1:286.1) (235.1:286.1:286.1))
|
3762 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/D (24.0:30.0:30.0) (24.0:30.0:30.0))
|
3763 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_1/I1 (202.3:242.3:242.3) (202.3:242.3:242.3))
|
3764 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/enable_interrupts_i_1/I1 (382.6:454.6:454.6) (382.6:454.6:454.6))
|
3765 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_RX_FIFO_i_1/I1 (446.4:530.4:530.4) (446.4:530.4:530.4))
|
3766 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_TX_FIFO_i_1/I1 (382.6:454.6:454.6) (382.6:454.6:454.6))
|
3767 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/I1 (447.4:531.4:531.4) (447.4:531.4:531.4))
|
3768 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/I4 (447.4:531.4:531.4) (447.4:531.4:531.4))
|
3769 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/I1 (515.4:619.4:619.4) (515.4:619.4:619.4))
|
3770 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I1 (514.4:617.4:617.4) (514.4:617.4:617.4))
|
3771 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_3/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I0 (280.6:332.6:332.6) (280.6:332.6:332.6))
|
3772 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_3/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I3 (163.6:197.6:197.6) (163.6:197.6:197.6))
|
3773 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I0 (459.5:549.5:549.5) (459.5:549.5:549.5))
|
3774 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I2 (355.5:426.5:426.5) (355.5:426.5:426.5))
|
3775 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/I4 (458.5:548.5:548.5) (458.5:548.5:548.5))
|
3776 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I4 (393.5:471.5:471.5) (393.5:471.5:471.5))
|
3777 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I5 (484.6:581.6:581.6) (484.6:581.6:581.6))
|
3778 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3779 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3780 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3781 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3782 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3783 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3784 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3785 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/CE (239.4:286.4:286.4) (239.4:286.4:286.4))
|
3786 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[0\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3787 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[2\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3788 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/clr_Status_i_1/O U0/UARTLITE_CORE_I/clr_Status_reg/D (348.3:429.3:429.3) (348.3:429.3:429.3))
|
3789 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/enable_interrupts_i_1/O U0/UARTLITE_CORE_I/enable_interrupts_reg/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3790 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_RX_FIFO_i_1/O U0/UARTLITE_CORE_I/reset_RX_FIFO_reg/D (470.1:570.1:570.1) (470.1:570.1:570.1))
|
3791 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/reset_TX_FIFO_i_1/O U0/UARTLITE_CORE_I/reset_TX_FIFO_reg/D (24.0:30.0:30.0) (24.0:30.0:30.0))
|
3792 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/rx_Data_Present_Pre_i_1/O U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
3793 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O m_axi\\\.araddr\[3\]_i_2/I0 (476.4:560.4:560.4) (476.4:560.4:560.4))
|
3794 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O m_axi\\\.arvalid_i_1/I0 (650.9:765.9:765.9) (650.9:765.9:765.9))
|
3795 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O axi_state\[2\]_C_i_1/I1 (645.2:759.2:759.2) (645.2:759.2:759.2))
|
3796 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O axi_state\[2\]_P_i_1/I1 (729.1:858.1:858.1) (729.1:858.1:858.1))
|
3797 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O axi_state\[2\]_P_i_2/I1 (738.7:869.7:869.7) (738.7:869.7:869.7))
|
3798 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O axi_state\[0\]_P_i_5/I4 (629.1:741.1:741.1) (629.1:741.1:741.1))
|
3799 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1/I0 (366.7:430.7:430.7) (366.7:430.7:430.7))
|
3800 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1/I2 (367.7:432.7:432.7) (367.7:432.7:432.7))
|
3801 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3802 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3803 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/D (408.1:492.1:492.1) (408.1:492.1:492.1))
|
3804 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/D (445.8:544.8:544.8) (445.8:544.8:544.8))
|
3805 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3806 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3807 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3808 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3809 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3810 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
3811 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/D (403.3:489.3:489.3) (403.3:489.3:489.3))
|
3812 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1/I0 (482.6:569.6:569.6) (482.6:569.6:569.6))
|
3813 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3814 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O m_axi\\\.wdata\[7\]_i_1/I3 (588.2:690.2:690.2) (588.2:690.2:690.2))
|
3815 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O axi_state\[1\]_P_i_5/I2 (502.2:586.2:586.2) (502.2:586.2:586.2))
|
3816 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O axi_state\[1\]_P_i_1/I5 (554.8:647.8:647.8) (554.8:647.8:647.8))
|
3817 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1/I0 (476.1:557.1:557.1) (476.1:557.1:557.1))
|
3818 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1/I2 (333.3:385.3:385.3) (333.3:385.3:385.3))
|
3819 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3820 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3821 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/tx_Buffer_Empty_Pre_i_1/O U0/UARTLITE_CORE_I/tx_Buffer_Empty_Pre_reg/D (371.6:452.6:452.6) (371.6:452.6:452.6))
|
3822 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[2\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3823 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3824 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[2\]_i_1/I1 (373.4:443.4:443.4) (373.4:443.4:443.4))
|
3825 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_1/I1 (378.6:448.6:448.6) (378.6:448.6:448.6))
|
3826 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[2\]_i_1/I4 (309.5:363.5:363.5) (309.5:363.5:363.5))
|
3827 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i\[1\]_i_1/I0 (444.4:513.4:513.4) (444.4:513.4:513.4))
|
3828 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_2/I1 (444.4:513.4:513.4) (444.4:513.4:513.4))
|
3829 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[0\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/I0 (443.4:512.4:512.4) (443.4:512.4:512.4))
|
3830 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[2\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/I1 (443.4:512.4:512.4) (443.4:512.4:512.4))
|
3831 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_1/I4 (235.3:276.3:276.3) (235.3:276.3:276.3))
|
3832 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i\[3\]_i_2/I0 (275.4:314.4:314.4) (275.4:314.4:314.4))
|
3833 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i\[1\]_i_1/I1 (275.4:314.4:314.4) (275.4:314.4:314.4))
|
3834 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[0\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/I1 (345.4:397.4:397.4) (345.4:397.4:397.4))
|
3835 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN\[0\]\.PER_CE_GEN\[2\]\.MULTIPLE_CES_THIS_CS_GEN\.CE_I/CS/I0 (449.4:520.4:520.4) (449.4:520.4:520.4))
|
3836 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3837 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_i_1/I4 (235.3:276.3:276.3) (235.3:276.3:276.3))
|
3838 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1/I0 (410.0:479.0:479.0) (410.0:479.0:479.0))
|
3839 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[2\]/R (524.7:619.7:619.7) (524.7:619.7:619.7))
|
3840 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg\[3\]/R (524.7:619.7:619.7) (524.7:619.7:619.7))
|
3841 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_reg/R (450.7:530.7:530.7) (450.7:530.7:530.7))
|
3842 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/R (524.7:619.7:619.7) (524.7:619.7:619.7))
|
3843 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/R (654.9:774.9:774.9) (654.9:774.9:774.9))
|
3844 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/R (747.2:872.2:872.2) (747.2:872.2:872.2))
|
3845 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/R (747.2:872.2:872.2) (747.2:872.2:872.2))
|
3846 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/R (910.3:1068.3:1068.3) (910.3:1068.3:1068.3))
|
3847 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/R (910.3:1068.3:1068.3) (910.3:1068.3:1068.3))
|
3848 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/R (746.2:870.2:870.2) (746.2:870.2:870.2))
|
3849 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/R (910.3:1068.3:1068.3) (910.3:1068.3:1068.3))
|
3850 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/R (910.3:1068.3:1068.3) (910.3:1068.3:1068.3))
|
3851 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/R (747.2:872.2:872.2) (747.2:872.2:872.2))
|
3852 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/R (746.2:870.2:870.2) (746.2:870.2:870.2))
|
3853 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/R (602.3:713.3:713.3) (602.3:713.3:713.3))
|
3854 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/R (524.7:619.7:619.7) (524.7:619.7:619.7))
|
3855 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/R (448.6:528.6:528.6) (448.6:528.6:528.6))
|
3856 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/R (602.3:713.3:713.3) (602.3:713.3:713.3))
|
3857 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/Q transmit_in_progress_reg_i_2/I0 (516.0:601.0:601.0) (516.0:601.0:601.0))
|
3858 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/Q cipher_data_reg\[127\]_i_3/I1 (516.0:601.0:601.0) (516.0:601.0:601.0))
|
3859 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/Q axi_state\[0\]_P_i_7/I3 (290.7:343.7:343.7) (290.7:343.7:343.7))
|
3860 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1/I3 (315.7:369.7:369.7) (315.7:369.7:369.7))
|
3861 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q cipher_data_reg\[127\]_i_3/I0 (598.0:699.0:699.0) (598.0:699.0:699.0))
|
3862 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q transmit_in_progress_reg_i_2/I1 (598.0:699.0:699.0) (598.0:699.0:699.0))
|
3863 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q axi_state\[0\]_P_i_7/I4 (244.9:286.9:286.9) (244.9:286.9:286.9))
|
3864 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[0\]_i_2/I4 (370.4:437.4:437.4) (370.4:437.4:437.4))
|
3865 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[1\]_i_2/I4 (372.4:440.4:440.4) (372.4:440.4:440.4))
|
3866 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1/I4 (245.1:286.1:286.1) (245.1:286.1:286.1))
|
3867 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/CE (526.5:620.5:620.5) (526.5:620.5:620.5))
|
3868 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/CE (526.5:620.5:620.5) (526.5:620.5:620.5))
|
3869 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/CE (524.5:618.5:618.5) (524.5:618.5:618.5))
|
3870 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/CE (524.5:618.5:618.5) (524.5:618.5:618.5))
|
3871 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/CE (457.4:539.4:539.4) (457.4:539.4:539.4))
|
3872 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/CE (524.5:618.5:618.5) (524.5:618.5:618.5))
|
3873 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/CE (524.5:618.5:618.5) (524.5:618.5:618.5))
|
3874 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/CE (526.5:620.5:620.5) (526.5:620.5:620.5))
|
3875 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/CE (457.4:539.4:539.4) (457.4:539.4:539.4))
|
3876 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q rx_fifo_valid_data_reg_i_1/I0 (558.8:661.8:661.8) (558.8:661.8:661.8))
|
3877 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q key_o\[0\]_i_1/I1 (623.7:745.7:745.7) (623.7:745.7:745.7))
|
3878 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q plain_text_data_o\[0\]_i_1/I1 (530.7:633.7:633.7) (530.7:633.7:633.7))
|
3879 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q key_o\[127\]_i_1/I2 (298.0:353.0:353.0) (298.0:353.0:353.0))
|
3880 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q key_set_in_progress_reg_i_2/I2 (324.6:385.6:385.6) (324.6:385.6:385.6))
|
3881 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q data_counter_reg\[3\]_i_3/I4 (316.6:375.6:375.6) (316.6:375.6:375.6))
|
3882 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[0\]/Q plain_text_set_in_progress_reg_i_2/I4 (460.0:547.0:547.0) (460.0:547.0:547.0))
|
3883 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/Q key_o\[127\]_i_6/I1 (278.6:332.6:332.6) (278.6:332.6:332.6))
|
3884 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/Q key_o\[1\]_i_1/I1 (943.1:1128.1:1128.1) (943.1:1128.1:1128.1))
|
3885 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[1\]/Q plain_text_data_o\[1\]_i_1/I1 (670.9:802.9:802.9) (670.9:802.9:802.9))
|
3886 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/Q key_o\[127\]_i_6/I0 (380.2:454.2:454.2) (380.2:454.2:454.2))
|
3887 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/Q key_o\[2\]_i_1/I1 (693.8:828.8:828.8) (693.8:828.8:828.8))
|
3888 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/Q plain_text_data_o\[2\]_i_1/I1 (725.9:869.9:869.9) (725.9:869.9:869.9))
|
3889 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[2\]/Q wait_tx_fifo_empty_reg_i_2/I1 (403.1:483.1:483.1) (403.1:483.1:483.1))
|
3890 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/Q key_o\[3\]_i_1/I1 (799.8:954.8:954.8) (799.8:954.8:954.8))
|
3891 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/Q plain_text_data_o\[3\]_i_1/I1 (633.0:757.0:757.0) (633.0:757.0:757.0))
|
3892 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[3\]/Q key_o\[127\]_i_4/I2 (234.8:281.8:281.8) (234.8:281.8:281.8))
|
3893 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q key_o\[4\]_i_1/I1 (283.7:336.7:336.7) (283.7:336.7:336.7))
|
3894 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q key_set_in_progress_reg_i_2/I1 (283.7:336.7:336.7) (283.7:336.7:336.7))
|
3895 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q plain_text_data_o\[4\]_i_1/I1 (716.5:855.5:855.5) (716.5:855.5:855.5))
|
3896 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q data_counter_reg\[3\]_i_3/I3 (274.7:326.7:326.7) (274.7:326.7:326.7))
|
3897 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q key_o\[127\]_i_1/I3 (314.0:375.0:375.0) (314.0:375.0:375.0))
|
3898 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[4\]/Q plain_text_set_in_progress_reg_i_2/I3 (357.0:426.0:426.0) (357.0:426.0:426.0))
|
3899 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/Q key_o\[127\]_i_4/I1 (370.8:442.8:442.8) (370.8:442.8:442.8))
|
3900 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/Q key_o\[5\]_i_1/I1 (726.0:870.0:870.0) (726.0:870.0:870.0))
|
3901 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[5\]/Q plain_text_data_o\[5\]_i_1/I1 (881.4:1052.4:1052.4) (881.4:1052.4:1052.4))
|
3902 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/Q key_o\[6\]_i_1/I1 (614.0:732.0:732.0) (614.0:732.0:732.0))
|
3903 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/Q plain_text_data_o\[6\]_i_1/I1 (530.2:632.2:632.2) (530.2:632.2:632.2))
|
3904 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[6\]/Q key_o\[127\]_i_4/I3 (448.7:533.7:533.7) (448.7:533.7:533.7))
|
3905 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/Q key_o\[7\]_i_1/I1 (913.0:1092.0:1092.0) (913.0:1092.0:1092.0))
|
3906 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/Q plain_text_data_o\[7\]_i_1/I1 (671.9:804.9:804.9) (671.9:804.9:804.9))
|
3907 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg\[7\]/Q key_o\[127\]_i_4/I4 (268.7:322.7:322.7) (268.7:322.7:322.7))
|
3908 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/Q key_o\[127\]_i_3/I0 (448.8:536.8:536.8) (448.8:536.8:536.8))
|
3909 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/Q plain_text_data_o\[127\]_i_3/I1 (368.9:444.9:444.9) (368.9:444.9:444.9))
|
3910 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/Q key_o\[127\]_i_6/I2 (368.9:444.9:444.9) (368.9:444.9:444.9))
|
3911 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg\[1\]/Q plain_text_data_valid_o_i_4/I2 (349.8:419.8:419.8) (349.8:419.8:419.8))
|
3912 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q plain_text_data_o\[127\]_i_3/I0 (618.7:721.7:721.7) (618.7:721.7:721.7))
|
3913 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q key_o\[127\]_i_3/I1 (627.7:733.7:733.7) (627.7:733.7:733.7))
|
3914 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q plain_text_data_valid_o_i_4/I1 (406.7:471.7:471.7) (406.7:471.7:471.7))
|
3915 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q key_o\[127\]_i_6/I3 (618.7:721.7:721.7) (618.7:721.7:721.7))
|
3916 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[0\]_i_2/I1 (212.4:250.4:250.4) (212.4:250.4:250.4))
|
3917 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[1\]_i_2/I1 (210.4:248.4:248.4) (210.4:248.4:248.4))
|
3918 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1/I4 (385.4:455.4:455.4) (385.4:455.4:455.4))
|
3919 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/D (321.3:390.3:390.3) (321.3:390.3:390.3))
|
3920 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[2\]_i_1/I3 (372.3:446.3:446.3) (372.3:446.3:446.3))
|
3921 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_1/I3 (533.3:638.3:638.3) (533.3:638.3:638.3))
|
3922 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[0\]\.ce_out_i_reg\[0\]/CE (430.7:512.7:512.7) (430.7:512.7:512.7))
|
3923 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[1\]\.ce_out_i_reg\[1\]/CE (430.7:512.7:512.7) (430.7:512.7:512.7))
|
3924 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[2\]\.ce_out_i_reg\[2\]/CE (430.7:512.7:512.7) (430.7:512.7:512.7))
|
3925 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS\[3\]\.ce_out_i_reg\[3\]/CE (430.7:512.7:512.7) (430.7:512.7:512.7))
|
3926 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1/I1 (389.5:458.5:458.5) (389.5:458.5:458.5))
|
3927 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[0\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1/I1 (227.1:274.1:274.1) (227.1:274.1:274.1))
|
3928 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[1\]_i_2/O U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1/I1 (298.9:354.9:354.9) (298.9:354.9:354.9))
|
3929 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/I0 (477.0:562.0:562.0) (477.0:562.0:562.0))
|
3930 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[0\]_i_2/I0 (644.6:759.6:759.6) (644.6:759.6:759.6))
|
3931 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_2/I1 (476.4:560.4:560.4) (476.4:560.4:560.4))
|
3932 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_i_1/I2 (149.8:173.8:173.8) (149.8:173.8:173.8))
|
3933 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1/I2 (476.4:560.4:560.4) (476.4:560.4:560.4))
|
3934 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1/I0 (631.8:742.8:742.8) (631.8:742.8:742.8))
|
3935 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1/I1 (479.5:562.5:562.5) (479.5:562.5:562.5))
|
3936 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1/I2 (396.2:466.2:466.2) (396.2:466.2:466.2))
|
3937 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1/I2 (384.5:450.5:450.5) (384.5:450.5:450.5))
|
3938 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[0\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1/I3 (238.7:279.7:279.7) (238.7:279.7:279.7))
|
3939 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i\[3\]_i_2/I0 (279.8:322.8:322.8) (279.8:322.8:322.8))
|
3940 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state\[1\]_i_2/I0 (359.6:420.6:420.6) (359.6:420.6:420.6))
|
3941 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i\[7\]_i_1/I1 (275.4:318.4:318.4) (275.4:318.4:318.4))
|
3942 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_rnw_i_i_1/I3 (494.7:578.7:578.7) (494.7:578.7:578.7))
|
3943 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2_i_1/I3 (279.8:322.8:322.8) (279.8:322.8:322.8))
|
3944 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rvalid_i_i_1/I0 (339.5:393.5:393.5) (339.5:393.5:393.5))
|
3945 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bresp_i\[1\]_i_1/I1 (214.7:246.7:246.7) (214.7:246.7:246.7))
|
3946 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_bvalid_i_i_1/I1 (323.8:376.8:376.8) (323.8:376.8:376.8))
|
3947 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[0\]_i_1/I2 (494.7:578.7:578.7) (494.7:578.7:578.7))
|
3948 |
|
|
(INTERCONNECT U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/state_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/state\[1\]_i_1/I3 (340.5:394.5:394.5) (340.5:394.5:394.5))
|
3949 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3950 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_1_reg/CE (342.3:408.3:408.3) (342.3:408.3:408.3))
|
3951 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3952 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_3_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3953 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_4_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3954 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_5_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3955 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_6_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3956 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_7_reg/CE (342.3:408.3:408.3) (342.3:408.3:408.3))
|
3957 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_8_reg/CE (342.3:408.3:408.3) (342.3:408.3:408.3))
|
3958 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_9_reg/CE (342.3:408.3:408.3) (342.3:408.3:408.3))
|
3959 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/CE (341.3:406.3:406.3) (341.3:406.3:406.3))
|
3960 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/CE (210.0:248.0:248.0) (210.0:248.0:248.0))
|
3961 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/CE (285.0:341.0:341.0) (285.0:341.0:341.0))
|
3962 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/I0 (306.4:357.4:357.4) (306.4:357.4:357.4))
|
3963 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1/I1 (236.4:274.4:274.4) (236.4:274.4:274.4))
|
3964 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/I1 (236.4:274.4:274.4) (236.4:274.4:274.4))
|
3965 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_2/I1 (224.9:262.9:262.9) (224.9:262.9:262.9))
|
3966 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/I2 (306.4:357.4:357.4) (306.4:357.4:357.4))
|
3967 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1/I2 (222.9:260.9:260.9) (222.9:260.9:260.9))
|
3968 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/CE (265.0:312.0:312.0) (265.0:312.0:312.0))
|
3969 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/CE (340.0:405.0:405.0) (340.0:405.0:405.0))
|
3970 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/tx_Data_Enable_i_1/I2 (555.2:654.2:654.2) (555.2:654.2:654.2))
|
3971 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
3972 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[1\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
3973 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
3974 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I1 (381.8:457.8:457.8) (381.8:457.8:457.8))
|
3975 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I4 (233.1:277.1:277.1) (233.1:277.1:277.1))
|
3976 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3977 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I0 (359.1:433.1:433.1) (359.1:433.1:433.1))
|
3978 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/D (33.0:42.0:42.0) (33.0:42.0:42.0))
|
3979 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/I0 (268.0:324.0:324.0) (268.0:324.0:324.0))
|
3980 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
3981 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/D (24.0:30.0:30.0) (24.0:30.0:30.0))
|
3982 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
3983 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1/I0 (373.4:444.4:444.4) (373.4:444.4:444.4))
|
3984 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1/I0 (373.4:444.4:444.4) (373.4:444.4:444.4))
|
3985 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/O U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1/I3 (373.4:444.4:444.4) (373.4:444.4:444.4))
|
3986 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[1\]_i_1/I1 (436.4:513.4:513.4) (436.4:513.4:513.4))
|
3987 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I1 (433.4:509.4:509.4) (433.4:509.4:509.4))
|
3988 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_2/I1 (436.4:513.4:513.4) (436.4:513.4:513.4))
|
3989 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2/I1 (218.9:256.9:256.9) (218.9:256.9:256.9))
|
3990 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/I2 (218.9:256.9:256.9) (218.9:256.9:256.9))
|
3991 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I3 (216.9:253.9:253.9) (216.9:253.9:253.9))
|
3992 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[0\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I4 (306.5:362.5:362.5) (306.5:362.5:362.5))
|
3993 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[1\]_i_1/I0 (262.5:306.5:306.5) (262.5:306.5:306.5))
|
3994 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I0 (312.8:369.8:369.8) (312.8:369.8:369.8))
|
3995 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_2/I0 (262.5:306.5:306.5) (262.5:306.5:306.5))
|
3996 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/I1 (333.5:390.5:390.5) (333.5:390.5:390.5))
|
3997 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2/I2 (333.5:390.5:390.5) (333.5:390.5:390.5))
|
3998 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I2 (329.5:385.5:385.5) (329.5:385.5:385.5))
|
3999 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[1\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I5 (431.8:508.8:508.8) (431.8:508.8:508.8))
|
4000 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2/I0 (424.6:498.6:498.6) (424.6:498.6:498.6))
|
4001 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I2 (327.5:382.5:382.5) (327.5:382.5:382.5))
|
4002 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_2/I2 (328.5:384.5:384.5) (328.5:384.5:384.5))
|
4003 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I3 (362.6:425.6:425.6) (362.6:425.6:425.6))
|
4004 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/I3 (424.6:498.6:498.6) (424.6:498.6:498.6))
|
4005 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[2\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I4 (112.5:128.5:128.5) (112.5:128.5:128.5))
|
4006 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I0 (263.6:308.6:308.6) (263.6:308.6:308.6))
|
4007 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/I0 (349.6:410.6:410.6) (349.6:410.6:410.6))
|
4008 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I1 (209.6:244.6:244.6) (209.6:244.6:244.6))
|
4009 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I1 (350.6:411.6:411.6) (350.6:411.6:411.6))
|
4010 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_2/I3 (349.6:410.6:410.6) (349.6:410.6:410.6))
|
4011 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[3\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I5 (217.4:255.4:255.4) (217.4:255.4:255.4))
|
4012 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/I1 (257.7:298.7:298.7) (257.7:298.7:298.7))
|
4013 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[0\]_i_1/I2 (342.7:400.7:400.7) (342.7:400.7:400.7))
|
4014 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_1/I3 (172.7:198.7:198.7) (172.7:198.7:198.7))
|
4015 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_2/I4 (235.9:273.9:273.9) (235.9:273.9:273.9))
|
4016 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I5 (261.7:303.7:303.7) (261.7:303.7:303.7))
|
4017 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[4\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I5 (237.9:275.9:275.9) (237.9:275.9:275.9))
|
4018 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[5\]_i_1/I0 (305.4:359.4:359.4) (305.4:359.4:359.4))
|
4019 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1/I1 (346.6:406.6:406.6) (346.6:406.6:406.6))
|
4020 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2/I1 (425.6:500.6:500.6) (425.6:500.6:500.6))
|
4021 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1/I2 (346.6:406.6:406.6) (346.6:406.6:406.6))
|
4022 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1/I2 (350.6:411.6:411.6) (350.6:411.6:411.6))
|
4023 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I3 (425.6:500.6:500.6) (425.6:500.6:500.6))
|
4024 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[5\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/I3 (425.6:500.6:500.6) (425.6:500.6:500.6))
|
4025 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2/I0 (374.0:448.0:448.0) (374.0:448.0:448.0))
|
4026 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1/I1 (297.6:357.6:357.6) (297.6:357.6:357.6))
|
4027 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1/I1 (165.6:198.6:198.6) (165.6:198.6:198.6))
|
4028 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1/I2 (297.6:357.6:357.6) (297.6:357.6:357.6))
|
4029 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/I2 (374.0:448.0:448.0) (374.0:448.0:448.0))
|
4030 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[6\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I4 (375.0:449.0:449.0) (375.0:449.0:449.0))
|
4031 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud_i_1/I0 (312.7:366.7:366.7) (312.7:366.7:366.7))
|
4032 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[2\]_i_2/I2 (385.8:453.8:453.8) (385.8:453.8:453.8))
|
4033 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[3\]_i_1/I2 (386.8:454.8:454.8) (386.8:454.8:454.8))
|
4034 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[6\]_i_1/I3 (312.7:366.7:366.7) (312.7:366.7:366.7))
|
4035 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[7\]_i_1/I3 (313.7:367.7:367.7) (313.7:367.7:367.7))
|
4036 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/BAUD_RATE_I/count_reg\[7\]/Q U0/UARTLITE_CORE_I/BAUD_RATE_I/count\[4\]_i_1/I4 (385.8:453.8:453.8) (385.8:453.8:453.8))
|
4037 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q addr_reg\[3\]_i_3/I0 (387.4:458.4:458.4) (387.4:458.4:458.4))
|
4038 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q FSM_sequential_sys_state\[0\]_i_2/I1 (175.5:208.5:208.5) (175.5:208.5:208.5))
|
4039 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q FSM_sequential_sys_state\[1\]_i_2/I1 (249.6:297.6:297.6) (249.6:297.6:297.6))
|
4040 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q FSM_sequential_sys_state\[2\]_i_3/I1 (382.5:451.5:451.5) (382.5:451.5:451.5))
|
4041 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q addr_reg\[2\]_i_2/I1 (209.4:247.4:247.4) (209.4:247.4:247.4))
|
4042 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q axi_data_wr_reg\[7\]_i_3/I2 (209.4:247.4:247.4) (209.4:247.4:247.4))
|
4043 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q cipher_data_reg\[127\]_i_5/I3 (455.6:537.6:537.6) (455.6:537.6:537.6))
|
4044 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/Interrupt_reg/Q FSM_sequential_sys_state\[2\]_i_5/I4 (301.5:357.5:357.5) (301.5:357.5:357.5))
|
4045 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/D (25.0:31.0:31.0) (25.0:31.0:31.0))
|
4046 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/D (160.5:192.5:192.5) (160.5:192.5:192.5))
|
4047 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1/I0 (453.1:536.1:536.1) (453.1:536.1:536.1))
|
4048 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/I0 (453.1:536.1:536.1) (453.1:536.1:536.1))
|
4049 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/I1 (452.1:535.1:535.1) (452.1:535.1:535.1))
|
4050 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/I1 (452.1:535.1:535.1) (452.1:535.1:535.1))
|
4051 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1/I2 (371.8:441.8:441.8) (371.8:441.8:441.8))
|
4052 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_2/I2 (371.8:441.8:441.8) (371.8:441.8:441.8))
|
4053 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1/I3 (372.8:443.8:443.8) (372.8:443.8:443.8))
|
4054 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din_reg\[2\]/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4055 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din_reg\[3\]/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
4056 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din_reg\[4\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4057 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din_reg\[5\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
4058 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din_reg\[6\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4059 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din_reg\[7\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
4060 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din_reg\[8\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4061 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1/I2 (479.1:565.1:565.1) (479.1:565.1:565.1))
|
4062 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1/I4 (225.5:266.5:266.5) (225.5:266.5:266.5))
|
4063 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1/I4 (478.1:565.1:565.1) (478.1:565.1:565.1))
|
4064 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1/I4 (373.2:440.2:440.2) (373.2:440.2:440.2))
|
4065 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1/I4 (303.2:357.2:357.2) (303.2:357.2:357.2))
|
4066 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1/I4 (480.1:566.1:566.1) (480.1:566.1:566.1))
|
4067 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1/I4 (480.1:566.1:566.1) (480.1:566.1:566.1))
|
4068 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1/I4 (307.1:361.1:361.1) (307.1:361.1:361.1))
|
4069 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
4070 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/frame_err_ocrd_reg/D (24.0:30.0:30.0) (24.0:30.0:30.0))
|
4071 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/running_reg/D (33.0:42.0:42.0) (33.0:42.0:42.0))
|
4072 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1/O U0/UARTLITE_CORE_I/status_reg_reg\[1\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4073 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1/I0 (443.7:532.7:532.7) (443.7:532.7:532.7))
|
4074 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4075 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2/D (177.9:216.9:216.9) (177.9:216.9:216.9))
|
4076 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/D (336.4:412.4:412.4) (336.4:412.4:412.4))
|
4077 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D (410.8:501.8:501.8) (410.8:501.8:501.8))
|
4078 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_1_reg/D (332.0:401.0:401.0) (332.0:401.0:401.0))
|
4079 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1/I1 (508.9:606.9:606.9) (508.9:606.9:606.9))
|
4080 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1/I3 (449.3:535.3:535.3) (449.3:535.3:535.3))
|
4081 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/I3 (449.3:535.3:535.3) (449.3:535.3:535.3))
|
4082 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC\.SINGLE_BIT\.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1/I0 (617.9:735.9:735.9) (617.9:735.9:735.9))
|
4083 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[1\]\.fifo_din_reg\[1\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4084 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[1\]\.fifo_din_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1/I1 (416.6:493.6:493.6) (416.6:493.6:493.6))
|
4085 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[1\]\.fifo_din_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1/I4 (245.6:290.6:290.6) (245.6:290.6:290.6))
|
4086 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[1\]\.fifo_din_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/D (169.8:200.8:200.8) (169.8:200.8:200.8))
|
4087 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1/I0 (250.7:294.7:294.7) (250.7:294.7:294.7))
|
4088 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1/I1 (251.7:295.7:295.7) (251.7:295.7:295.7))
|
4089 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/D (180.9:212.9:212.9) (180.9:212.9:212.9))
|
4090 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1/I0 (384.3:455.3:455.3) (384.3:455.3:455.3))
|
4091 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1/I1 (205.6:242.6:242.6) (205.6:242.6:242.6))
|
4092 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/D (238.6:283.6:283.6) (238.6:283.6:283.6))
|
4093 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1/I0 (238.7:279.7:279.7) (238.7:279.7:279.7))
|
4094 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1/I1 (242.7:284.7:284.7) (242.7:284.7:284.7))
|
4095 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/D (258.2:305.2:305.2) (258.2:305.2:305.2))
|
4096 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din_reg\[5\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1/I0 (304.1:358.1:358.1) (304.1:358.1:358.1))
|
4097 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din_reg\[5\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1/I1 (213.4:250.4:250.4) (213.4:250.4:250.4))
|
4098 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din_reg\[5\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/D (321.6:382.6:382.6) (321.6:382.6:382.6))
|
4099 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din_reg\[6\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1/I0 (238.4:279.4:279.4) (238.4:279.4:279.4))
|
4100 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din_reg\[6\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1/I1 (242.4:284.4:284.4) (242.4:284.4:284.4))
|
4101 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din_reg\[6\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/D (278.9:325.9:325.9) (278.9:325.9:325.9))
|
4102 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din_reg\[7\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1/I0 (314.0:368.0:368.0) (314.0:368.0:368.0))
|
4103 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din_reg\[7\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1/I1 (334.1:395.1:395.1) (334.1:395.1:395.1))
|
4104 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din_reg\[7\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/D (181.3:213.3:213.3) (181.3:213.3:213.3))
|
4105 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din_reg\[8\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1/I0 (303.1:357.1:357.1) (303.1:357.1:357.1))
|
4106 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din_reg\[8\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1/I0 (279.3:331.3:331.3) (279.3:331.3:331.3))
|
4107 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din_reg\[8\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/D (313.6:374.6:374.6) (313.6:374.6:374.6))
|
4108 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4109 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I5 (321.1:372.1:372.1) (321.1:372.1:372.1))
|
4110 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4111 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
4112 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/D (33.0:41.0:41.0) (33.0:41.0:41.0))
|
4113 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
4114 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/R (317.1:389.1:389.1) (317.1:389.1:389.1))
|
4115 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/S (213.7:259.7:259.7) (213.7:259.7:259.7))
|
4116 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/S (213.7:259.7:259.7) (213.7:259.7:259.7))
|
4117 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/S (317.1:389.1:389.1) (317.1:389.1:389.1))
|
4118 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/S (317.1:389.1:389.1) (317.1:389.1:389.1))
|
4119 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/S (317.1:389.1:389.1) (317.1:389.1:389.1))
|
4120 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4121 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I1 (300.5:358.5:358.5) (300.5:358.5:358.5))
|
4122 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_5__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I3 (371.7:447.7:447.7) (371.7:447.7:447.7))
|
4123 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I0 (477.8:568.8:568.8) (477.8:568.8:568.8))
|
4124 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/I3 (276.3:329.3:329.3) (276.3:329.3:329.3))
|
4125 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/I4 (371.3:439.3:439.3) (371.3:439.3:439.3))
|
4126 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I5 (206.3:246.3:246.3) (206.3:246.3:246.3))
|
4127 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I5 (371.3:439.3:439.3) (371.3:439.3:439.3))
|
4128 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I5 (252.3:300.3:300.3) (252.3:300.3:300.3))
|
4129 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A0 (510.9:599.9:599.9) (510.9:599.9:599.9))
|
4130 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A0 (509.9:597.9:597.9) (509.9:597.9:597.9))
|
4131 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A0 (411.8:481.8:481.8) (411.8:481.8:481.8))
|
4132 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A0 (425.8:489.8:489.8) (425.8:489.8:489.8))
|
4133 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A0 (510.9:599.9:599.9) (510.9:599.9:599.9))
|
4134 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A0 (509.9:597.9:597.9) (509.9:597.9:597.9))
|
4135 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A0 (411.8:481.8:481.8) (411.8:481.8:481.8))
|
4136 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A0 (425.8:489.8:489.8) (425.8:489.8:489.8))
|
4137 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/I0 (498.0:585.0:585.0) (498.0:585.0:585.0))
|
4138 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I0 (269.9:315.9:315.9) (269.9:315.9:315.9))
|
4139 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I1 (429.0:500.0:500.0) (429.0:500.0:500.0))
|
4140 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/I4 (246.3:287.3:287.3) (246.3:287.3:287.3))
|
4141 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I4 (250.3:292.3:292.3) (250.3:292.3:292.3))
|
4142 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I4 (402.3:474.3:474.3) (402.3:474.3:474.3))
|
4143 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A1 (342.9:405.9:405.9) (342.9:405.9:405.9))
|
4144 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A1 (343.9:406.9:406.9) (343.9:406.9:406.9))
|
4145 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A1 (467.5:549.5:549.5) (467.5:549.5:549.5))
|
4146 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A1 (473.5:553.5:553.5) (473.5:553.5:553.5))
|
4147 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A1 (342.9:405.9:405.9) (342.9:405.9:405.9))
|
4148 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A1 (343.9:406.9:406.9) (343.9:406.9:406.9))
|
4149 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A1 (467.5:549.5:549.5) (467.5:549.5:549.5))
|
4150 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A1 (473.5:553.5:553.5) (473.5:553.5:553.5))
|
4151 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2/I0 (368.5:431.5:431.5) (368.5:431.5:431.5))
|
4152 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I0 (533.5:627.5:627.5) (533.5:627.5:627.5))
|
4153 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4/I1 (454.5:533.5:533.5) (454.5:533.5:533.5))
|
4154 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_5__0/I1 (454.5:533.5:533.5) (454.5:533.5:533.5))
|
4155 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/I2 (368.5:431.5:431.5) (368.5:431.5:431.5))
|
4156 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I3 (369.5:433.5:433.5) (369.5:433.5:433.5))
|
4157 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4158 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4159 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4160 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A2 (327.5:382.5:382.5) (327.5:382.5:382.5))
|
4161 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4162 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4163 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A2 (320.5:372.5:372.5) (320.5:372.5:372.5))
|
4164 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A2 (327.5:382.5:382.5) (327.5:382.5:382.5))
|
4165 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4/I0 (152.2:176.2:176.2) (152.2:176.2:176.2))
|
4166 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_5__0/I0 (152.2:176.2:176.2) (152.2:176.2:176.2))
|
4167 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2/I1 (260.2:304.2:304.2) (260.2:304.2:304.2))
|
4168 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1/I3 (260.2:304.2:304.2) (260.2:304.2:304.2))
|
4169 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I4 (261.2:305.2:305.2) (261.2:305.2:305.2))
|
4170 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A3 (405.8:480.8:480.8) (405.8:480.8:480.8))
|
4171 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A3 (325.5:380.5:380.5) (325.5:380.5:380.5))
|
4172 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A3 (417.3:493.3:493.3) (417.3:493.3:493.3))
|
4173 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A3 (417.3:494.3:494.3) (417.3:494.3:494.3))
|
4174 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A3 (405.8:480.8:480.8) (405.8:480.8:480.8))
|
4175 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A3 (325.5:380.5:380.5) (325.5:380.5:380.5))
|
4176 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A3 (417.3:493.3:493.3) (417.3:493.3:493.3))
|
4177 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A3 (417.3:494.3:494.3) (417.3:494.3:494.3))
|
4178 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1/I2 (402.0:473.0:473.0) (402.0:473.0:473.0))
|
4179 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4/I2 (218.8:255.8:255.8) (218.8:255.8:255.8))
|
4180 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_5__0/I2 (218.8:255.8:255.8) (218.8:255.8:255.8))
|
4181 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I4 (234.0:275.0:275.0) (234.0:275.0:275.0))
|
4182 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/rx_Data_Present_Pre_i_1/I0 (222.1:255.1:255.1) (222.1:255.1:255.1))
|
4183 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/I0 (399.0:468.0:468.0) (399.0:468.0:468.0))
|
4184 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[3\]_i_2/I2 (399.0:468.0:468.0) (399.0:468.0:468.0))
|
4185 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/I4 (518.2:606.2:606.2) (518.2:606.2:606.2))
|
4186 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/I1 (427.1:496.1:496.1) (427.1:496.1:496.1))
|
4187 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1/I2 (345.9:395.9:395.9) (345.9:395.9:395.9))
|
4188 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1/I2 (191.1:222.1:222.1) (191.1:222.1:222.1))
|
4189 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2/I2 (262.0:307.0:307.0) (262.0:307.0:307.0))
|
4190 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1/I3 (190.1:220.1:220.1) (190.1:220.1:220.1))
|
4191 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/O U0/UARTLITE_CORE_I/Interrupt_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4192 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[7\]_i_2/I3 (383.2:458.2:458.2) (383.2:458.2:458.2))
|
4193 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/I1 (371.5:443.5:443.5) (371.5:443.5:443.5))
|
4194 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/I1 (431.0:513.0:513.0) (431.0:513.0:513.0))
|
4195 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/I1 (376.6:448.6:448.6) (376.6:448.6:448.6))
|
4196 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/I1 (334.4:405.4:405.4) (334.4:405.4:405.4))
|
4197 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/I1 (365.3:440.3:440.3) (365.3:440.3:440.3))
|
4198 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/I1 (376.0:451.0:451.0) (376.0:451.0:451.0))
|
4199 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[0\]_i_1/I1 (343.8:416.8:416.8) (343.8:416.8:416.8))
|
4200 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4201 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4202 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4203 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4204 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4205 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4206 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4207 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/CE (167.8:202.8:202.8) (167.8:202.8:202.8))
|
4208 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[1\]_i_1/I0 (386.1:459.1:459.1) (386.1:459.1:459.1))
|
4209 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/I1 (463.0:550.0:550.0) (463.0:550.0:550.0))
|
4210 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/I1 (391.0:465.0:465.0) (391.0:465.0:465.0))
|
4211 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1/I2 (221.8:264.8:264.8) (221.8:264.8:264.8))
|
4212 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1/O U0/UARTLITE_CORE_I/status_reg_reg\[2\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4213 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_i_1/I1 (304.1:360.1:360.1) (304.1:360.1:360.1))
|
4214 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1/I1 (478.5:557.5:557.5) (478.5:557.5:557.5))
|
4215 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/I0 (331.6:388.6:388.6) (331.6:388.6:388.6))
|
4216 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_Write_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/I2 (403.6:474.6:474.6) (403.6:474.6:474.6))
|
4217 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/frame_err_ocrd_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I5 (500.1:598.1:598.1) (500.1:598.1:598.1))
|
4218 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/frame_err_ocrd_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/I4 (333.0:400.0:400.0) (333.0:400.0:400.0))
|
4219 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/running_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I3 (465.4:553.4:553.4) (465.4:553.4:553.4))
|
4220 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/running_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/I4 (228.9:269.9:269.9) (228.9:269.9:269.9))
|
4221 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_1_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2_reg/D (344.3:416.3:416.3) (344.3:416.3:416.3))
|
4222 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_1_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I4 (400.3:477.3:477.3) (400.3:477.3:477.3))
|
4223 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_3_reg/D (232.6:284.6:284.6) (232.6:284.6:284.6))
|
4224 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I1 (160.6:194.6:194.6) (160.6:194.6:194.6))
|
4225 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_3_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_4_reg/D (422.9:507.9:507.9) (422.9:507.9:507.9))
|
4226 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_3_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I3 (306.9:362.9:362.9) (306.9:362.9:362.9))
|
4227 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_4_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_5_reg/D (422.6:508.6:508.6) (422.6:508.6:508.6))
|
4228 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_4_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I5 (306.9:362.9:362.9) (306.9:362.9:362.9))
|
4229 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_5_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_6_reg/D (261.4:316.4:316.4) (261.4:316.4:316.4))
|
4230 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_5_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I0 (242.1:286.1:286.1) (242.1:286.1:286.1))
|
4231 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_6_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_7_reg/D (484.5:585.5:585.5) (484.5:585.5:585.5))
|
4232 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_6_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I4 (387.5:464.5:464.5) (387.5:464.5:464.5))
|
4233 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_7_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_8_reg/D (393.7:476.7:476.7) (393.7:476.7:476.7))
|
4234 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_7_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I1 (424.7:506.7:506.7) (424.7:506.7:506.7))
|
4235 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_8_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_9_reg/D (415.6:498.6:498.6) (415.6:498.6:498.6))
|
4236 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_8_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I0 (548.6:650.6:650.6) (548.6:650.6:650.6))
|
4237 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/rx_9_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/I2 (138.5:164.5:164.5) (138.5:164.5:164.5))
|
4238 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4239 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_2/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_i_1/I2 (203.8:245.8:245.8) (203.8:245.8:245.8))
|
4240 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_i_1/I0 (362.7:430.7:430.7) (362.7:430.7:430.7))
|
4241 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/I0 (673.8:795.8:795.8) (673.8:795.8:795.8))
|
4242 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[2\]\.fifo_din\[2\]_i_1/I2 (706.3:833.3:833.3) (706.3:833.3:833.3))
|
4243 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[3\]\.fifo_din\[3\]_i_1/I2 (705.3:831.3:831.3) (705.3:831.3:831.3))
|
4244 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[4\]\.fifo_din\[4\]_i_1/I2 (611.9:726.9:726.9) (611.9:726.9:726.9))
|
4245 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[5\]\.fifo_din\[5\]_i_1/I2 (611.9:726.9:726.9) (611.9:726.9:726.9))
|
4246 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[6\]\.fifo_din\[6\]_i_1/I2 (603.3:711.3:711.3) (603.3:711.3:711.3))
|
4247 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[7\]\.fifo_din\[7\]_i_1/I2 (603.3:711.3:711.3) (603.3:711.3:711.3))
|
4248 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_1/I2 (490.3:577.3:577.3) (490.3:577.3:577.3))
|
4249 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1/I3 (507.5:601.5:601.5) (507.5:601.5:601.5))
|
4250 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/start_Edge_Detected_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/SERIAL_TO_PARALLEL\[1\]\.fifo_din\[1\]_i_1/I1 (458.4:547.4:547.4) (458.4:547.4:547.4))
|
4251 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1/I0 (242.7:284.7:284.7) (242.7:284.7:284.7))
|
4252 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_2/I0 (242.7:284.7:284.7) (242.7:284.7:284.7))
|
4253 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/stop_Bit_Position_i_1/I1 (241.7:283.7:283.7) (241.7:283.7:283.7))
|
4254 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/SERIAL_TO_PARALLEL\[8\]\.fifo_din\[8\]_i_2/I2 (401.0:470.0:470.0) (401.0:470.0:470.0))
|
4255 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/fifo_Write_i_1/I2 (401.0:470.0:470.0) (401.0:470.0:470.0))
|
4256 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/frame_err_ocrd_i_1/I2 (401.0:470.0:470.0) (401.0:470.0:470.0))
|
4257 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/stop_Bit_Position_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/running_i_1/I3 (401.0:470.0:470.0) (401.0:470.0:470.0))
|
4258 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_i_1/O U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4259 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_i_1/I2 (310.7:364.7:364.7) (310.7:364.7:364.7))
|
4260 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15_i_1/I1 (397.3:466.3:466.3) (397.3:466.3:466.3))
|
4261 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_6/I2 (395.3:463.3:463.3) (395.3:463.3:463.3))
|
4262 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_RX_I/valid_rx_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1__0/I0 (233.4:273.4:273.4) (233.4:273.4:273.4))
|
4263 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/D (25.0:31.0:31.0) (25.0:31.0:31.0))
|
4264 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[14\]\[0\]_srl15/D (230.4:278.4:278.4) (230.4:278.4:278.4))
|
4265 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN\.data_reg\[15\]\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/tx_Data_Enable_i_1/I0 (245.4:294.4:294.4) (245.4:294.4:294.4))
|
4266 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/tx_Data_Enable_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4267 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4268 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I5 (125.9:149.9:149.9) (125.9:149.9:149.9))
|
4269 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/D (41.0:53.0:53.0) (41.0:53.0:53.0))
|
4270 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4271 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/D (40.0:52.0:52.0) (40.0:52.0:52.0))
|
4272 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
4273 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_2__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I3 (159.8:195.8:195.8) (159.8:195.8:195.8))
|
4274 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/R (291.2:357.2:357.2) (291.2:357.2:357.2))
|
4275 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/S (291.2:357.2:357.2) (291.2:357.2:357.2))
|
4276 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/S (292.2:359.2:359.2) (292.2:359.2:359.2))
|
4277 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/S (291.2:357.2:357.2) (291.2:357.2:357.2))
|
4278 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/S (292.2:359.2:359.2) (292.2:359.2:359.2))
|
4279 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/S (292.2:359.2:359.2) (292.2:359.2:359.2))
|
4280 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4281 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I0 (137.6:163.6:163.6) (137.6:163.6:163.6))
|
4282 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4__0/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I3 (159.4:196.4:196.4) (159.4:196.4:196.4))
|
4283 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A0 (508.1:594.1:594.1) (508.1:594.1:594.1))
|
4284 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A0 (507.1:592.1:592.1) (507.1:592.1:592.1))
|
4285 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A0 (438.9:508.9:508.9) (438.9:508.9:508.9))
|
4286 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A0 (452.9:516.9:516.9) (452.9:516.9:516.9))
|
4287 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A0 (508.1:594.1:594.1) (508.1:594.1:594.1))
|
4288 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A0 (507.1:592.1:592.1) (507.1:592.1:592.1))
|
4289 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A0 (438.9:508.9:508.9) (438.9:508.9:508.9))
|
4290 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A0 (452.9:516.9:516.9) (452.9:516.9:516.9))
|
4291 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I1 (378.1:439.1:439.1) (378.1:439.1:439.1))
|
4292 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/I3 (261.0:299.0:299.0) (261.0:299.0:299.0))
|
4293 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I3 (349.0:403.0:403.0) (349.0:403.0:403.0))
|
4294 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I4 (452.1:527.1:527.1) (452.1:527.1:527.1))
|
4295 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I5 (350.0:404.0:404.0) (350.0:404.0:404.0))
|
4296 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I5 (261.0:299.0:299.0) (261.0:299.0:299.0))
|
4297 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A1 (432.5:506.5:506.5) (432.5:506.5:506.5))
|
4298 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A1 (433.5:507.5:507.5) (433.5:507.5:507.5))
|
4299 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A1 (428.2:500.2:500.2) (428.2:500.2:500.2))
|
4300 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A1 (434.2:504.2:504.2) (434.2:504.2:504.2))
|
4301 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A1 (432.5:506.5:506.5) (432.5:506.5:506.5))
|
4302 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A1 (433.5:507.5:507.5) (433.5:507.5:507.5))
|
4303 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A1 (428.2:500.2:500.2) (428.2:500.2:500.2))
|
4304 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A1 (434.2:504.2:504.2) (434.2:504.2:504.2))
|
4305 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2__0/I0 (348.5:405.5:405.5) (348.5:405.5:405.5))
|
4306 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/I0 (277.5:321.5:321.5) (277.5:321.5:321.5))
|
4307 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I1 (537.4:631.4:631.4) (537.4:631.4:631.4))
|
4308 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4__0/I1 (452.9:521.9:521.9) (452.9:521.9:521.9))
|
4309 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0/I3 (452.9:521.9:521.9) (452.9:521.9:521.9))
|
4310 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I5 (169.5:193.5:193.5) (169.5:193.5:193.5))
|
4311 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A2 (393.9:460.9:460.9) (393.9:460.9:460.9))
|
4312 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A2 (544.2:639.2:639.2) (544.2:639.2:639.2))
|
4313 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A2 (544.2:639.2:639.2) (544.2:639.2:639.2))
|
4314 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A2 (551.2:649.2:649.2) (551.2:649.2:649.2))
|
4315 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A2 (393.9:460.9:460.9) (393.9:460.9:460.9))
|
4316 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A2 (544.2:639.2:639.2) (544.2:639.2:639.2))
|
4317 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A2 (544.2:639.2:639.2) (544.2:639.2:639.2))
|
4318 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A2 (551.2:649.2:649.2) (551.2:649.2:649.2))
|
4319 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4__0/I0 (356.8:407.8:407.8) (356.8:407.8:407.8))
|
4320 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_2__0/I1 (421.9:495.9:495.9) (421.9:495.9:495.9))
|
4321 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I2 (170.8:196.8:196.8) (170.8:196.8:196.8))
|
4322 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0/I2 (356.8:407.8:407.8) (356.8:407.8:407.8))
|
4323 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I4 (403.9:473.9:473.9) (403.9:473.9:473.9))
|
4324 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/A3 (238.3:276.3:276.3) (238.3:276.3:276.3))
|
4325 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/A3 (239.3:278.3:278.3) (239.3:278.3:278.3))
|
4326 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/A3 (431.7:508.7:508.7) (431.7:508.7:508.7))
|
4327 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/A3 (431.7:509.7:509.7) (431.7:509.7:509.7))
|
4328 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/A3 (238.3:276.3:276.3) (238.3:276.3:276.3))
|
4329 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/A3 (239.3:278.3:278.3) (239.3:278.3:278.3))
|
4330 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/A3 (431.7:508.7:508.7) (431.7:508.7:508.7))
|
4331 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/A3 (431.7:509.7:509.7) (431.7:509.7:509.7))
|
4332 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_1__0/I0 (394.9:465.9:465.9) (394.9:465.9:465.9))
|
4333 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0/I0 (226.9:267.9:267.9) (226.9:267.9:267.9))
|
4334 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_4__0/I2 (226.9:267.9:267.9) (226.9:267.9:267.9))
|
4335 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[3\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I4 (98.7:114.7:114.7) (98.7:114.7:114.7))
|
4336 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[2\]_i_1/I0 (492.0:577.0:577.0) (492.0:577.0:577.0))
|
4337 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/tx_Buffer_Empty_Pre_i_1/I1 (319.5:371.5:371.5) (319.5:371.5:371.5))
|
4338 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/I3 (301.1:353.1:353.1) (301.1:353.1:353.1))
|
4339 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I0 (348.4:404.4:404.4) (348.4:404.4:404.4))
|
4340 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I0 (344.4:399.4:399.4) (344.4:399.4:399.4))
|
4341 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_2__0/I0 (433.1:510.1:510.1) (433.1:510.1:510.1))
|
4342 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/I1 (433.1:510.1:510.1) (433.1:510.1:510.1))
|
4343 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1/I1 (432.4:504.4:504.4) (432.4:504.4:504.4))
|
4344 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I2 (230.0:267.0:267.0) (230.0:267.0:267.0))
|
4345 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i_reg\[4\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I2 (429.4:501.4:501.4) (429.4:501.4:501.4))
|
4346 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Start_reg/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4347 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[0\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/I1 (387.5:452.5:452.5) (387.5:452.5:452.5))
|
4348 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[1\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/I2 (276.8:328.8:328.8) (276.8:328.8:328.8))
|
4349 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[2\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/I2 (374.9:445.9:445.9) (374.9:445.9:445.9))
|
4350 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[3\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/I4 (468.3:557.3:557.3) (468.3:557.3:557.3))
|
4351 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[4\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/I0 (451.3:533.3:533.3) (451.3:533.3:533.3))
|
4352 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[5\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/I2 (279.3:339.3:339.3) (279.3:339.3:339.3))
|
4353 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[6\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/I4 (227.3:277.3:277.3) (227.3:277.3:277.3))
|
4354 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/I4 (225.7:276.7:276.7) (225.7:276.7:276.7))
|
4355 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/serial_Data_reg/D (39.0:50.0:50.0) (39.0:50.0:50.0))
|
4356 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1/I0 (206.4:244.4:244.4) (206.4:244.4:244.4))
|
4357 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1/I1 (89.6:107.6:107.6) (89.6:107.6:107.6))
|
4358 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1/I2 (208.0:246.0:246.0) (208.0:246.0:246.0))
|
4359 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_1/I3 (308.6:366.6:366.6) (308.6:366.6:366.6))
|
4360 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.data_reg\[15\]\[7\]_srl16_i_1/I0 (335.7:395.7:395.7) (335.7:395.7:395.7))
|
4361 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[3\]_i_1/I0 (377.5:446.5:446.5) (377.5:446.5:446.5))
|
4362 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rresp_i\[1\]_i_1/I1 (335.7:395.7:395.7) (335.7:395.7:395.7))
|
4363 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INFERRED_GEN\.cnt_i\[4\]_i_5/I2 (466.4:548.4:548.4) (466.4:548.4:548.4))
|
4364 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/FIFO_Full_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I2 (414.7:489.7:489.7) (414.7:489.7:489.7))
|
4365 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
4366 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg/Q /I (1571.8:1790.8:1790.8) (1571.8:1790.8:1790.8))
|
4367 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4368 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1/I2 (237.5:283.5:283.5) (237.5:283.5:283.5))
|
4369 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[0\]_i_1__0/I1 (395.2:466.2:466.2) (395.2:466.2:466.2))
|
4370 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[2\]_i_1__0/I1 (185.1:217.1:217.1) (185.1:217.1:217.1))
|
4371 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[3\]_i_2__0/I1 (334.2:393.2:393.2) (334.2:393.2:393.2))
|
4372 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_2__0/I1 (307.1:360.1:360.1) (307.1:360.1:360.1))
|
4373 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_3__0/I1 (314.1:370.1:370.1) (314.1:370.1:370.1))
|
4374 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[1\]_i_1__0/I2 (334.2:393.2:393.2) (334.2:393.2:393.2))
|
4375 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/FIFO_Full_i_1__0/I3 (395.1:464.1:464.1) (395.1:464.1:464.1))
|
4376 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/D (38.0:49.0:49.0) (38.0:49.0:49.0))
|
4377 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/D (25.0:31.0:31.0) (25.0:31.0:31.0))
|
4378 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4379 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1/I0 (192.1:224.1:224.1) (192.1:224.1:224.1))
|
4380 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/I2 (331.0:386.0:386.0) (331.0:386.0:386.0))
|
4381 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/I2 (331.0:386.0:386.0) (331.0:386.0:386.0))
|
4382 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/I2 (331.1:388.1:388.1) (331.1:388.1:388.1))
|
4383 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/I0 (455.8:534.8:534.8) (455.8:534.8:534.8))
|
4384 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/I0 (326.1:382.1:382.1) (326.1:382.1:382.1))
|
4385 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/I3 (420.7:491.7:491.7) (420.7:491.7:491.7))
|
4386 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[0\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/I4 (461.8:538.8:538.8) (461.8:538.8:538.8))
|
4387 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/I0 (395.4:469.4:469.4) (395.4:469.4:469.4))
|
4388 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/I0 (395.4:469.4:469.4) (395.4:469.4:469.4))
|
4389 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1/I2 (307.6:365.6:365.6) (307.6:365.6:365.6))
|
4390 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/I3 (227.4:270.4:270.4) (227.4:270.4:270.4))
|
4391 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/I1 (409.3:484.3:484.3) (409.3:484.3:484.3))
|
4392 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/I2 (458.4:544.4:544.4) (458.4:544.4:544.4))
|
4393 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/I3 (481.3:570.3:570.3) (481.3:570.3:570.3))
|
4394 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/I3 (469.6:557.6:557.6) (469.6:557.6:557.6))
|
4395 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1/I1 (299.1:352.1:352.1) (299.1:352.1:352.1))
|
4396 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/I1 (322.0:379.0:379.0) (322.0:379.0:379.0))
|
4397 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/I1 (322.0:379.0:379.0) (322.0:379.0:379.0))
|
4398 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/I4 (203.0:240.0:240.0) (203.0:240.0:240.0))
|
4399 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_2/I0 (319.6:373.6:373.6) (319.6:373.6:373.6))
|
4400 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_3/I1 (319.6:373.6:373.6) (319.6:373.6:373.6))
|
4401 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_4/I1 (176.1:207.1:207.1) (176.1:207.1:207.1))
|
4402 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/serial_Data_i_5/I3 (202.6:238.6:238.6) (202.6:238.6:238.6))
|
4403 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/serial_Data_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_i_1/I2 (377.0:446.0:446.0) (377.0:446.0:446.0))
|
4404 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1/O U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/D (38.0:48.0:48.0) (38.0:48.0:48.0))
|
4405 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_i_1/I0 (292.6:348.6:348.6) (292.6:348.6:348.6))
|
4406 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/I0 (535.8:637.8:637.8) (535.8:637.8:637.8))
|
4407 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1/I3 (478.6:559.6:559.6) (478.6:559.6:559.6))
|
4408 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/I4 (365.8:435.8:435.8) (365.8:435.8:435.8))
|
4409 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/I4 (365.8:435.8:435.8) (365.8:435.8:435.8))
|
4410 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1/I2 (455.6:541.6:541.6) (455.6:541.6:541.6))
|
4411 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[2\]_i_1/I1 (332.4:390.4:390.4) (332.4:390.4:390.4))
|
4412 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1/I1 (257.5:305.5:305.5) (257.5:305.5:305.5))
|
4413 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_Read_i_1/I3 (407.4:479.4:479.4) (407.4:479.4:479.4))
|
4414 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[0\]_i_1/I3 (259.3:303.3:303.3) (259.3:303.3:303.3))
|
4415 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/mux_sel\[1\]_i_1/I3 (259.3:303.3:303.3) (259.3:303.3:303.3))
|
4416 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1/I0 (236.4:275.4:275.4) (236.4:275.4:275.4))
|
4417 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Data_Enable_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/tx_Data_Enable_i_1/I1 (258.3:302.3:302.3) (258.3:302.3:302.3))
|
4418 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Start_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_DataBits_i_1/I0 (399.7:463.7:463.7) (399.7:463.7:463.7))
|
4419 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Start_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_i_1/I1 (251.7:295.7:295.7) (251.7:295.7:295.7))
|
4420 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/UARTLITE_TX_I/tx_Start_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/tx_Start_i_1/I3 (250.7:294.7:294.7) (250.7:294.7:294.7))
|
4421 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/clr_Status_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1/I4 (370.8:439.8:439.8) (370.8:439.8:439.8))
|
4422 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/clr_Status_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1/I3 (164.8:198.8:198.8) (164.8:198.8:198.8))
|
4423 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/enable_interrupts_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[4\]_i_1/I0 (365.8:431.8:431.8) (365.8:431.8:431.8))
|
4424 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/enable_interrupts_reg/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/enable_interrupts_i_1/I3 (314.0:368.0:368.0) (314.0:368.0:368.0))
|
4425 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/enable_interrupts_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/I2 (334.1:395.1:395.1) (334.1:395.1:395.1))
|
4426 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/reset_RX_FIFO_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1/I0 (225.5:267.5:267.5) (225.5:267.5:267.5))
|
4427 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/reset_TX_FIFO_reg/Q U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN\.cnt_i\[4\]_i_1__0/I0 (188.6:228.6:228.6) (188.6:228.6:228.6))
|
4428 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/I0 (300.5:356.5:356.5) (300.5:356.5:356.5))
|
4429 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/status_reg_reg\[1\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[6\]_i_1/I0 (304.2:361.2:361.2) (304.2:361.2:361.2))
|
4430 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/status_reg_reg\[1\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/status_reg\[1\]_i_1/I2 (232.1:274.1:274.1) (232.1:274.1:274.1))
|
4431 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/status_reg_reg\[2\]/Q U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_rdata_i\[5\]_i_1/I0 (251.7:296.7:296.7) (251.7:296.7:296.7))
|
4432 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/status_reg_reg\[2\]/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/status_reg\[2\]_i_1/I0 (247.9:289.9:289.9) (247.9:289.9:289.9))
|
4433 |
|
|
(INTERCONNECT U0/UARTLITE_CORE_I/tx_Buffer_Empty_Pre_reg/Q U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/I4 (161.3:194.3:194.3) (161.3:194.3:194.3))
|
4434 |
|
|
)
|
4435 |
|
|
)
|
4436 |
|
|
)
|
4437 |
|
|
)
|