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Amr_Salah |
/*
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Project : AES
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Standard doc. : FIPS 197
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Module name : MixColumns block
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Dependancy :
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Design doc. :
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References :
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Description : This Module is used to perform Mix Columns calculations
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as declared in standard document
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Owner : Amr Salah
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*/
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`timescale 1 ns/1 ps
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module MixColumns
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#
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(
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parameter DATA_W = 128 //data width
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)
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(
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input clk, //system clock
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input reset, //asynch active low reset
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input valid_in, //input valid signal
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input [DATA_W-1:0] data_in, //input data
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output reg valid_out, //output valid signal
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output reg [DATA_W-1:0] data_out //output data
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)
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;
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wire [7:0] State [0:15]; //array of wires to form state array
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wire [7:0] State_Mulx2 [0:15]; //array of wires to perform multiplication by 02
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wire [7:0] State_Mulx3 [0:15]; //array of wires to perform multiplication by 03
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genvar i ;
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generate
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for(i=0;i<=15;i=i+1) begin :MUL
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assign State[i]= data_in[(((15-i)*8)+7):((15-i)*8)]; // filling state array as each row represents one byte ex: state[0] means first byte and so on
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assign State_Mulx2[i]= (State[i][7])?((State[i]<<1) ^ 8'h1b):(State[i]<<1); //Multiplication by {02} in finite field is done shifting 1 bit lift //and xoring with 1b if the most bit =1
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assign State_Mulx3[i]= (State_Mulx2[i])^State[i]; // Multiply by {03} in finite field can be done as multiplication by {02 xor 01}
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end
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endgenerate
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always@(posedge clk or negedge reset)
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if(!reset)begin
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valid_out <= 1'b0;
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data_out <= 'b0;
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end else begin
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if(valid_in) begin //mul by 2 and mul by 3 are used to perform matrix multiplication for each column
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data_out[(15*8)+7:(15*8)]<= State_Mulx2[0] ^ State_Mulx3[1] ^ State[2] ^ State[3]; //first column
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data_out[(14*8)+7:(14*8)]<= State[0] ^ State_Mulx2[1] ^ State_Mulx3[2] ^ State[3];
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data_out[(13*8)+7:(13*8)]<= State[0] ^ State[1] ^ State_Mulx2[2] ^ State_Mulx3[3];
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data_out[(12*8)+7:(12*8)]<= State_Mulx3[0] ^ State[1] ^ State[2] ^ State_Mulx2[3];
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/*********************************************************************************/
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data_out[(11*8)+7:(11*8)]<= State_Mulx2[4] ^ State_Mulx3[5] ^ State[6] ^ State[7]; //second column
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data_out[(10*8)+7:(10*8)]<= State[4] ^ State_Mulx2[5] ^ State_Mulx3[6] ^ State[7];
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data_out[(9*8)+7:(9*8)] <= State[4] ^ State[5] ^ State_Mulx2[6] ^ State_Mulx3[7];
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data_out[(8*8)+7:(8*8)]<= State_Mulx3[4] ^ State[5] ^ State[6] ^ State_Mulx2[7];
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/**********************************************************************************/
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data_out[(7*8)+7:(7*8)]<= State_Mulx2[8] ^ State_Mulx3[9] ^ State[10] ^ State[11]; //third column
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data_out[(6*8)+7:(6*8)]<= State[8] ^ State_Mulx2[9] ^ State_Mulx3[10] ^ State[11];
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data_out[(5*8)+7:(5*8)]<= State[8] ^ State[9] ^ State_Mulx2[10] ^ State_Mulx3[11];
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data_out[(4*8)+7:(4*8)]<= State_Mulx3[8] ^ State[9] ^ State[10] ^ State_Mulx2[11];
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/***********************************************************************************/
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data_out[(3*8)+7:(3*8)]<= State_Mulx2[12] ^ State_Mulx3[13] ^ State[14] ^ State[15]; //fourth column
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data_out[(2*8)+7:(2*8)]<= State[12] ^ State_Mulx2[13] ^ State_Mulx3[14] ^ State[15];
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data_out[(1*8)+7:(1*8)]<= State[12] ^ State[13] ^ State_Mulx2[14] ^ State_Mulx3[15];
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data_out[(0*8)+7:(0*8)]<= State_Mulx3[12] ^ State[13] ^ State[14] ^ State_Mulx2[15];
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end
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valid_out <= valid_in;
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end
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endmodule
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