OpenCores
URL https://opencores.org/ocsvn/aes-128_pipelined_encryption/aes-128_pipelined_encryption/trunk

Subversion Repositories aes-128_pipelined_encryption

[/] [aes-128_pipelined_encryption/] [trunk/] [rtl/] [MixColumns.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 Amr_Salah
/*
2
Project        : AES
3
Standard doc.  : FIPS 197
4
Module name    : MixColumns block
5
Dependancy     :
6
Design doc.    :
7
References     :
8
Description    : This Module is used to perform Mix Columns calculations
9
                 as declared in standard document
10
Owner          : Amr Salah
11
*/
12
 
13
`timescale 1 ns/1 ps
14
 
15
module MixColumns
16
#
17
(
18
parameter DATA_W = 128             //data width
19
)
20
(
21
input clk,                         //system clock
22
input reset,                       //asynch active low reset
23
input valid_in,                    //input valid signal   
24
input [DATA_W-1:0] data_in,        //input data
25
output reg valid_out,              //output valid signal
26
output reg [DATA_W-1:0] data_out   //output data
27
)
28
;
29
 
30
wire [7:0] State [0:15];        //array of wires to form state array
31
wire [7:0] State_Mulx2 [0:15];  //array of wires to perform multiplication by 02
32
wire [7:0] State_Mulx3 [0:15];  //array of wires to perform multiplication by 03
33
 
34
genvar i ;
35
generate
36
for(i=0;i<=15;i=i+1) begin :MUL
37
 assign State[i]= data_in[(((15-i)*8)+7):((15-i)*8)];   // filling state array as each row represents one byte ex: state[0] means first byte and so on
38
 assign State_Mulx2[i]= (State[i][7])?((State[i]<<1) ^ 8'h1b):(State[i]<<1);  //Multiplication by {02} in finite field is done shifting 1 bit lift                                                                               //and xoring with 1b if the most bit =1
39
 assign State_Mulx3[i]= (State_Mulx2[i])^State[i];  // Multiply by {03} in finite field can be done as multiplication by {02 xor 01}
40
end
41
endgenerate
42
 
43
 
44
always@(posedge clk or negedge reset)
45
if(!reset)begin
46
    valid_out <= 1'b0;
47
    data_out <= 'b0;
48
end else begin
49
   if(valid_in) begin               //mul by 2 and mul by 3 are used to perform matrix multiplication  for each column
50
    data_out[(15*8)+7:(15*8)]<=  State_Mulx2[0] ^ State_Mulx3[1] ^ State[2] ^ State[3];   //first column
51
    data_out[(14*8)+7:(14*8)]<= State[0] ^ State_Mulx2[1] ^ State_Mulx3[2] ^ State[3];
52
    data_out[(13*8)+7:(13*8)]<= State[0] ^ State[1] ^ State_Mulx2[2] ^ State_Mulx3[3];
53
    data_out[(12*8)+7:(12*8)]<= State_Mulx3[0] ^ State[1] ^ State[2] ^ State_Mulx2[3];
54
    /*********************************************************************************/
55
    data_out[(11*8)+7:(11*8)]<= State_Mulx2[4] ^ State_Mulx3[5] ^ State[6] ^ State[7];   //second column
56
    data_out[(10*8)+7:(10*8)]<= State[4] ^ State_Mulx2[5] ^ State_Mulx3[6] ^ State[7];
57
    data_out[(9*8)+7:(9*8)] <=  State[4] ^ State[5] ^ State_Mulx2[6] ^ State_Mulx3[7];
58
    data_out[(8*8)+7:(8*8)]<= State_Mulx3[4] ^ State[5] ^ State[6] ^ State_Mulx2[7];
59
    /**********************************************************************************/
60
    data_out[(7*8)+7:(7*8)]<= State_Mulx2[8] ^ State_Mulx3[9] ^ State[10] ^ State[11];   //third column
61
    data_out[(6*8)+7:(6*8)]<= State[8] ^ State_Mulx2[9] ^ State_Mulx3[10] ^ State[11];
62
    data_out[(5*8)+7:(5*8)]<= State[8] ^ State[9] ^ State_Mulx2[10] ^ State_Mulx3[11];
63
    data_out[(4*8)+7:(4*8)]<= State_Mulx3[8] ^ State[9] ^ State[10] ^ State_Mulx2[11];
64
    /***********************************************************************************/
65
    data_out[(3*8)+7:(3*8)]<= State_Mulx2[12] ^ State_Mulx3[13] ^ State[14] ^ State[15];  //fourth column
66
    data_out[(2*8)+7:(2*8)]<= State[12] ^ State_Mulx2[13] ^ State_Mulx3[14] ^ State[15];
67
    data_out[(1*8)+7:(1*8)]<= State[12] ^ State[13] ^ State_Mulx2[14] ^ State_Mulx3[15];
68
    data_out[(0*8)+7:(0*8)]<= State_Mulx3[12] ^ State[13] ^ State[14] ^ State_Mulx2[15];
69
   end
70
   valid_out <= valid_in;
71
end
72
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.