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[/] [aes-128_pipelined_encryption/] [trunk/] [rtl/] [RoundKeyGen.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Amr_Salah
/*
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Project        : AES
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Standard doc.  : FIPS 197
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Module name    : RoundKeyGen block
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Dependancy     :
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Design doc.    :
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References     :
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Description    : This module is used to perform the process
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                 of round key generation from input key
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                                 this module is the basic block of key expantion module
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Owner          : Amr Salah
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*/
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`timescale 1 ns/1 ps
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module RoundKeyGen
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#
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(
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parameter KEY_L = 128,     //key length
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parameter WORD = 32        //a parameter to represent WORD  = 4 bytes = 32 bit
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)
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(
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input clk,                           //system clk
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input reset,                         //asynch active low reset
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input [WORD-1:0] RCON_Word,          //round constant word       
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input valid_in,                      //input valid signal
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input [KEY_L-1:0] key,               //input key
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output reg [KEY_L-1:0]round_key,     //round key
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output reg valid_out                 //output valid signal
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);
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wire [WORD-1:0] Key_RotWord;
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reg [KEY_L-1:0] Key_FirstStage;
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reg [KEY_L-1:0] Key_SecondStage;
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reg [KEY_L-1:0] round_key_delayed;
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reg  valid_FirstStage;
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reg  valid_round_key;
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wire [WORD-1:0] Key_SubBytes;
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wire  subbytes_valid_out;
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wire [KEY_L-1:0] temp_round_key;
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//The keygeneration stages should be balanced with the 4 round stages(SubBytes-ShiftRows-MixColumns-AddRoundKey)
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//in order to let the round key and the data meet at the same time in the AddRoundKey module
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/******************************************First Stage Register***********************************************************/
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always @(posedge clk or negedge reset)
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if(!reset)begin
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    valid_FirstStage <= 1'b0;
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    Key_FirstStage <= 'b0;
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end else begin
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 if(valid_in)begin
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    Key_FirstStage <= key;
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 end
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    valid_FirstStage <= valid_in;
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end
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/***********************************************Second Stage Register*******************************************************/
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always @(posedge clk or negedge reset)
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if(!reset)begin
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    Key_SecondStage <= 'b0;
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end else begin
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 if(valid_FirstStage)begin
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   Key_SecondStage <= Key_FirstStage;
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 end
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end
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/*******************************************************RotWord****************************************************************/
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assign Key_RotWord = {Key_FirstStage[WORD-9:0],Key_FirstStage[WORD-1:WORD-8]}; //rotation of the least word in key
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/**************************************************SubBytes (Parallel to second stage register)*******************************/
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//perform subbytes operation on the result word of rotword step
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SubBytes #(WORD) SUB_U (clk,reset,valid_FirstStage,Key_RotWord,subbytes_valid_out,Key_SubBytes);
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/***************************************************Round Key calculations ***********************************************/
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assign temp_round_key[4*WORD-1:3*WORD] =  Key_SecondStage[4*WORD-1:3*WORD]  ^ Key_SubBytes ^ RCON_Word;
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assign temp_round_key[3*WORD-1:2*WORD] = Key_SecondStage[3*WORD-1:2*WORD] ^ temp_round_key[4*WORD-1:3*WORD] ;
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assign temp_round_key[2*WORD-1:WORD] =  Key_SecondStage[2*WORD-1:WORD] ^   temp_round_key[3*WORD-1:2*WORD];
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assign temp_round_key[WORD-1:0] = Key_SecondStage[WORD-1:0] ^ temp_round_key[2*WORD-1:WORD];
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/***************************************************Roundkey Register (Third Stage)******************************************/
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always @(posedge clk or negedge reset)
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if(!reset)begin
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    round_key_delayed <= 'b0;
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    valid_round_key <= 1'b0;
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end else begin
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 if(subbytes_valid_out)begin
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    round_key_delayed <= temp_round_key;
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 end
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    valid_round_key <= subbytes_valid_out;
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end
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/****************************************Out Put Register (Fourth Stage)*********************************************/
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always @(posedge clk or negedge reset)
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if(!reset)begin
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   valid_out <= 1'b0;
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   round_key <= 'b0;
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end else begin
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 if(valid_round_key)begin
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   round_key <= round_key_delayed;
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 end
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   valid_out <= valid_round_key;
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end
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endmodule

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