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-- Organization: www.opendsp.pl
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-- Engineer: Jerzy Gbur
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--
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-- Create Date: 2006-05-13
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-- Design Name: aes
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-- Module Name: key_expansion
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-- Project Name: aes
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-- Target Device:
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-- Tool versions:
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-- Description:
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-- KEY_SIZE: 0 - 128
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-- 1 - 192
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-- 2 - 256
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library WORK;
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use WORK.aes_pkg.ALL;
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entity key_expansion is
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generic (
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KEY_SIZE : in integer range 0 to 2 := 2
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);
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port
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(
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KEY_I : in std_logic_vector(7 downto 0);
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VALID_KEY_I : in std_logic;
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CLK_I : in std_logic;
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RESET_I : in std_logic;
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CE_I : in std_logic;
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DONE_O : out std_logic;
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GET_KEY_I : in std_logic;
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KEY_NUMB_I : in std_logic_vector(5 downto 0);
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KEY_EXP_O : out std_logic_vector(31 downto 0)
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);
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end key_expansion;
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architecture Behavioral of key_expansion is
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type type_ROUND_TABLE is array (0 to 63) of std_logic_vector(31 downto 0);
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signal KEY_EXPAN0 : type_ROUND_TABLE;
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signal t_FORWARD_TABLE : type_SBOX;
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signal v_KEY32_IN : std_logic_vector(31 downto 0);
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signal i_ROUND : integer range 0 to 13;
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signal i_BYTE_CNTR4 : integer range 0 to 3;
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signal FF_VALID_KEY : std_logic;
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signal v_KEY_COL_IN0 : std_logic_vector(31 downto 0);
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signal v_KEY_COL_OUT0 : std_logic_vector(31 downto 0);
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signal v_TEMP_VECTOR : std_logic_vector(31 downto 0);
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signal i_FRW_ADD_RD0 : integer range 0 to 255;
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signal v_SUB_WORD : std_logic_vector(7 downto 0);
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signal SRAM_WREN0 : std_logic;
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signal i_SRAM_ADDR_WR0 : integer range 0 to 63;
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signal i_SRAM_ADDR_RD0 : integer range 0 to 63;
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signal i_EXTERN_ADDRESS : integer range 0 to 63;
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signal i_INTERN_ADDR_RD0 : integer range 0 to 63;
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signal v_CALCULATION_CNTR : std_logic_vector(7 downto 0);
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signal START_CALCULATION : std_logic;
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signal CALCULATION : std_logic;
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signal FF_GET_KEY : std_logic;
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begin
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t_FORWARD_TABLE <= c_SBOX_FRV;
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--****************************************************************************--
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--* Packetization for 32bit words from input *--
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--****************************************************************************--
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P0000:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if CE_I = '1' then
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FF_VALID_KEY <= VALID_KEY_I;
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if VALID_KEY_I = '0' then
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i_BYTE_CNTR4 <= 0;
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elsif VALID_KEY_I = '1' then
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if i_BYTE_CNTR4 = 0 then
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v_KEY32_IN(7 downto 0) <= KEY_I;
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elsif i_BYTE_CNTR4 = 1 then
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v_KEY32_IN(15 downto 8) <= KEY_I;
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elsif i_BYTE_CNTR4 = 2 then
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v_KEY32_IN(23 downto 16) <= KEY_I;
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elsif i_BYTE_CNTR4 = 3 then
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v_KEY32_IN(31 downto 24) <= KEY_I;
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end if;
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if i_BYTE_CNTR4 = 3 then
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i_BYTE_CNTR4 <= 0;
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else
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i_BYTE_CNTR4 <= i_BYTE_CNTR4 + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* RAM for Key Expansion *--
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--****************************************************************************--
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SRAM0:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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SRAM_WREN0 <= '0';
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elsif CE_I = '1' then
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if VALID_KEY_I = '1' and i_BYTE_CNTR4 = 3 then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"08" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"09" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"0A" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"0B" then
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SRAM_WREN0 <= '1';
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elsif KEY_SIZE = 1 then
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if v_CALCULATION_CNTR = x"0C" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"0D" then
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SRAM_WREN0 <= '1';
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else
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SRAM_WREN0 <= '0';
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end if;
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elsif KEY_SIZE = 2 then
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if v_CALCULATION_CNTR = x"11" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"12" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"13" then
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SRAM_WREN0 <= '1';
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elsif v_CALCULATION_CNTR = x"14" then
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SRAM_WREN0 <= '1';
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else
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SRAM_WREN0 <= '0';
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end if;
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else
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SRAM_WREN0 <= '0';
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end if;
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end if;
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-- RAM
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if CE_I = '1' then
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if SRAM_WREN0 = '1' then
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KEY_EXPAN0(i_SRAM_ADDR_WR0) <= v_KEY_COL_IN0;
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end if;
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v_KEY_COL_OUT0 <= KEY_EXPAN0(i_SRAM_ADDR_RD0);
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end if;
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-- Write address
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if RESET_I = '1' then
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i_SRAM_ADDR_WR0 <= 0;
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elsif CE_I = '1' then
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if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then
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i_SRAM_ADDR_WR0 <= 0;
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elsif SRAM_WREN0 = '1' then
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i_SRAM_ADDR_WR0 <= i_SRAM_ADDR_WR0 + 1;
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end if;
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end if;
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-- Read address
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if RESET_I = '1' then
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i_INTERN_ADDR_RD0 <= 0;
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elsif CE_I = '1' then
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if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then
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i_INTERN_ADDR_RD0 <= 0;
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elsif v_CALCULATION_CNTR = x"07" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"08" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"09" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"0A" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif KEY_SIZE = 1 then
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if v_CALCULATION_CNTR = x"0B" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"0C" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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end if;
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elsif KEY_SIZE = 2 then
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if v_CALCULATION_CNTR = x"10" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"11" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"12" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"13" then
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i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
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end if;
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end if;
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end if;
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FF_GET_KEY <= GET_KEY_I;
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end if;
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end process;
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i_EXTERN_ADDRESS <= conv_integer(KEY_NUMB_I);
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i_SRAM_ADDR_RD0 <= i_INTERN_ADDR_RD0 when GET_KEY_I = '0' else i_EXTERN_ADDRESS;
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KEY_EXP_O <= v_KEY_COL_OUT0 when FF_GET_KEY = '1' else (others => '0');
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--****************************************************************************--
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--* ROM for Sub Word *--
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--****************************************************************************--
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i_FRW_ADD_RD0 <= conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"02" else
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conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"03" else
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conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"04" else
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conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"05" else
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conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 2 else
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conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 2 else
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conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 2 else
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conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"0F" and KEY_SIZE = 2 else
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0;
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ROM0:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if CE_I = '1' then
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v_SUB_WORD <= t_FORWARD_TABLE(i_FRW_ADD_RD0);
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* v_KEY_COL_IN0 *--
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--****************************************************************************--
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v_KEY_COL_IN0 <= v_KEY32_IN when FF_VALID_KEY = '1' and i_BYTE_CNTR4 = 0 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"09" else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0A" else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0B" else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0C" else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 1 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"12" and KEY_SIZE = 2 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"13" and KEY_SIZE = 2 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"14" and KEY_SIZE = 2 else
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v_TEMP_VECTOR when v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 else
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(others => '0');
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--****************************************************************************--
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--* CALCULATION *--
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--****************************************************************************--
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P0002:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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START_CALCULATION <= '0';
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CALCULATION <= '0';
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DONE_O <= '0';
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elsif CE_I = '1' then
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if FF_VALID_KEY = '1' and VALID_KEY_I = '0' then
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START_CALCULATION <= '1';
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CALCULATION <= '1';
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DONE_O <= '0';
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elsif i_ROUND = 10 and KEY_SIZE = 0 then
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DONE_O <= '1';
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CALCULATION <= '0';
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elsif i_ROUND = 8 and KEY_SIZE = 1 then
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DONE_O <= '1';
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CALCULATION <= '0';
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elsif i_ROUND = 7 and KEY_SIZE = 2 then
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DONE_O <= '1';
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CALCULATION <= '0';
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else
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START_CALCULATION <= '0';
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end if;
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end if;
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end if;
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end process;
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P0003:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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v_CALCULATION_CNTR <= (others => '0');
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i_ROUND <= 0;
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elsif CE_I = '1' then
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if START_CALCULATION = '1' then
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v_CALCULATION_CNTR <= (others => '0');
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i_ROUND <= 0;
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elsif v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 0 then
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v_CALCULATION_CNTR <= (others => '0');
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i_ROUND <= i_ROUND + 1;
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elsif v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 then
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v_CALCULATION_CNTR <= (others => '0');
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i_ROUND <= i_ROUND + 1;
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|
|
elsif v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 then
|
331 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
332 |
|
|
i_ROUND <= i_ROUND + 1;
|
333 |
|
|
elsif CALCULATION = '1' then
|
334 |
|
|
v_CALCULATION_CNTR <= v_CALCULATION_CNTR + 1;
|
335 |
|
|
else
|
336 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
337 |
|
|
end if;
|
338 |
|
|
end if;
|
339 |
|
|
end if;
|
340 |
|
|
end process;
|
341 |
|
|
--****************************************************************************--
|
342 |
|
|
--* v_TEMP_VECTOR *--
|
343 |
|
|
--****************************************************************************--
|
344 |
|
|
P0:
|
345 |
|
|
process(CLK_I)
|
346 |
|
|
begin
|
347 |
|
|
if rising_edge(CLK_I) then
|
348 |
|
|
if RESET_I = '1' then
|
349 |
|
|
v_TEMP_VECTOR <= (others => '0');
|
350 |
|
|
elsif CE_I = '1' then
|
351 |
|
|
if START_CALCULATION = '1' then
|
352 |
|
|
v_TEMP_VECTOR <= v_KEY32_IN;
|
353 |
|
|
elsif v_CALCULATION_CNTR = x"03" then
|
354 |
|
|
v_TEMP_VECTOR(7 downto 0) <= v_SUB_WORD;
|
355 |
|
|
elsif v_CALCULATION_CNTR = x"04" then
|
356 |
|
|
v_TEMP_VECTOR(15 downto 8) <= v_SUB_WORD;
|
357 |
|
|
elsif v_CALCULATION_CNTR = x"05" then
|
358 |
|
|
v_TEMP_VECTOR(23 downto 16) <= v_SUB_WORD;
|
359 |
|
|
elsif v_CALCULATION_CNTR = x"06" then
|
360 |
|
|
v_TEMP_VECTOR(31 downto 24) <= v_SUB_WORD;
|
361 |
|
|
|
362 |
|
|
elsif v_CALCULATION_CNTR = x"07" then
|
363 |
|
|
v_TEMP_VECTOR <= (v_TEMP_VECTOR(7 downto 0) & v_TEMP_VECTOR(31 downto 8)) xor (x"000000" & c_RCON(i_ROUND));
|
364 |
|
|
elsif v_CALCULATION_CNTR = x"08" then
|
365 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
366 |
|
|
elsif v_CALCULATION_CNTR = x"09" then
|
367 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
368 |
|
|
elsif v_CALCULATION_CNTR = x"0A" then
|
369 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
370 |
|
|
elsif v_CALCULATION_CNTR = x"0B" then
|
371 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
372 |
|
|
elsif KEY_SIZE = 1 then
|
373 |
|
|
if v_CALCULATION_CNTR = x"0C" then
|
374 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
375 |
|
|
elsif v_CALCULATION_CNTR = x"0D" then
|
376 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
377 |
|
|
end if;
|
378 |
|
|
elsif KEY_SIZE = 2 then
|
379 |
|
|
|
380 |
|
|
if v_CALCULATION_CNTR = x"0D" then
|
381 |
|
|
v_TEMP_VECTOR(7 downto 0) <= v_SUB_WORD;
|
382 |
|
|
elsif v_CALCULATION_CNTR = x"0E" then
|
383 |
|
|
v_TEMP_VECTOR(15 downto 8) <= v_SUB_WORD;
|
384 |
|
|
elsif v_CALCULATION_CNTR = x"0F" then
|
385 |
|
|
v_TEMP_VECTOR(23 downto 16) <= v_SUB_WORD;
|
386 |
|
|
elsif v_CALCULATION_CNTR = x"10" then
|
387 |
|
|
v_TEMP_VECTOR(31 downto 24) <= v_SUB_WORD;
|
388 |
|
|
|
389 |
|
|
elsif v_CALCULATION_CNTR = x"11" then
|
390 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
391 |
|
|
elsif v_CALCULATION_CNTR = x"12" then
|
392 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
393 |
|
|
elsif v_CALCULATION_CNTR = x"13" then
|
394 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
395 |
|
|
elsif v_CALCULATION_CNTR = x"14" then
|
396 |
|
|
v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
|
397 |
|
|
end if;
|
398 |
|
|
|
399 |
|
|
end if;
|
400 |
|
|
end if;
|
401 |
|
|
end if;
|
402 |
|
|
end process;
|
403 |
|
|
|
404 |
|
|
end Behavioral;
|