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hemanth |
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| 2 |
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| 3 |
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| 4 |
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Clock Frequency Report
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| 5 |
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| 6 |
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Clock : Frequency
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| 7 |
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------------------------------------
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| 8 |
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| 9 |
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clk : 101.3 MHz
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| 10 |
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| 11 |
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| 12 |
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Critical Path Report
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| 13 |
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| 14 |
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| 15 |
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Critical path #1, (path slack = 0.1):
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| 16 |
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| 17 |
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NAME GATE ARRIVAL LOAD
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--------------------------------------------------------------------------------------------
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| 19 |
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clock information not specified
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| 20 |
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delay thru clock network 0.00 (ideal)
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| 21 |
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| 22 |
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| 23 |
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reg_s3_buf(1)(3)/Q FDC 0.00 0.53 up 1.50
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| 24 |
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ix36548_ix910/O LUT4 0.72 1.25 up 0.50
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| 25 |
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ix36548_ix913/O MUXF5 0.38 1.63 up 0.50
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| 26 |
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ix36548_ix919/O MUXF6 0.24 1.86 up 0.50
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| 27 |
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ix36548_ix933/O MUXF7 0.24 2.10 up 0.50
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| 28 |
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ix36548_ix963/O MUXF8 0.24 2.34 up 0.80
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| 29 |
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r_02(1)(6)/O LUT3 0.72 3.06 up 1.00
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| 30 |
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nx14310/O LUT4 0.72 3.78 up 0.60
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| 31 |
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modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50
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| 32 |
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a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00
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| 33 |
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modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50
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| 34 |
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modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50
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| 35 |
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nx40772/O LUT3 0.72 7.37 up 0.50
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| 36 |
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next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60
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| 37 |
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nx27520/O LUT4 0.72 8.81 up 0.60
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| 38 |
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reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00
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| 39 |
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data arrival time 8.81
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| 40 |
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| 41 |
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| 42 |
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data required time (default specified - setup time) 8.94
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| 43 |
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--------------------------------------------------------------------------------------------
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| 44 |
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data required time 8.94
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| 45 |
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data arrival time 8.81
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| 46 |
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----------
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| 47 |
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slack 0.13
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| 48 |
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--------------------------------------------------------------------------------------------
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| 49 |
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| 50 |
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| 51 |
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| 52 |
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| 53 |
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Critical path #2, (path slack = 0.1):
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| 54 |
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| 55 |
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NAME GATE ARRIVAL LOAD
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| 56 |
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--------------------------------------------------------------------------------------------
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| 57 |
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clock information not specified
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| 58 |
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delay thru clock network 0.00 (ideal)
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| 59 |
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| 60 |
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| 61 |
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reg_s3_buf(1)(2)/Q FDC 0.00 0.53 up 1.50
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| 62 |
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ix36548_ix910/O LUT4 0.72 1.25 up 0.50
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| 63 |
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ix36548_ix913/O MUXF5 0.38 1.63 up 0.50
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| 64 |
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ix36548_ix919/O MUXF6 0.24 1.86 up 0.50
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| 65 |
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ix36548_ix933/O MUXF7 0.24 2.10 up 0.50
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| 66 |
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ix36548_ix963/O MUXF8 0.24 2.34 up 0.80
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| 67 |
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r_02(1)(6)/O LUT3 0.72 3.06 up 1.00
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| 68 |
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nx14310/O LUT4 0.72 3.78 up 0.60
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| 69 |
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modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50
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| 70 |
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a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00
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| 71 |
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modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50
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| 72 |
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modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50
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| 73 |
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nx40772/O LUT3 0.72 7.37 up 0.50
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| 74 |
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next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60
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| 75 |
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nx27520/O LUT4 0.72 8.81 up 0.60
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| 76 |
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reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00
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| 77 |
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data arrival time 8.81
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| 78 |
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| 79 |
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| 80 |
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data required time (default specified - setup time) 8.94
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| 81 |
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--------------------------------------------------------------------------------------------
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| 82 |
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data required time 8.94
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| 83 |
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data arrival time 8.81
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| 84 |
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----------
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| 85 |
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slack 0.13
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| 86 |
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--------------------------------------------------------------------------------------------
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| 87 |
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| 88 |
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| 89 |
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| 90 |
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| 91 |
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Critical path #3, (path slack = 0.1):
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| 92 |
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| 93 |
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NAME GATE ARRIVAL LOAD
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| 94 |
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--------------------------------------------------------------------------------------------
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| 95 |
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clock information not specified
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| 96 |
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delay thru clock network 0.00 (ideal)
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| 97 |
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| 98 |
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| 99 |
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reg_s3_buf(1)(1)/Q FDC 0.00 0.53 up 1.50
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| 100 |
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ix36548_ix910/O LUT4 0.72 1.25 up 0.50
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| 101 |
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ix36548_ix913/O MUXF5 0.38 1.63 up 0.50
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| 102 |
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ix36548_ix919/O MUXF6 0.24 1.86 up 0.50
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| 103 |
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ix36548_ix933/O MUXF7 0.24 2.10 up 0.50
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| 104 |
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ix36548_ix963/O MUXF8 0.24 2.34 up 0.80
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| 105 |
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r_02(1)(6)/O LUT3 0.72 3.06 up 1.00
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| 106 |
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nx14310/O LUT4 0.72 3.78 up 0.60
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| 107 |
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modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50
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| 108 |
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a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00
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| 109 |
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modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50
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| 110 |
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modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50
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| 111 |
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nx40772/O LUT3 0.72 7.37 up 0.50
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| 112 |
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next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60
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| 113 |
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nx27520/O LUT4 0.72 8.81 up 0.60
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| 114 |
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reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00
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| 115 |
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data arrival time 8.81
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| 116 |
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| 117 |
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| 118 |
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data required time (default specified - setup time) 8.94
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| 119 |
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--------------------------------------------------------------------------------------------
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| 120 |
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data required time 8.94
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| 121 |
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data arrival time 8.81
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| 122 |
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----------
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| 123 |
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slack 0.13
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| 124 |
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--------------------------------------------------------------------------------------------
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| 125 |
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| 126 |
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| 127 |
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| 128 |
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| 129 |
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Critical path #4, (path slack = 0.1):
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| 130 |
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| 131 |
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NAME GATE ARRIVAL LOAD
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| 132 |
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--------------------------------------------------------------------------------------------
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| 133 |
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clock information not specified
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| 134 |
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delay thru clock network 0.00 (ideal)
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| 135 |
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| 136 |
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| 137 |
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reg_s3_buf(1)(0)/Q FDC 0.00 0.53 up 1.50
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| 138 |
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ix36548_ix910/O LUT4 0.72 1.25 up 0.50
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| 139 |
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ix36548_ix913/O MUXF5 0.38 1.63 up 0.50
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| 140 |
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ix36548_ix919/O MUXF6 0.24 1.86 up 0.50
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| 141 |
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ix36548_ix933/O MUXF7 0.24 2.10 up 0.50
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| 142 |
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ix36548_ix963/O MUXF8 0.24 2.34 up 0.80
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| 143 |
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r_02(1)(6)/O LUT3 0.72 3.06 up 1.00
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| 144 |
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nx14310/O LUT4 0.72 3.78 up 0.60
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| 145 |
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modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50
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| 146 |
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a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00
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| 147 |
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modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50
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| 148 |
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modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50
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| 149 |
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nx40772/O LUT3 0.72 7.37 up 0.50
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| 150 |
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next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60
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| 151 |
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nx27520/O LUT4 0.72 8.81 up 0.60
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| 152 |
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reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00
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| 153 |
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data arrival time 8.81
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| 154 |
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| 155 |
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| 156 |
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data required time (default specified - setup time) 8.94
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| 157 |
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--------------------------------------------------------------------------------------------
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| 158 |
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data required time 8.94
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| 159 |
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data arrival time 8.81
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| 160 |
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----------
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| 161 |
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slack 0.13
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| 162 |
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--------------------------------------------------------------------------------------------
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| 163 |
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| 164 |
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