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hemanth |
--*************************************************************************
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-- Project : AES128 *
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-- *
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-- Block Name : aes128_fast.vhd *
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-- *
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-- Author : Hemanth Satyanarayana *
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-- *
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-- Email : hemanth@opencores.org *
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-- *
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-- Description: This is the top level module for the aes core. *
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-- It instantiates the key expander and uses the *
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-- aes package for other transformations. *
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-- Implementation is ECB mode. *
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-- *
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-- Revision History *
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Name | Date | Version | Revision details |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Hemanth | 15-Dec-2004 | 1.1.1.1 | Uploaded |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- *
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-- Refer FIPS-197 document for details *
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--*************************************************************************
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-- *
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-- Copyright (C) 2004 Author *
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-- *
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-- This source file may be used and distributed without *
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-- restriction provided that this copyright statement is not *
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-- removed from the file and that any derivative work contains *
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-- the original copyright notice and the associated disclaimer. *
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-- *
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-- This source file is free software; you can redistribute it *
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-- and/or modify it under the terms of the GNU Lesser General *
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-- Public License as published by the Free Software Foundation; *
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-- either version 2.1 of the License, or (at your option) any *
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-- later version. *
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-- *
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-- This source is distributed in the hope that it will be *
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-- useful, but WITHOUT ANY WARRANTY; without even the implied *
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
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-- PURPOSE. See the GNU Lesser General Public License for more *
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-- details. *
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-- *
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-- You should have received a copy of the GNU Lesser General *
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-- Public License along with this source; if not, download it *
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-- from http://www.opencores.org/lgpl.shtml *
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-- *
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--*************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.aes_package.all;
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entity aes128_fast is
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port(
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic; -- to initiate the encryption/decryption process after loading
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mode : in std_logic; -- to select encryption or decryption
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load : in std_logic; -- to load the input and keys.has to
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key : in std_logic_vector(63 downto 0);
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data_in : in std_logic_vector(63 downto 0);
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data_out : out std_logic_vector(127 downto 0);
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done : out std_logic
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);
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end aes128_fast;
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architecture mapping of aes128_fast is
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component key_expander
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port(
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clk : in std_logic;
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reset : in std_logic;
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key_in_c0: in state_array_type;
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key_in_c1: in state_array_type;
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key_in_c2: in state_array_type;
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key_in_c3: in state_array_type;
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count : in integer;
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mode : in std_logic;
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keyout_c0: out state_array_type;
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keyout_c1: out state_array_type;
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keyout_c2: out state_array_type;
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keyout_c3: out state_array_type
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);
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end component;
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signal data_in_reg0: state_array_type;
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signal data_in_reg1: state_array_type;
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signal data_in_reg2: state_array_type;
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signal data_in_reg3: state_array_type;
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signal key_reg0: state_array_type;
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signal key_reg1: state_array_type;
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signal key_reg2: state_array_type;
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signal key_reg3: state_array_type;
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signal s0 : state_array_type;
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signal s1 : state_array_type;
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signal s2 : state_array_type;
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signal s3 : state_array_type;
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signal s_00 : state_array_type;
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signal s_01 : state_array_type;
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signal s_02 : state_array_type;
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signal s_03 : state_array_type;
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signal r_00 : state_array_type;
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signal r_01 : state_array_type;
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signal r_02 : state_array_type;
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signal r_03 : state_array_type;
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signal load_d1 : std_logic;
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signal start_d1: std_logic;
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signal start_d2: std_logic;
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signal round_cnt: integer range 0 to 15;
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signal flag_cnt: std_logic;
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signal done_d1 : std_logic;
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signal done_d2 : std_logic;
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signal mixcol_0: state_array_type;
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signal mixcol_1: state_array_type;
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signal mixcol_2: state_array_type;
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signal mixcol_3: state_array_type;
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signal new_key0: state_array_type;
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signal new_key1: state_array_type;
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signal new_key2: state_array_type;
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signal new_key3: state_array_type;
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signal new_key0_d1: state_array_type;
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signal new_key1_d1: state_array_type;
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signal new_key2_d1: state_array_type;
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signal new_key3_d1: state_array_type;
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signal s0_buf : state_array_type;
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signal s1_buf : state_array_type;
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signal s2_buf : state_array_type;
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signal s3_buf : state_array_type;
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signal next_round_data_0: state_array_type;
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signal next_round_data_1: state_array_type;
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signal next_round_data_2: state_array_type;
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signal next_round_data_3: state_array_type;
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signal pr_data_0: state_array_type;
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signal pr_data_1: state_array_type;
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signal pr_data_2: state_array_type;
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signal pr_data_3: state_array_type;
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signal mix_col_array : std_logic_vector(0 to 127);
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signal mixcol_key_array: std_logic_vector(0 to 127);
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signal mixcol_key_0 : state_array_type;
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signal mixcol_key_1 : state_array_type;
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signal mixcol_key_2 : state_array_type;
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signal mixcol_key_3 : state_array_type;
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signal key_select_0 : state_array_type;
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signal key_select_1 : state_array_type;
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signal key_select_2 : state_array_type;
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signal key_select_3 : state_array_type;
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begin
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-- Loading the data and keys
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process(clk,reset)
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begin
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if(reset = '1') then
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key_reg0 <= (others =>(others => '0'));
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key_reg1 <= (others =>(others => '0'));
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key_reg2 <= (others =>(others => '0'));
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key_reg3 <= (others =>(others => '0'));
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data_in_reg0 <= (others =>(others => '0'));
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data_in_reg1 <= (others =>(others => '0'));
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data_in_reg2 <= (others =>(others => '0'));
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data_in_reg3 <= (others =>(others => '0'));
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elsif rising_edge(clk) then
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if(load = '1' and load_d1 = '0') then
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key_reg0 <= (key(63 downto 56),key(55 downto 48),key(47 downto 40),key(39 downto 32));
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key_reg1 <= (key(31 downto 24),key(23 downto 16),key(15 downto 8),key(7 downto 0));
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data_in_reg0 <= (data_in(63 downto 56),data_in(55 downto 48),data_in(47 downto 40),data_in(39 downto 32));
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data_in_reg1 <= (data_in(31 downto 24),data_in(23 downto 16),data_in(15 downto 8),data_in(7 downto 0));
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elsif(load_d1 = '1' and load = '0') then
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key_reg2 <= (key(63 downto 56),key(55 downto 48),key(47 downto 40),key(39 downto 32));
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key_reg3 <= (key(31 downto 24),key(23 downto 16),key(15 downto 8),key(7 downto 0));
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data_in_reg2 <= (data_in(63 downto 56),data_in(55 downto 48),data_in(47 downto 40),data_in(39 downto 32));
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data_in_reg3 <= (data_in(31 downto 24),data_in(23 downto 16),data_in(15 downto 8),data_in(7 downto 0));
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end if;
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end if;
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end process;
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----------STATE MATRIX ROW WORDS ------
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-- Given input xored with given key for generating input to the first round
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s0(0) <= data_in_reg0(0) xor key_reg0(0);
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s0(1) <= data_in_reg0(1) xor key_reg0(1);
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s0(2) <= data_in_reg0(2) xor key_reg0(2);
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s0(3) <= data_in_reg0(3) xor key_reg0(3);
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s1(0) <= data_in_reg1(0) xor key_reg1(0);
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s1(1) <= data_in_reg1(1) xor key_reg1(1);
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s1(2) <= data_in_reg1(2) xor key_reg1(2);
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s1(3) <= data_in_reg1(3) xor key_reg1(3);
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s2(0) <= data_in_reg2(0) xor key_reg2(0);
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s2(1) <= data_in_reg2(1) xor key_reg2(1);
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s2(2) <= data_in_reg2(2) xor key_reg2(2);
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s2(3) <= data_in_reg2(3) xor key_reg2(3);
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s3(0) <= data_in_reg3(0) xor key_reg3(0);
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s3(1) <= data_in_reg3(1) xor key_reg3(1);
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s3(2) <= data_in_reg3(2) xor key_reg3(2);
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s3(3) <= data_in_reg3(3) xor key_reg3(3);
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-----------------SUB BYTES TRANSFORMATION--------------------------------------
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process(s0_buf,s1_buf,s2_buf,s3_buf,mode)
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begin
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if(mode = '1') then
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s_00(0) <= sbox_val(s0_buf(0));
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s_00(1) <= sbox_val(s0_buf(1));
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s_00(2) <= sbox_val(s0_buf(2));
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s_00(3) <= sbox_val(s0_buf(3));
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s_01(0) <= sbox_val(s1_buf(0));
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s_01(1) <= sbox_val(s1_buf(1));
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s_01(2) <= sbox_val(s1_buf(2));
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s_01(3) <= sbox_val(s1_buf(3));
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s_02(0) <= sbox_val(s2_buf(0));
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s_02(1) <= sbox_val(s2_buf(1));
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s_02(2) <= sbox_val(s2_buf(2));
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s_02(3) <= sbox_val(s2_buf(3));
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s_03(0) <= sbox_val(s3_buf(0));
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s_03(1) <= sbox_val(s3_buf(1));
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s_03(2) <= sbox_val(s3_buf(2));
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s_03(3) <= sbox_val(s3_buf(3));
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else
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s_00(0) <= inv_sbox_val(s0_buf(0));
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s_00(1) <= inv_sbox_val(s0_buf(1));
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s_00(2) <= inv_sbox_val(s0_buf(2));
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s_00(3) <= inv_sbox_val(s0_buf(3));
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s_01(0) <= inv_sbox_val(s1_buf(0));
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s_01(1) <= inv_sbox_val(s1_buf(1));
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s_01(2) <= inv_sbox_val(s1_buf(2));
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s_01(3) <= inv_sbox_val(s1_buf(3));
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s_02(0) <= inv_sbox_val(s2_buf(0));
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s_02(1) <= inv_sbox_val(s2_buf(1));
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s_02(2) <= inv_sbox_val(s2_buf(2));
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s_02(3) <= inv_sbox_val(s2_buf(3));
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s_03(0) <= inv_sbox_val(s3_buf(0));
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s_03(1) <= inv_sbox_val(s3_buf(1));
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s_03(2) <= inv_sbox_val(s3_buf(2));
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s_03(3) <= inv_sbox_val(s3_buf(3));
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end if;
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end process;
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-----------SHIFT ROWS TRANSFORMATION--------------------------------------
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process(s_00,s_01,s_02,s_03,mode)
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begin
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if(mode = '1') then
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r_00 <= (s_00(0),s_01(1),s_02(2),s_03(3));
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r_01 <= (s_01(0),s_02(1),s_03(2),s_00(3));
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r_02 <= (s_02(0),s_03(1),s_00(2),s_01(3));
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r_03 <= (s_03(0),s_00(1),s_01(2),s_02(3));
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else
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r_00 <= (s_00(0),s_03(1),s_02(2),s_01(3));
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r_01 <= (s_01(0),s_00(1),s_03(2),s_02(3));
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r_02 <= (s_02(0),s_01(1),s_00(2),s_03(3));
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r_03 <= (s_03(0),s_02(1),s_01(2),s_00(3));
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end if;
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end process;
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-----------MIX COLUMNS TRANSFORMATION--------------------------------------
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mix_col_array <= mix_cols_routine(r_00,r_01,r_02,r_03,mode);
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mixcol_0 <= (mix_col_array(0 to 7),mix_col_array(8 to 15),mix_col_array(16 to 23),mix_col_array(24 to 31));
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mixcol_1 <= (mix_col_array(32 to 39),mix_col_array(40 to 47),mix_col_array(48 to 55),mix_col_array(56 to 63));
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mixcol_2 <= (mix_col_array(64 to 71),mix_col_array(72 to 79),mix_col_array(80 to 87),mix_col_array(88 to 95));
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mixcol_3 <= (mix_col_array(96 to 103),mix_col_array(104 to 111),mix_col_array(112 to 119),mix_col_array(120 to 127));
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mixcol_key_array <= mix_cols_routine(new_key0_d1,new_key1_d1,new_key2_d1,new_key3_d1,mode);
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mixcol_key_0 <= (mixcol_key_array(0 to 7),mixcol_key_array(8 to 15),mixcol_key_array(16 to 23),mixcol_key_array(24 to 31));
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mixcol_key_1 <= (mixcol_key_array(32 to 39),mixcol_key_array(40 to 47),mixcol_key_array(48 to 55),mixcol_key_array(56 to 63));
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mixcol_key_2 <= (mixcol_key_array(64 to 71),mixcol_key_array(72 to 79),mixcol_key_array(80 to 87),mixcol_key_array(88 to 95));
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mixcol_key_3 <= (mixcol_key_array(96 to 103),mixcol_key_array(104 to 111),mixcol_key_array(112 to 119),mixcol_key_array(120 to 127));
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---------ADD ROUND KEY STEP-------------------------------------------------
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expand_key: key_expander
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port map(
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clk => clk,
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reset => reset,
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key_in_c0 => key_reg0,
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key_in_c1 => key_reg1,
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key_in_c2 => key_reg2,
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288 |
|
|
key_in_c3 => key_reg3,
|
289 |
|
|
count => round_cnt,
|
290 |
|
|
mode => mode,
|
291 |
|
|
keyout_c0 => new_key0,
|
292 |
|
|
keyout_c1 => new_key1,
|
293 |
|
|
keyout_c2 => new_key2,
|
294 |
|
|
keyout_c3 => new_key3
|
295 |
|
|
);
|
296 |
|
|
|
297 |
|
|
process(clk,reset) ---- registered to increase speed
|
298 |
|
|
begin
|
299 |
|
|
if(reset = '1') then
|
300 |
|
|
new_key0_d1 <= (others =>(others => '0'));
|
301 |
|
|
new_key1_d1 <= (others =>(others => '0'));
|
302 |
|
|
new_key2_d1 <= (others =>(others => '0'));
|
303 |
|
|
new_key3_d1 <= (others =>(others => '0'));
|
304 |
|
|
elsif rising_edge(clk) then
|
305 |
|
|
new_key0_d1 <= new_key0;
|
306 |
|
|
new_key1_d1 <= new_key1;
|
307 |
|
|
new_key2_d1 <= new_key2;
|
308 |
|
|
new_key3_d1 <= new_key3;
|
309 |
|
|
end if;
|
310 |
|
|
end process;
|
311 |
|
|
|
312 |
|
|
-- Previous round output as input to next round
|
313 |
|
|
next_round_data_0 <= (pr_data_0(0) xor key_select_0(0),pr_data_0(1) xor key_select_0(1),pr_data_0(2) xor key_select_0(2),pr_data_0(3) xor key_select_0(3));
|
314 |
|
|
next_round_data_1 <= (pr_data_1(0) xor key_select_1(0),pr_data_1(1) xor key_select_1(1),pr_data_1(2) xor key_select_1(2),pr_data_1(3) xor key_select_1(3));
|
315 |
|
|
next_round_data_2 <= (pr_data_2(0) xor key_select_2(0),pr_data_2(1) xor key_select_2(1),pr_data_2(2) xor key_select_2(2),pr_data_2(3) xor key_select_2(3));
|
316 |
|
|
next_round_data_3 <= (pr_data_3(0) xor key_select_3(0),pr_data_3(1) xor key_select_3(1),pr_data_3(2) xor key_select_3(2),pr_data_3(3) xor key_select_3(3));
|
317 |
|
|
|
318 |
|
|
-- Muxing for choosing data for the last round
|
319 |
|
|
pr_data_0 <= r_00 when round_cnt=11 else
|
320 |
|
|
mixcol_0;
|
321 |
|
|
pr_data_1 <= r_01 when round_cnt=11 else
|
322 |
|
|
mixcol_1;
|
323 |
|
|
pr_data_2 <= r_02 when round_cnt=11 else
|
324 |
|
|
mixcol_2;
|
325 |
|
|
pr_data_3 <= r_03 when round_cnt=11 else
|
326 |
|
|
mixcol_3;
|
327 |
|
|
|
328 |
|
|
key_select_0 <= new_key0_d1 when (mode = '1') else
|
329 |
|
|
mixcol_key_0 when(mode = '0' and round_cnt < 11) else
|
330 |
|
|
new_key0_d1;
|
331 |
|
|
key_select_1 <= new_key1_d1 when (mode = '1') else
|
332 |
|
|
mixcol_key_1 when(mode = '0' and round_cnt < 11) else
|
333 |
|
|
new_key1_d1;
|
334 |
|
|
key_select_2 <= new_key2_d1 when (mode = '1') else
|
335 |
|
|
mixcol_key_2 when(mode = '0' and round_cnt < 11) else
|
336 |
|
|
new_key2_d1;
|
337 |
|
|
key_select_3 <= new_key3_d1 when (mode = '1') else
|
338 |
|
|
mixcol_key_3 when(mode = '0' and round_cnt < 11) else
|
339 |
|
|
new_key3_d1;
|
340 |
|
|
done <= done_d2;
|
341 |
|
|
|
342 |
|
|
-- Registering start and load
|
343 |
|
|
process(clk,reset)
|
344 |
|
|
begin
|
345 |
|
|
if(reset = '1') then
|
346 |
|
|
load_d1 <= '0';
|
347 |
|
|
start_d1 <= '0';
|
348 |
|
|
start_d2 <= '0';
|
349 |
|
|
elsif rising_edge(clk) then
|
350 |
|
|
load_d1 <= load;
|
351 |
|
|
start_d1 <= start;
|
352 |
|
|
start_d2 <= start_d1;
|
353 |
|
|
end if;
|
354 |
|
|
end process;
|
355 |
|
|
|
356 |
|
|
-- Register outputs at end of each round
|
357 |
|
|
process(clk,reset)
|
358 |
|
|
begin
|
359 |
|
|
if(reset = '1') then
|
360 |
|
|
s0_buf <= (others =>(others => '0'));
|
361 |
|
|
s1_buf <= (others =>(others => '0'));
|
362 |
|
|
s2_buf <= (others =>(others => '0'));
|
363 |
|
|
s3_buf <= (others =>(others => '0'));
|
364 |
|
|
elsif rising_edge(clk) then
|
365 |
|
|
if(round_cnt = 0 or round_cnt = 1) then
|
366 |
|
|
s0_buf <= s0;
|
367 |
|
|
s1_buf <= s1;
|
368 |
|
|
s2_buf <= s2;
|
369 |
|
|
s3_buf <= s3;
|
370 |
|
|
else
|
371 |
|
|
s0_buf <= next_round_data_0;
|
372 |
|
|
s1_buf <= next_round_data_1;
|
373 |
|
|
s2_buf <= next_round_data_2;
|
374 |
|
|
s3_buf <= next_round_data_3;
|
375 |
|
|
end if;
|
376 |
|
|
end if;
|
377 |
|
|
end process;
|
378 |
|
|
|
379 |
|
|
-- Initiator process
|
380 |
|
|
process(clk,reset)
|
381 |
|
|
begin
|
382 |
|
|
if(reset = '1') then
|
383 |
|
|
round_cnt <= 0;
|
384 |
|
|
flag_cnt <= '0';
|
385 |
|
|
elsif rising_edge(clk) then
|
386 |
|
|
if((start_d2 = '1' and start_d1 = '0') or flag_cnt = '1') then
|
387 |
|
|
if(round_cnt < 11) then
|
388 |
|
|
round_cnt <= round_cnt + 1;
|
389 |
|
|
flag_cnt <= '1';
|
390 |
|
|
else
|
391 |
|
|
round_cnt <= 0;
|
392 |
|
|
flag_cnt <= '0';
|
393 |
|
|
end if;
|
394 |
|
|
end if;
|
395 |
|
|
end if;
|
396 |
|
|
end process;
|
397 |
|
|
|
398 |
|
|
-- Completion signalling process
|
399 |
|
|
process(clk,reset)
|
400 |
|
|
begin
|
401 |
|
|
if(reset = '1') then
|
402 |
|
|
done_d1 <= '0';
|
403 |
|
|
done_d2 <= '0';
|
404 |
|
|
elsif rising_edge(clk) then
|
405 |
|
|
if(start_d2 = '1' and start_d1 = '0') then
|
406 |
|
|
done_d1 <= '0';
|
407 |
|
|
done_d2 <= '0';
|
408 |
|
|
elsif(round_cnt = 10) then
|
409 |
|
|
done_d1 <= '1';
|
410 |
|
|
end if;
|
411 |
|
|
done_d2 <= done_d1;
|
412 |
|
|
end if;
|
413 |
|
|
end process;
|
414 |
|
|
|
415 |
|
|
-- Output assignment process
|
416 |
|
|
process(clk,reset)
|
417 |
|
|
begin
|
418 |
|
|
if(reset= '1') then
|
419 |
|
|
data_out <= (others => '0');
|
420 |
|
|
elsif rising_edge(clk) then
|
421 |
|
|
if(done_d1 = '1' and done_d2 = '0') then
|
422 |
|
|
data_out <= (next_round_data_0(0) & next_round_data_0(1) & next_round_data_0(2) & next_round_data_0(3) &
|
423 |
|
|
next_round_data_1(0) & next_round_data_1(1) & next_round_data_1(2) & next_round_data_1(3) &
|
424 |
|
|
next_round_data_2(0) & next_round_data_2(1) & next_round_data_2(2) & next_round_data_2(3) &
|
425 |
|
|
next_round_data_3(0) & next_round_data_3(1) & next_round_data_3(2) & next_round_data_3(3));
|
426 |
|
|
end if;
|
427 |
|
|
end if;
|
428 |
|
|
end process;
|
429 |
|
|
|
430 |
|
|
end mapping;
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
|