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ghegde |
--************************************************************
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--Copyright 2015, Ganesh Hegde < ghegde@opencores.org >
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--
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--This source file may be used and distributed without
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--restriction provided that this copyright statement is not
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--removed from the file and that any derivative work contains
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--the original copyright notice and the associated disclaimer.
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--
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--This source is distributed in the hope that it will be
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--useful, but WITHOUT ANY WARRANTY; without even the implied
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--warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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--PURPOSE. See the GNU Lesser General Public License for more
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--details.
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--
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--You should have received a copy of the GNU Lesser General
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--Public License along with this source; if not, download it
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--from http://www.opencores.org/lgpl.shtml
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--
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--*************************************************************
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--*************************************************************
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--Top level entity for AES decryption IP.
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--*************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity AES_decrypter is
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port(
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cipher: in std_logic_vector(127 downto 0); --Cipher text
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text_out: out std_logic_vector(127 downto 0); -- Decrypted output
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key: in std_logic_vector(127 downto 0); --Cipher Key
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k_valid,c_valid: in std_logic;--Asserted when either key, cipher is valid
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ready:out std_logic;--Asserted high when IP is ready to accept the data(key or Cipher)
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out_valid: out std_logic;--out_valid:Asserted high when decrypted cipher is on the bus.(IMP : **Output is valid only for one cycle)
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clk,reset: in std_logic
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);
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end AES_decrypter;
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architecture beh_AES_decrypter of AES_decrypter is
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component key_scheduler
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port(
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key_in : in std_logic_vector(127 downto 0);--Decryption Key
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key_out : out std_logic_vector(127 downto 0);
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valid_in : in std_logic;--Should be high when input key is valid
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key_ready : out std_logic;--Asserted high when key_scheduler generated all the keys
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round: in std_logic_vector(3 downto 0);--Which round key to access
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clk,reset: in std_logic
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);
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end component;
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component one_round_decrypt
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port(
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cipher : in std_logic_vector(127 downto 0);
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text_out: out std_logic_vector(127 downto 0);
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round_key: in std_logic_vector(127 downto 0)
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);
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end component;
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component InvSub_addRk
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port(
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state_in : in std_logic_vector(127 downto 0);
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state_out : out std_logic_vector(127 downto 0);
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key : in std_logic_vector(127 downto 0)
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);
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end component;
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type state is (IDLE,KEYGEN,GETKY0,ROUND,FINALR,DELAY);
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signal state_reg,state_n: state;
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signal round_reg:unsigned(3 downto 0);
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signal KS_key_ready:std_logic;
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signal KS_key_out:std_logic_vector(127 downto 0);
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signal KS_round:unsigned(3 downto 0);
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signal one_round_out:std_logic_vector(127 downto 0);
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signal cipher_reg,cipher_n,cipher_round0: std_logic_vector(127 downto 0);
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begin
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key_scheduler_inst:key_scheduler
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port map(key_in=>key,key_out=>KS_key_out,valid_in=>k_valid,key_ready=>KS_key_ready,round=>std_logic_vector(KS_round),clk=>clk,reset=>reset);
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one_round_decrypt_inst:one_round_decrypt
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port map(cipher=>cipher_reg,text_out=>one_round_out,round_key=>KS_key_out);
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InvSub_addRk_inst:InvSub_addRk
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port map(state_in=>cipher_reg,state_out=>text_out,key=>KS_key_out);
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--State register logic
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process(clk,reset)
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begin
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if(reset='1') then
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state_reg <= IDLE;
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round_reg<=(others=>'0');
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cipher_reg<=(others=>'0');
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elsif(clk ' event and clk='1') then
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state_reg <= state_n;
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round_reg<=KS_round+1;
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cipher_reg<=cipher_n;
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end if;
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end process;
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--Next state logic
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process(state_reg,c_valid,KS_key_ready,k_valid,round_reg)
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begin
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case state_reg is
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when IDLE =>
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if(k_valid='1') then
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state_n <= KEYGEN;
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else
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state_n <= IDLE;
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end if;
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when KEYGEN =>
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if(KS_key_ready='1') then
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state_n <= GETKY0;--Unnecessary delay here??????
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else
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state_n <= KEYGEN;
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end if;
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when GETKY0 =>
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if(c_valid='1') then
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state_n<=DELAY;
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else
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state_n<=GETKY0;
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end if;
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when DELAY =>
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state_n <= ROUND;
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when ROUND=>
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if(round_reg="1010") then
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state_n<=FINALR;
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else
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state_n<=ROUND;
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end if;
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when FINALR=>
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state_n<=GETKY0;
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end case;
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end process;
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cipher_round0 <= KS_key_out xor cipher;
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with state_reg select
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KS_round <= "0000" when GETKY0,
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round_reg when DELAY,
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round_reg when ROUND,
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"1010" when others;
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with state_reg select
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cipher_n <= cipher_round0 when DELAY,
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one_round_out when others;
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out_valid<='1' when state_reg=FINALR else
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'0';
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ready<='1' when state_reg=GETKY0 or state_reg=IDLE else
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'0' ;
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end beh_AES_decrypter;
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