1 |
4 |
ghegde |
--************************************************************
|
2 |
|
|
--Copyright 2015, Ganesh Hegde < ghegde@opencores.org >
|
3 |
|
|
--
|
4 |
|
|
--This source file may be used and distributed without
|
5 |
|
|
--restriction provided that this copyright statement is not
|
6 |
|
|
--removed from the file and that any derivative work contains
|
7 |
|
|
--the original copyright notice and the associated disclaimer.
|
8 |
|
|
--
|
9 |
|
|
--This source is distributed in the hope that it will be
|
10 |
|
|
--useful, but WITHOUT ANY WARRANTY; without even the implied
|
11 |
|
|
--warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
12 |
|
|
--PURPOSE. See the GNU Lesser General Public License for more
|
13 |
|
|
--details.
|
14 |
|
|
--
|
15 |
|
|
--You should have received a copy of the GNU Lesser General
|
16 |
|
|
--Public License along with this source; if not, download it
|
17 |
|
|
--from http://www.opencores.org/lgpl.shtml
|
18 |
|
|
--
|
19 |
|
|
--*************************************************************
|
20 |
|
|
|
21 |
|
|
--*************************************************************
|
22 |
|
|
-- First three round i.e Inv shift row, Inv Sub byte, Add round
|
23 |
|
|
-- key are performed.
|
24 |
|
|
--Logic type : Combinational
|
25 |
|
|
--*************************************************************
|
26 |
|
|
|
27 |
|
|
library ieee;
|
28 |
|
|
use ieee.std_logic_1164.all;
|
29 |
|
|
|
30 |
|
|
entity InvSub_addRk is
|
31 |
|
|
port(
|
32 |
|
|
state_in : in std_logic_vector(127 downto 0);
|
33 |
|
|
state_out : out std_logic_vector(127 downto 0);
|
34 |
|
|
key : in std_logic_vector(127 downto 0)
|
35 |
|
|
);
|
36 |
|
|
end InvSub_addRk;
|
37 |
|
|
|
38 |
|
|
architecture beh_InvSub_addRk of InvSub_addRk is
|
39 |
|
|
|
40 |
|
|
component Inv_Sub_4bytes
|
41 |
|
|
port(
|
42 |
|
|
word_in: in std_logic_vector(31 downto 0);
|
43 |
|
|
word_out: out std_logic_vector(31 downto 0)
|
44 |
|
|
);
|
45 |
|
|
end component;
|
46 |
|
|
|
47 |
|
|
signal shc0,shc1,shc2,shc3 : std_logic_vector(31 downto 0);--Inv shifted columns
|
48 |
|
|
signal c0,c1,c2,c3 : std_logic_vector(31 downto 0);
|
49 |
|
|
signal k0,k1,k2,k3 : std_logic_vector(31 downto 0);
|
50 |
|
|
signal isb0,isb1,isb2,isb3:std_logic_vector(31 downto 0);
|
51 |
|
|
signal w0,w1,w2,w3 : std_logic_vector(31 downto 0);
|
52 |
|
|
|
53 |
|
|
begin
|
54 |
|
|
Inv_Sub_4bytes_inst1:Inv_Sub_4bytes
|
55 |
|
|
port map(word_in=>shc0 , word_out=>isb0 );
|
56 |
|
|
|
57 |
|
|
Inv_Sub_4bytes_inst2:Inv_Sub_4bytes
|
58 |
|
|
port map(word_in=>shc1 , word_out=>isb1 );
|
59 |
|
|
|
60 |
|
|
Inv_Sub_4bytes_inst3:Inv_Sub_4bytes
|
61 |
|
|
port map(word_in=>shc2 , word_out=>isb2 );
|
62 |
|
|
|
63 |
|
|
Inv_Sub_4bytes_inst4:Inv_Sub_4bytes
|
64 |
|
|
port map(word_in=>shc3 , word_out=>isb3 );
|
65 |
|
|
|
66 |
|
|
k0 <= key(127 downto 96);
|
67 |
|
|
k1 <= key(95 downto 64);
|
68 |
|
|
k2 <= key(63 downto 32);
|
69 |
|
|
k3 <= key(31 downto 0);
|
70 |
|
|
|
71 |
|
|
c0 <= state_in(127 downto 96);
|
72 |
|
|
c1 <= state_in(95 downto 64);
|
73 |
|
|
c2 <= state_in(63 downto 32);
|
74 |
|
|
c3 <= state_in(31 downto 0);
|
75 |
|
|
|
76 |
|
|
shc0 <= c0(31 downto 24) & c3(23 downto 16) & c2(15 downto 8) & c1(7 downto 0);
|
77 |
|
|
shc1 <= c1(31 downto 24) & c0(23 downto 16) & c3(15 downto 8) & c2(7 downto 0);
|
78 |
|
|
shc2 <= c2(31 downto 24) & c1(23 downto 16) & c0(15 downto 8) & c3(7 downto 0);
|
79 |
|
|
shc3 <= c3(31 downto 24) & c2(23 downto 16) & c1(15 downto 8) & c0(7 downto 0);
|
80 |
|
|
|
81 |
|
|
w0 <= isb0 xor k0;
|
82 |
|
|
w1 <= isb1 xor k1;
|
83 |
|
|
w2 <= isb2 xor k2;
|
84 |
|
|
w3 <= isb3 xor k3;
|
85 |
|
|
|
86 |
|
|
state_out <= w0 & w1 & w2 & w3;
|
87 |
|
|
|
88 |
|
|
end beh_InvSub_addRk;
|