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[/] [aes_decry_ip_128bit/] [trunk/] [rtl/] [key_schd/] [singleport_RAM.vhd] - Blame information for rev 4

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1 4 ghegde
--************************************************************
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--Copyright 2015, Ganesh Hegde < ghegde@opencores.org >      
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--                                                           
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--This source file may be used and distributed without  
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--restriction provided that this copyright statement is not 
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--removed from the file and that any derivative work contains
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--the original copyright notice and the associated disclaimer.
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--
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--This source is distributed in the hope that it will be
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--useful, but WITHOUT ANY WARRANTY; without even the implied
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--warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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--PURPOSE.  See the GNU Lesser General Public License for more
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--details.
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--
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--You should have received a copy of the GNU Lesser General
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--Public License along with this source; if not, download it
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--from http://www.opencores.org/lgpl.shtml
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--
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--*************************************************************
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--*************************************************************
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-- Single port RAM module.
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--Write latency : 1 clock cycle
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-- Read latency : One clock cycle is consumed to register the address.
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-- Data is valid there after. 
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--Logic type : Sequential
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--*************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity singleport_RAM is
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   port(
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        datain : in std_logic_vector(127 downto 0);
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                addr : in std_logic_vector(3 downto 0);
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                we,clk   : in std_logic;
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                dataout: out std_logic_vector(127 downto 0)
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   );
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end singleport_RAM;
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architecture beh_singleport_RAM of singleport_RAM is
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-- Build a 2-D array type for the RAM
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subtype word_t is std_logic_vector(127  downto 0);
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type memory is array (15 downto 0) of word_t;
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-- Declare the RAM signal.
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signal RAM:memory;
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-- Register to hold the address
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signal addr_reg : natural range 0 to 15;
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signal ram_addr :natural range 0 to 15;
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begin
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   process(clk)
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   begin
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        if clk'event and clk='1' then
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           if(we='1') then
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             RAM(ram_addr)<= datain;
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           end if;
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       -- Register the address for reading
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       addr_reg <=  ram_addr;
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        end if;
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   end process;
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   dataout <= RAM(addr_reg);
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   ram_addr <= to_integer(unsigned(addr));
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end beh_singleport_RAM;

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