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[/] [aes_decry_ip_128bit/] [trunk/] [rtl/] [one_round_decrypt.vhd] - Blame information for rev 4

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1 4 ghegde
--************************************************************
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--Copyright 2015, Ganesh Hegde < ghegde@opencores.org >      
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--                                                           
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--This source file may be used and distributed without  
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--restriction provided that this copyright statement is not 
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--removed from the file and that any derivative work contains
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--the original copyright notice and the associated disclaimer.
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--
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--This source is distributed in the hope that it will be
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--useful, but WITHOUT ANY WARRANTY; without even the implied
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--warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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--PURPOSE.  See the GNU Lesser General Public License for more
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--details.
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--
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--You should have received a copy of the GNU Lesser General
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--Public License along with this source; if not, download it
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--from http://www.opencores.org/lgpl.shtml
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--
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--*************************************************************
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--*************************************************************
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-- One round of decryption is done
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--Logic type : Combinational
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--*************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity one_round_decrypt is
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   port(
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          cipher : in std_logic_vector(127 downto 0);
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                  text_out: out std_logic_vector(127 downto 0);
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                  round_key: in std_logic_vector(127 downto 0)
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       );
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end one_round_decrypt;
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architecture beh_one_round_decrypt of one_round_decrypt is
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component InvSub_addRk
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   port(
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        state_in : in std_logic_vector(127 downto 0);
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        state_out : out std_logic_vector(127 downto 0);
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                key : in std_logic_vector(127 downto 0)
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         );
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end component;
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component inv_mix_column
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   port(
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           column: in std_logic_vector(31 downto 0);
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                   p0,p1,p2,p3: out std_logic_vector(31 downto 0)
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        );
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end component;
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signal p00,p01,p02,p03,
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       p10,p11,p12,p13,
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           p20,p21,p22,p23,
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           p30,p31,p32,p33:std_logic_vector(31 downto 0);
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signal c0,c1,c2,c3:std_logic_vector(31 downto 0);
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signal out0,out1,out2,out3: std_logic_vector(31 downto 0);
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signal t0,t1,t2,t3:std_logic_vector(31 downto 0);
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signal state_out: std_logic_vector(127 downto 0);
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begin
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    InvSub_addRk_inst:InvSub_addRk
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        port map(state_in=>cipher,state_out=>state_out,key=>round_key);
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        inv_mix_column_inst0:inv_mix_column
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        port map(column=>c0,p0=>p00,p1=>p01,p2=>p02,p3=>p03);
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        inv_mix_column_inst1:inv_mix_column
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        port map(column=>c1,p0=>p10,p1=>p11,p2=>p12,p3=>p13);
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        inv_mix_column_inst2:inv_mix_column
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        port map(column=>c2,p0=>p20,p1=>p21,p2=>p22,p3=>p23);
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        inv_mix_column_inst3:inv_mix_column
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        port map(column=>c3,p0=>p30,p1=>p31,p2=>p32,p3=>p33);
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        c0<=state_out(127 downto 96);
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        c1<=state_out(95 downto 64);
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        c2<=state_out(63 downto 32);
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        c3<=state_out(31 downto 0);
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        out0 <= p00 xor p01 xor p02 xor p03;
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        out1 <= p10 xor p11 xor p12 xor p13;
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        out2 <= p20 xor p21 xor p22 xor p23;
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        out3 <= p30 xor p31 xor p32 xor p33;
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        text_out<=out0 & out1 & out2 & out3;
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end  beh_one_round_decrypt;

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