OpenCores
URL https://opencores.org/ocsvn/aes_decrypt_fpga/aes_decrypt_fpga/trunk

Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt256_tb.sv] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 schengopen
`timescale 1ns/1ps
2
 
3
// Uncomment the following line if you're targeting Xilinx FPGA
4
//`define XILINX 1
5
 
6
// generic_muxfx.v defines a generic 2-to-1 MUX. This file is used to provide
7
// a generic definition of MUXF7 and MUXF8 in case you are not targetting Xilinx.
8
// When targetting Xilinx, skip this file to allow the simulator to locate the
9
// MUXF7 and MUXF8 in the Xilinx unisim library.
10
`ifndef XILINX
11
`include "generic/generic_muxfx.v"
12
`endif
13
 
14
`include "InvSbox.sv"
15
`include "InvSubBytes.sv"
16
`include "InvShiftRows.sv"
17
`include "InvAddRoundKey.sv"
18
`include "gfmul.sv"
19
`include "InvMixCol_slice.sv"
20
`include "InvMixColumns.sv"
21
`include "decrypt.sv"
22
`include "KschBuffer.sv"
23
`include "Sbox.sv"
24
`include "SubWord.sv"
25
`include "RotWord.sv"
26
`include "KeyExpand256.sv"
27
`include "aes_decrypt256.sv"
28
`include "aes_beh_model.sv"
29
 
30
`define PERIOD 10
31
`define T (`PERIOD/2)
32
`define Tcko 1
33
 
34
`define WAIT_N_CLK(num_of_clk) repeat(num_of_clk) @(posedge clk); #(`Tcko)
35
 
36
module aes_decrypt256_tb;
37
 
38
        logic   [0:127] ct;
39
        logic   ct_vld;
40
        wire    ct_rdy;
41
 
42
        logic   [0:255] kt;
43
        logic   kt_vld;
44
        wire    kt_rdy;
45
 
46
        wire    [0:127] pt;
47
        wire    pt_vld;
48
 
49
        logic   clk;
50
        logic   rst;
51
 
52
        int     sample_vec_failed = 0;
53
        int     back_to_back_failed = 0;
54
        int     RandVec_256_failed = 0;
55
        int     failed = 0;
56
 
57
        aes256_decrypt_t ref_model;
58
 
59
        logic   [0:255] tmp_kt;
60
        logic   [0:127] tmp_ct;
61
 
62
        `include "decrypt_vec.sv"
63
 
64
        task set_kt(input [0:255] x);
65
                kt = x;
66
                kt_vld = 1;
67
                `WAIT_N_CLK(1);
68
                kt_vld = 0;
69
                `WAIT_N_CLK(1);
70
        endtask
71
 
72
        task set_ct(input [0:127] x);
73
                ct = x;
74
                ct_vld = 1;
75
                `WAIT_N_CLK(1);
76
                ct_vld = 0;
77
                `WAIT_N_CLK(1);
78
        endtask
79
 
80
        function logic [0:127] rand128;
81
                rand128 = {$random, $random, $random, $random};
82
        endfunction
83
 
84
 
85
        function logic [0:255] rand256;
86
                rand256 = {$random, $random, $random, $random, $random, $random, $random, $random};
87
        endfunction
88
 
89
        always
90
        begin
91
                clk <= 1;
92
                #(`T);
93
                clk <= 0;
94
                #(`T);
95
        end
96
 
97
        aes_decrypt256 uut(.*);
98
 
99
        initial begin
100
                ref_model = new;
101
 
102
                rst = 1;
103
                kt_vld = 0;
104
                ct_vld = 0;
105
                `WAIT_N_CLK(3);
106
 
107
                rst = 0;
108
                `WAIT_N_CLK(1);
109
 
110
                // FIPS-197 sample vector test. FIPS-197 appendix C.3.
111
 
112
                $display("FIPS-197 sample vector test");
113
                $display("kt=000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f ct=8ea2b7ca516745bfeafc49904b496089");
114
                wait (kt_rdy);
115
                set_kt(256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f);
116
                wait (ct_rdy);
117
                set_ct(128'h8ea2b7ca516745bfeafc49904b496089);
118
                wait (pt_vld);
119
                $display("pt=%h expected=00112233445566778899aabbccddeeff",pt);
120
                if (pt != 128'h00112233445566778899aabbccddeeff)
121
                begin
122
                        $display("***Mismatch");
123
                        sample_vec_failed = 1;
124
                        failed = 1;
125
                end
126
                $display("FIPS-197 sample vector test finished : %s", (sample_vec_failed)? "FAILED" : "PASSED");
127
                `WAIT_N_CLK(2);
128
 
129
                // Back-to-back ciphertext test.
130
                // Two ciphertext are applied back-to-back with no dead cycle in between.
131
 
132
                $display("\nBack-to-back ciphertext test");
133
                tmp_ct = rand128();
134
                tmp_kt = rand256();
135
                ref_model.KeyExpand(tmp_kt);
136
                ref_model.LoadCt(tmp_ct);
137
                ref_model.run(0);
138
 
139
                wait (kt_rdy);
140
                set_kt(tmp_kt);
141
                wait (ct_rdy);
142
                set_ct(tmp_ct);
143
                wait (pt_vld);
144
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
145
                if (pt != ref_model.GetState())
146
                begin
147
                        $display("***Mismatch");
148
                        back_to_back_failed = 1;
149
                        failed = 1;
150
                end
151
 
152
                tmp_ct = rand128();
153
                ref_model.LoadCt(tmp_ct);
154
                ref_model.run(0);
155
                wait (ct_rdy);
156
                set_ct(tmp_ct);
157
                wait (pt_vld);
158
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
159
                if (pt != ref_model.GetState())
160
                begin
161
                        $display("***Mismatch");
162
                        back_to_back_failed = 1;
163
                        failed = 1;
164
                end
165
 
166
                $display("Back-to-back ciphertext test finished : %s", (back_to_back_failed)? "FAILED" : "PASSED");
167
                `WAIT_N_CLK(2);
168
 
169
                // ECB-AES256.Decrypt sample vector test. SP800-38a appendix F.1.6
170
 
171
                $display("\nECB-AES256.Decrypt sample vector test");
172
                for (int k=0; k<`ECB_DECRYPT_256_VEC_SIZE; k++)
173
                begin
174
                        set_kt(ECBDecrypt_256_kt);
175
                        wait(ct_rdy);
176
                        set_ct(ECBDecrypt_256_ct[k]);
177
                        wait(pt_vld);
178
                        $display("kt=%h ct=%h pt=%h expected=%h",ECBDecrypt_256_kt,ECBDecrypt_256_ct[k],pt,ECBDecrypt_256_pt[k]);
179
                        if (pt != ECBDecrypt_256_pt[k])
180
                        begin
181
                                $display("***Mismatch");
182
                                ECBDecrypt_256_failed = 1;
183
                        end
184
                end
185
 
186
                $display("ECB-AES192.Decrypt sample vector test finished : %s", (ECBDecrypt_256_failed)? "FAILED" : "PASSED");
187
                `WAIT_N_CLK(2);
188
 
189
                // GFSbox Known Answer Test. AESAVS appendix B.3.
190
 
191
                $display("\nGFSbox Known Answer Test");
192
                for (int k=0; k<`GFSbox_256_VEC_SIZE; k++)
193
                begin
194
                        set_kt(GFSbox_256_kt);
195
                        wait(ct_rdy);
196
                        set_ct(GFSbox_256_ct[k]);
197
                        wait(pt_vld);
198
                        $display("kt=%h ct=%h pt=%h expected=%h",GFSbox_256_kt,GFSbox_256_ct[k],pt,GFSbox_256_pt[k]);
199
                        if (pt != GFSbox_256_pt[k])
200
                        begin
201
                                $display("***Mismatch");
202
                                GFSbox_256_failed = 1;
203
                        end
204
                end
205
 
206
                $display("GFSbox test finished : %s", (GFSbox_256_failed)? "FAILED" : "PASSED");
207
                `WAIT_N_CLK(2);
208
 
209
                // KeySbox Known Answer Test. AESAVS appendix C.3.
210
 
211
                $display("\nKeySbox Known Answer Test");
212
                for (int k=0; k<`KEYSBOX_256_VEC_SIZE; k++)
213
                begin
214
                        set_kt(KeySbox_256_kt[k]);
215
                        wait(ct_rdy);
216
                        set_ct(KeySbox_256_ct[k]);
217
                        wait(pt_vld);
218
                        $display("kt=%h ct=%h pt=%h expected=%h",KeySbox_256_kt[k],KeySbox_256_ct[k],pt,KeySbox_256_pt);
219
                        if (pt != KeySbox_256_pt[k])
220
                        begin
221
                                $display("***Mismatch");
222
                                KeySbox_256_failed = 1;
223
                        end
224
                end
225
 
226
                $display("KeySbox test finished : %s", (KeySbox_256_failed)? "FAILED" : "PASSED");
227
                `WAIT_N_CLK(2);
228
 
229
                // VarTxt Known Answer Test. AESAVS appendix D.3.
230
 
231
                $display("\nVarTxt Known Answer Test");
232
                for (int k=0; k<`VARTXT_256_VEC_SIZE; k++)
233
                begin
234
                        set_kt(VarTxt_256_kt);
235
                        wait(ct_rdy);
236
                        set_ct(VarTxt_256_ct[k]);
237
                        wait(pt_vld);
238
                        $display("kt=%h ct=%h pt=%h expected=%h",VarTxt_256_kt,VarTxt_256_ct[k],pt,VarTxt_256_pt[k]);
239
                        if (pt != VarTxt_256_pt[k])
240
                        begin
241
                                $display("***Mismatch");
242
                                VarTxt_256_failed = 1;
243
                        end
244
                end
245
 
246
                $display("VarTxt Known Answer Test finished : %s", (VarTxt_256_failed)? "FAILED" : "PASSED");
247
                `WAIT_N_CLK(2);
248
 
249
                // VarKey Known Answer Test. AESAVS appendix E.3.
250
 
251
                $display("\nVarKey Known Answer Test");
252
                for (int k=0; k<`VARKEY_256_VEC_SIZE; k++)
253
                begin
254
                        set_kt(VarKey_256_kt[k]);
255
                        wait(ct_rdy);
256
                        set_ct(VarKey_256_ct[k]);
257
                        wait(pt_vld);
258
                        $display("kt=%h ct=%h pt=%h expected=%h",VarKey_256_kt[k],VarKey_256_ct[k],pt,VarKey_256_pt);
259
                        if (pt != VarKey_256_pt)
260
                        begin
261
                                $display("***Mismatch");
262
                                VarKey_256_failed = 1;
263
                        end
264
                end
265
 
266
                $display("VarKey Known Answer Test finished : %s", (VarKey_256_failed)? "FAILED" : "PASSED");
267
                `WAIT_N_CLK(2);
268
 
269
                // Random vector test against golden model.
270
 
271
                $display("\nRandom Vector Test");
272
                for (int k=0; k<1000; k++)
273
                begin
274
                        tmp_ct = rand128();
275
                        tmp_kt = rand256();
276
                        ref_model.KeyExpand(tmp_kt);
277
                        ref_model.LoadCt(tmp_ct);
278
                        ref_model.run(0);
279
 
280
                        wait (kt_rdy);
281
                        set_kt(tmp_kt);
282
                        wait (ct_rdy);
283
                        set_ct(tmp_ct);
284
                        wait (pt_vld);
285
                        $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
286
                        if (pt != ref_model.GetState())
287
                        begin
288
                                $display("***Mismatch");
289
                                RandVec_256_failed = 1;
290
                        failed = 1;
291
                        end
292
                end
293
 
294
                $display("Random Vector Test finished : %s", (RandVec_256_failed)? "FAILED" : "PASSED");
295
                `WAIT_N_CLK(2);
296
 
297
                $display("\nAll tests finished : %s", (failed)? "FAILED" : "OK");
298
 
299
                $stop;
300
        end
301
 
302
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.