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[/] [aes_decrypt_fpga/] [trunk/] [rtl/] [verilog/] [InvAddRoundKey.sv] - Blame information for rev 4

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`timescale 1ns/1ps
 
module InvAddRoundKey(
        input   [0:127] din0,
        input   [0:127] din1,
        input   [0:127] rkey,
        input   S,
        output  [0:127] dout);
 
        logic   [0:127] tmp;
 
        always_comb
                tmp <= S? din1 : din0;
 
        assign dout = tmp ^ rkey;
endmodule

Line No.	Rev	Author	Line
1	2	schengopen	`timescale 1ns/1ps
2
3			`module InvAddRoundKey(`
4			`input [0:127] din0,`
5			`input [0:127] din1,`
6			`input [0:127] rkey,`
7			`input S,`
8			`output [0:127] dout);`
9
10			`logic [0:127] tmp;`
11
12			`always_comb`
13			`tmp <= S? din1 : din0;`
14
15			`assign dout = tmp ^ rkey;`
16			`endmodule`

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[/] [aes_decrypt_fpga/] [trunk/] [rtl/] [verilog/] [InvAddRoundKey.sv] - Blame information for rev 4