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schengopen |
////////////////////////////////////////////////////////////////// ////
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//// ////
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//// AES Decryption Core for FPGA ////
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//// ////
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//// This file is part of the AES Decryption Core for FPGA project ////
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//// http://www.opencores.org/cores/xxx/ ////
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//// ////
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//// Description ////
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//// Implementation of AES Decryption Core for FPGA according to ////
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//// core specification document. ////
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//// ////
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//// To Do: ////
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//// - ////
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//// ////
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//// Author(s): ////
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//// - scheng, schengopencores@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// //// ///
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///////////////////////////////////////////////////////////////////
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//// ////
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//// Decryption engine ////
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//// ////
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//// Wrapper for 192-bit AES decryption ////
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//// ////
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////////////////////////////////////////////////////////////////////////
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module aes_decrypt192(
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input [0:191] kt,
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input kt_vld, // Active high input informing key expander that a valid new key is present at kt.
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output kt_rdy, // Active high output indicates decryptor ready to accept new key.
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input [0:127] ct, // Ciphertext input
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input ct_vld, // Active high input indicates a valid ciphertext present on ct.
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output ct_rdy, // Active high output indicates decryptor ready to accept new ct.
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output [0:127] pt, // Plaintext output
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output pt_vld, // Active high output indicates valid plaintext available on pt.
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input clk,
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input rst
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);
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// Decryptor side
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wire [0:127] rkey_decrypt;
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wire rkey_vld_decrypt;
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wire next_rkey_decrypt;
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// Key Expander side
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wire [0:127] rkey_keyexp;
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wire rkey_vld_keyexp;
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(* KEEP_HIRARACHY = "yes" *) KschBuffer KschBuffer_u(.rkey_in(rkey_keyexp),
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.rkey_vld_in(rkey_vld_keyexp),
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.rkey_out(rkey_decrypt),
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.rkey_vld_out(rkey_vld_decrypt),
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.next_rkey(next_rkey_decrypt),
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.klen_sel(2'b01),
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.clk(clk),
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.rst(rst)
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);
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(* KEEP_HIRARACHY = "yes" *) KeyExpand192 KeyExpand192_u(
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.kt(kt),
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.kt_vld(kt_vld),
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.kt_rdy(kt_rdy),
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.rkey(rkey_keyexp),
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.rkey_vld(rkey_vld_keyexp),
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.rkey_last(),
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.clk(clk),
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.rst(rst)
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);
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(* KEEP_HIRARACHY = "yes" *) decrypt decrypt_u( .ct(ct),
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.ct_vld(ct_vld),
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.ct_rdy(ct_rdy),
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.rkey(rkey_decrypt),
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.rkey_vld(rkey_vld_decrypt),
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.next_rkey(next_rkey_decrypt),
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.pt(pt),
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.pt_vld(pt_vld),
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.klen_sel(2'b01), // 2'b01 selects 192-bit key
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.clk(clk),
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.rst(rst)
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);
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endmodule
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