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[/] [aes_decrypt_fpga/] [trunk/] [rtl/] [verilog/] [generic/] [generic_muxfx.v] - Blame information for rev 2

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1 2 schengopen
// Technology independent version of MUXF7 and MUXF8.
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//
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// This file should not be included while targeting Xilinx so that
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// the MUXF7/MUXF8 primitives in the Xilinx simulation/synthesis
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// will be used instead.
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module MUXF7 (output O, input I0, input I1, input S);
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        assign O = (S)? I1 : I0;
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endmodule
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module MUXF8 (output O, input I0, input I1, input S);
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        assign O = (S)? I1 : I0;
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endmodule

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