URL https://opencores.org/ocsvn/aes_decrypt_fpga/aes_decrypt_fpga/trunk

Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim128.do] - Blame information for rev 2

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cd ../run
vlib aes_decrypt128_tb_lib
vmap work aes_decrypt128_tb_lib
vlog +incdir+../../../rtl/verilog +incdir+../src  ../../../bench/verilog/aes_decrypt128_tb.sv
vsim aes_decrypt128_tb
#add wave *
run -all

Line No.	Rev	Author	Line
1	2	schengopen	`cd ../run`
2			`vlib aes_decrypt128_tb_lib`
3			`vmap work aes_decrypt128_tb_lib`
4			`vlog +incdir+../../../rtl/verilog +incdir+../src ../../../bench/verilog/aes_decrypt128_tb.sv`
5			`vsim aes_decrypt128_tb`
6			`#add wave *`
7			`run -all`

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Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim128.do] - Blame information for rev 2