OpenCores
URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [readme.txt] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rainrhythm
____________________________________________________________________________
2
General Description:
3
        This is a high performance AES core. It supports 128/192/256 key size
4
        modes for encryption and decryption.
5
____________________________________________________________________________
6
Clock Speed:
7
        It can reach more than 300 MHz under 65nm process.
8
____________________________________________________________________________
9
Gatecount:
10
        Around 35K NAND2 gates;
11
____________________________________________________________________________
12
Performance:
13
        Clock Frequency * 128 / Round number, under 200 MHz, it is:
14
        128 bit -> 2.5Gbps;
15
        192 bit -> 2.1Gbps;
16
        256 bit -> 1.8Gbps;
17
____________________________________________________________________________
18
Some notes for the interface:
19
1. After a i_start assert (pluse), please wait for o_key_ready high
20
2. For decryption, don't input data before o_key_ready is not high
21
3. For encryption, data can be input after 1cycle of i_start pluse
22
4. Don't input data if previous cycle's o_ready is low
23
5. Don't input data if i_enable is low
24
6. make i_key_mode and i_key stable before o_key_ready is high
25
7. i_enable is used pause the core for any purpose
26
8. Basically, you can import 4  128 bit data to the core before the first valid output
27
        data, because there are 4 pipelines inside. Then you need to wait for the output data for
28
        Nr*4 cycles. (o_ready is reflecting it actually)
29
9. key expansion will take 30~40 cycles based on key modes (o_key_ready marks it).
30
10. Currently, there are 2 16x64 rams, with minor modifications, can change to
31
        1 16x128 ram or 4 16x32 rams or 8 16x16 rams
32
11. in 128/192 mode, the higher bits of i_key is valid
33
____________________________________________________________________________
34
Any questions, please contact dongjun_luo@hotmail.com

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.