URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [xram_16x64.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	motilito	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Ram module ////`
4			`//// ////`
5			`//// Description: ////`
6			`//// this is 16x64, we can use a 16x128 to replace two of this ////`
7			`//// module, also, can use specific foundry libs instead ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - done ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Luo Dongjun, dongjun_luo@hotmail.com ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`module xram_16x64`
17			`(`
18			`clk, wr,`
19			`wr_addr, wr_data,`
20			`rd_addr, rd_data`
21			`);`
22
23			`input clk, wr;`
24			`input [3:0] wr_addr, rd_addr;`
25			`input [63:0] wr_data;`
26			`output [63:0] rd_data;`
27
28			`reg [63:0] mem [15:0];`
29			`wire [63:0] rd_data;`
30
31			`// behavioral code for 16x64 mem`
32			`always @ (posedge clk)`
33			`begin`
34			`if (wr)`
35			`mem[wr_addr] <= wr_data;`
36			`end`
37
38			`assign rd_data = mem[rd_addr];`
39
40			`endmodule`