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subhasis25 |
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---- ----
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subhasis25 |
---- Pipelined Aes IP Core ----
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---- ----
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---- This file is part of the Pipelined AES project ----
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---- http://www.opencores.org/cores/aes_pipe/ ----
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---- ----
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---- Description ----
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---- Implementation of AES IP core according to ----
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---- FIPS PUB 197 specification document. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Subhasis Das, subhasis256@gmail.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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subhasis25 |
---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Author: Subhasis
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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--
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-- Description: The AddKey step
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-- Ports:
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-- clk: System Clock
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-- roundkey: The RoundKey block for this round
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-- datain: Input State block
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-- rcon: The rcon byte corresponding to the current stage
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-- dataout: datain xor roundkey
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-- fc3: See keysched1 for explanation
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-- c0: See keysched1 for explanation
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-- c1: See keysched1 for explanation
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-- c2: See keysched1 for explanation
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-- c3: See keysched1 for explanation
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------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.aes_pkg.all;
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entity addkey is
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port(
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clk: in std_logic;
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rst: in std_logic;
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roundkey: in datablock;
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datain: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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dataout: out datablock;
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fc3: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c2: out blockcol;
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c3: out blockcol
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);
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end addkey;
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architecture rtl of addkey is
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component keysched1 is
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port(
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clk: in std_logic;
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rst: in std_logic;
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roundkey: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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fc3: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c2: out blockcol;
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c3: out blockcol
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);
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end component;
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signal added: datablock;
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begin
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step1: keysched1 port map(
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clk => clk,
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rst => rst,
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roundkey => roundkey,
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rcon => rcon,
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fc3 => fc3,
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c0 => c0,
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c1 => c1,
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c2 => c2,
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c3 => c3
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);
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g0: for i in 3 downto 0 generate
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g1: for j in 3 downto 0 generate
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added(i,j) <= datain(i,j) xor roundkey(i,j);
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end generate;
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end generate;
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process(clk,rst)
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begin
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if(rst = '1') then
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dataout <= zero_data;
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elsif(rising_edge(clk)) then
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dataout <= added;
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end if;
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end process;
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end rtl;
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