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[/] [aes_pipe/] [trunk/] [rtl/] [vhdl/] [aes_top.vhdl] - Blame information for rev 9

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----------------------------------------------------------------------
----                                                              ----
---- Pipelined Aes IP Core                                        ----
----                                                              ----
---- This file is part of the Pipelined AES project               ----
---- http://www.opencores.org/cores/aes_pipe/                     ----
----                                                              ----
---- Description                                                  ----
---- Implementation of AES IP core according to                   ----
---- FIPS PUB 197 specification document.                         ----
----                                                              ----
---- To Do:                                                       ----
----   -                                                          ----
----                                                              ----
---- Author:                                                      ----
----      - Subhasis Das, subhasis256@gmail.com                   ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The Overall Core
-- Ports:
--                      clk_i: System Clock
--                      plaintext_i: Input plaintext blocks
--                      keyblock_i: Input keyblock
--                      ciphertext_o: Output Cipher Block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity aes_top is
port(
        clk_i: in std_logic;
        rst_i: in std_logic;
        plaintext_i: in datablock;
        keyblock_i: in datablock;
        ciphertext_o: out datablock
        );
end aes_top;
 
architecture rtl of aes_top is
signal fc3, c0, c1, c2, c3: colnet(9 downto 0);
signal textnet_a_s, textnet_s_m, textnet_m_a: datanet(9 downto 0);
signal key_m, key_s: datanet(9 downto 0);
signal textnet_s_a: datablock;
 
component sboxshr is
port(
        clk: in std_logic;
        rst: in std_logic;
        blockin: in datablock;
        fc3: in blockcol;
        c0: in blockcol;
        c1: in blockcol;
        c2: in blockcol;
        c3: in blockcol;
        nextkey: out datablock;
        blockout: out datablock
        );
end component;
component colmix is
port(
        clk: in std_logic;
        rst: in std_logic;
        datain: in datablock;
        inrkey: in datablock;
        outrkey: out datablock;
        dataout: out datablock
        );
end component;
component addkey is
port(
        clk: in std_logic;
        rst: in std_logic;
        roundkey: in datablock;
        datain: in datablock;
        rcon: in std_logic_vector(7 downto 0);
        dataout: out datablock;
        fc3: out blockcol;
        c0: out blockcol;
        c1: out blockcol;
        c2: out blockcol;
        c3: out blockcol
        );
end component;
begin
        key_m(0) <= keyblock_i;
        textnet_m_a(0) <= plaintext_i;
        -------------------------------------------------------
        -- Instead of the conventional order of
        -- Addkey -> (Sbox -> Mixcol -> Addkey) ... 9 times
        -- -> Sbox -> Addkey, we code the design as
        -- (Addkey -> Sbox -> Mixcol) ... 9 times -> Addkey ->
        -- Sbox -> Addkey
        -------------------------------------------------------
        proc: for i in 8 downto 0 generate
                add: addkey port map(
                                                        clk => clk_i,
                                                        rst => rst_i,
                                                        roundkey => key_m(i),
                                                        datain => textnet_m_a(i),
                                                        rcon => rcon(i),
                                                        dataout => textnet_a_s(i),
                                                        fc3 => fc3(i),
                                                        c0 => c0(i),
                                                        c1 => c1(i),
                                                        c2 => c2(i),
                                                        c3 => c3(i)
                                                        );
                sbox: sboxshr port map(
                                                          clk => clk_i,
                                                          rst => rst_i,
                                                          blockin => textnet_a_s(i),
                                                          fc3 => fc3(i),
                                                          c0 => c0(i),
                                                          c1 => c1(i),
                                                          c2 => c2(i),
                                                          c3 => c3(i),
                                                          nextkey => key_s(i),
                                                          blockout => textnet_s_m(i)
                                                          );
                mix: colmix port map(
                                                        clk => clk_i,
                                                        rst => rst_i,
                                                        datain => textnet_s_m(i),
                                                        inrkey => key_s(i),
                                                        outrkey => key_m(i+1),
                                                        dataout => textnet_m_a(i+1)
                                                        );
        end generate;
        add_f_1: addkey port map(
                                                        clk => clk_i,
                                                        rst => rst_i,
                                                        roundkey => key_m(9),
                                                        datain => textnet_m_a(9),
                                                        rcon => rcon(9),
                                                        dataout => textnet_a_s(9),
                                                        fc3 => fc3(9),
                                                        c0 => c0(9),
                                                        c1 => c1(9),
                                                        c2 => c2(9),
                                                        c3 => c3(9)
                                                        );
        sbox_f_1: sboxshr port map(
                                                          clk => clk_i,
                                                          rst => rst_i,
                                                          blockin => textnet_a_s(9),
                                                          fc3 => fc3(9),
                                                          c0 => c0(9),
                                                          c1 => c1(9),
                                                          c2 => c2(9),
                                                          c3 => c3(9),
                                                          nextkey => key_s(9),
                                                          blockout => textnet_s_a
                                                          );
        add_f: addkey port map(
                                                  clk => clk_i,
                                                  rst => rst_i,
                                                  roundkey => key_s(9),
                                                  datain => textnet_s_a,
                                                  rcon => X"00",
                                                  dataout => ciphertext_o
                                                  );
end rtl;

Line No.	Rev	Author	Line
1	2	subhasis25	`----------------------------------------------------------------------`
2			`---- ----`
3	9	subhasis25	`---- Pipelined Aes IP Core ----`
4			`---- ----`
5			`---- This file is part of the Pipelined AES project ----`
6			`---- http://www.opencores.org/cores/aes_pipe/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Implementation of AES IP core according to ----`
10			`---- FIPS PUB 197 specification document. ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- - ----`
14			`---- ----`
15			`---- Author: ----`
16			`---- - Subhasis Das, subhasis256@gmail.com ----`
17			`---- ----`
18			`----------------------------------------------------------------------`
19			`---- ----`
20			`---- Copyright (C) 2009 Authors and OPENCORES.ORG ----`
21			`---- ----`
22	2	subhasis25	`---- This source file may be used and distributed without ----`
23			`---- restriction provided that this copyright statement is not ----`
24	9	subhasis25	`---- removed from the file and that any derivative work contains ----`
25	2	subhasis25	`---- the original copyright notice and the associated disclaimer. ----`
26			`---- ----`
27			`---- This source file is free software; you can redistribute it ----`
28			`---- and/or modify it under the terms of the GNU Lesser General ----`
29			`---- Public License as published by the Free Software Foundation; ----`
30			`---- either version 2.1 of the License, or (at your option) any ----`
31			`---- later version. ----`
32			`---- ----`
33			`---- This source is distributed in the hope that it will be ----`
34			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
35			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
36	9	subhasis25	`---- PURPOSE. See the GNU Lesser General Public License for more ----`
37	2	subhasis25	`---- details. ----`
38			`---- ----`
39			`---- You should have received a copy of the GNU Lesser General ----`
40			`---- Public License along with this source; if not, download it ----`
41	5	subhasis25	`---- from http://www.opencores.org/lgpl.shtml ----`
42	2	subhasis25	`---- ----`
43			`----------------------------------------------------------------------`
44			`------------------------------------------------------`
45			`-- Project: AESFast`
46			`-- Author: Subhasis`
47	9	subhasis25	`-- Last Modified: 25/03/10`
48	2	subhasis25	`-- Email: subhasis256@gmail.com`
49			`------------------------------------------------------`
50			`--`
51	4	subhasis25	`-- Description: The Overall Core`
52	2	subhasis25	`-- Ports:`
53	5	subhasis25	`-- clk_i: System Clock`
54			`-- plaintext_i: Input plaintext blocks`
55			`-- keyblock_i: Input keyblock`
56			`-- ciphertext_o: Output Cipher Block`
57	2	subhasis25	`------------------------------------------------------`
58
59			`library IEEE;`
60			`use IEEE.std_logic_1164.all;`
61			`use IEEE.std_logic_arith.all;`
62			`use IEEE.std_logic_unsigned.all;`
63
64			`library work;`
65			`use work.aes_pkg.all;`
66
67	5	subhasis25	`entity aes_top is`
68	2	subhasis25	`port(`
69	5	subhasis25	`clk_i: in std_logic;`
70	9	subhasis25	`rst_i: in std_logic;`
71	5	subhasis25	`plaintext_i: in datablock;`
72			`keyblock_i: in datablock;`
73			`ciphertext_o: out datablock`
74	2	subhasis25	`);`
75	5	subhasis25	`end aes_top;`
76	2	subhasis25
77	5	subhasis25	`architecture rtl of aes_top is`
78	2	subhasis25	`signal fc3, c0, c1, c2, c3: colnet(9 downto 0);`
79			`signal textnet_a_s, textnet_s_m, textnet_m_a: datanet(9 downto 0);`
80			`signal key_m, key_s: datanet(9 downto 0);`
81			`signal textnet_s_a: datablock;`
82
83			`component sboxshr is`
84			`port(`
85			`clk: in std_logic;`
86	9	subhasis25	`rst: in std_logic;`
87	2	subhasis25	`blockin: in datablock;`
88			`fc3: in blockcol;`
89			`c0: in blockcol;`
90			`c1: in blockcol;`
91			`c2: in blockcol;`
92			`c3: in blockcol;`
93			`nextkey: out datablock;`
94			`blockout: out datablock`
95			`);`
96			`end component;`
97			`component colmix is`
98			`port(`
99			`clk: in std_logic;`
100	9	subhasis25	`rst: in std_logic;`
101	2	subhasis25	`datain: in datablock;`
102			`inrkey: in datablock;`
103			`outrkey: out datablock;`
104			`dataout: out datablock`
105			`);`
106			`end component;`
107			`component addkey is`
108			`port(`
109			`clk: in std_logic;`
110	9	subhasis25	`rst: in std_logic;`
111	2	subhasis25	`roundkey: in datablock;`
112			`datain: in datablock;`
113			`rcon: in std_logic_vector(7 downto 0);`
114			`dataout: out datablock;`
115			`fc3: out blockcol;`
116			`c0: out blockcol;`
117			`c1: out blockcol;`
118			`c2: out blockcol;`
119			`c3: out blockcol`
120			`);`
121			`end component;`
122			`begin`
123	5	subhasis25	`key_m(0) <= keyblock_i;`
124			`textnet_m_a(0) <= plaintext_i;`
125	2	subhasis25	`-------------------------------------------------------`
126			`-- Instead of the conventional order of`
127			`-- Addkey -> (Sbox -> Mixcol -> Addkey) ... 9 times`
128			`-- -> Sbox -> Addkey, we code the design as`
129			`-- (Addkey -> Sbox -> Mixcol) ... 9 times -> Addkey ->`
130			`-- Sbox -> Addkey`
131			`-------------------------------------------------------`
132			`proc: for i in 8 downto 0 generate`
133			`add: addkey port map(`
134	5	subhasis25	`clk => clk_i,`
135	9	subhasis25	`rst => rst_i,`
136	2	subhasis25	`roundkey => key_m(i),`
137			`datain => textnet_m_a(i),`
138			`rcon => rcon(i),`
139			`dataout => textnet_a_s(i),`
140			`fc3 => fc3(i),`
141			`c0 => c0(i),`
142			`c1 => c1(i),`
143			`c2 => c2(i),`
144			`c3 => c3(i)`
145			`);`
146			`sbox: sboxshr port map(`
147	5	subhasis25	`clk => clk_i,`
148	9	subhasis25	`rst => rst_i,`
149	2	subhasis25	`blockin => textnet_a_s(i),`
150			`fc3 => fc3(i),`
151			`c0 => c0(i),`
152			`c1 => c1(i),`
153			`c2 => c2(i),`
154			`c3 => c3(i),`
155			`nextkey => key_s(i),`
156			`blockout => textnet_s_m(i)`
157			`);`
158			`mix: colmix port map(`
159	5	subhasis25	`clk => clk_i,`
160	9	subhasis25	`rst => rst_i,`
161	2	subhasis25	`datain => textnet_s_m(i),`
162			`inrkey => key_s(i),`
163			`outrkey => key_m(i+1),`
164			`dataout => textnet_m_a(i+1)`
165			`);`
166			`end generate;`
167			`add_f_1: addkey port map(`
168	5	subhasis25	`clk => clk_i,`
169	9	subhasis25	`rst => rst_i,`
170	2	subhasis25	`roundkey => key_m(9),`
171			`datain => textnet_m_a(9),`
172			`rcon => rcon(9),`
173			`dataout => textnet_a_s(9),`
174			`fc3 => fc3(9),`
175			`c0 => c0(9),`
176			`c1 => c1(9),`
177			`c2 => c2(9),`
178			`c3 => c3(9)`
179			`);`
180			`sbox_f_1: sboxshr port map(`
181	5	subhasis25	`clk => clk_i,`
182	9	subhasis25	`rst => rst_i,`
183	2	subhasis25	`blockin => textnet_a_s(9),`
184			`fc3 => fc3(9),`
185			`c0 => c0(9),`
186			`c1 => c1(9),`
187			`c2 => c2(9),`
188			`c3 => c3(9),`
189			`nextkey => key_s(9),`
190			`blockout => textnet_s_a`
191			`);`
192			`add_f: addkey port map(`
193	5	subhasis25	`clk => clk_i,`
194	9	subhasis25	`rst => rst_i,`
195	2	subhasis25	`roundkey => key_s(9),`
196			`datain => textnet_s_a,`
197			`rcon => X"00",`
198	5	subhasis25	`dataout => ciphertext_o`
199	2	subhasis25	`);`
200			`end rtl;`

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[/] [aes_pipe/] [trunk/] [rtl/] [vhdl/] [aes_top.vhdl] - Blame information for rev 9