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[/] [aes_pipe/] [trunk/] [syn/] [Xilinx/] [log/] [aes.map.par] - Blame information for rev 10

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Line No. Rev Author Line
1 10 subhasis25 
Release 11.1 par L.33 (lin)
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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blackpearl-laptop::  Thu Mar 25 14:30:35 2010
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par -w -ol high ../out/aes.ncd ../out/aes.map.ncd
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Constraints file: ../out/aes.pcf.
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Loading device for application Rf_Device from file '5vlx50t.nph' in environment /opt/Xilinx/11.1/ISE.
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   "aes_top" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -1
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
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Device speed data version:  "PRODUCTION 1.64 2009-03-03".
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Device Utilization Summary:
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   Number of BUFGs                           2 out of 32      6%
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   Number of External IOBs                 386 out of 480    80%
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      Number of LOCed IOBs                   0 out of 386     0%
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   Number of Slice Registers              7873 out of 28800  27%
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      Number used as Flip Flops           7873
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      Number used as Latches                 0
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      Number used as LatchThrus              0
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   Number of Slice LUTS                  14724 out of 28800  51%
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   Number of Slice LUT-Flip Flop pairs   15770 out of 28800  54%
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Overall effort level (-ol):   High
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Router effort level (-rl):    High
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Starting initial Timing Analysis.  REAL time: 47 secs
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Finished initial Timing Analysis.  REAL time: 48 secs
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Starting Router
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Phase  1  : 77449 unrouted;      REAL time: 52 secs
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Phase  2  : 67441 unrouted;      REAL time: 1 mins 5 secs
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Phase  3  : 11182 unrouted;      REAL time: 4 mins 3 secs
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Phase  4  : 11253 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 26 secs
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Updating file: ../out/aes.map.ncd with current fully routed design.
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Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
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Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
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Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
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Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
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Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
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Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 24 secs
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Total REAL time to Router completion: 5 mins 24 secs
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Total CPU time to Router completion: 5 mins 13 secs
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Partition Implementation Status
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-------------------------------
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  No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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|         clk_i_BUFGP | BUFGCTRL_X0Y1| No   | 3403 |  0.334     |  1.843      |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Asterisk (*) preceding a constraint indicates it was not met.
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   This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
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                                            |             |    Slack   | Achievable | Errors |    Score
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----------------------------------------------------------------------------------------------------------
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  TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH | SETUP       |     0.026ns|     2.974ns|       0|           0
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   50%                                      | HOLD        |     0.296ns|            |       0|           0
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 5 mins 42 secs
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Total CPU time to PAR completion: 5 mins 30 secs
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Peak Memory Usage:  425 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 0
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Writing design to file ../out/aes.map.ncd
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PAR done!

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