OpenCores
URL https://opencores.org/ocsvn/aes_pipe/aes_pipe/trunk

Subversion Repositories aes_pipe

[/] [aes_pipe/] [trunk/] [syn/] [Xilinx/] [log/] [aes.map.par] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 subhasis25 
Release 11.1 par L.33 (lin)
2 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3 
 
4 
blackpearl-laptop::  Thu Mar 25 14:30:35 2010
5 
 
6 
par -w -ol high ../out/aes.ncd ../out/aes.map.ncd
7 
 
8 
 
9 
Constraints file: ../out/aes.pcf.
10 
Loading device for application Rf_Device from file '5vlx50t.nph' in environment /opt/Xilinx/11.1/ISE.
11 
   "aes_top" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -1
12 
 
13 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
14 
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
15 
 
16 
 
17 
Device speed data version:  "PRODUCTION 1.64 2009-03-03".
18 
 
19 
 
20 
 
21 
Device Utilization Summary:
22 
 
23 
   Number of BUFGs                           2 out of 32      6%
24 
   Number of External IOBs                 386 out of 480    80%
25 
      Number of LOCed IOBs                   0 out of 386     0%
26 
 
27 
   Number of Slice Registers              7873 out of 28800  27%
28 
      Number used as Flip Flops           7873
29 
      Number used as Latches                 0
30 
      Number used as LatchThrus              0
31 
 
32 
   Number of Slice LUTS                  14724 out of 28800  51%
33 
   Number of Slice LUT-Flip Flop pairs   15770 out of 28800  54%
34 
 
35 
 
36 
Overall effort level (-ol):   High
37 
Router effort level (-rl):    High
38 
 
39 
Starting initial Timing Analysis.  REAL time: 47 secs
40 
Finished initial Timing Analysis.  REAL time: 48 secs
41 
 
42 
Starting Router
43 
 
44 
 
45 
Phase  1  : 77449 unrouted;      REAL time: 52 secs
46 
 
47 
Phase  2  : 67441 unrouted;      REAL time: 1 mins 5 secs
48 
 
49 
Phase  3  : 11182 unrouted;      REAL time: 4 mins 3 secs
50 
 
51 
Phase  4  : 11253 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 26 secs
52 
 
53 
Updating file: ../out/aes.map.ncd with current fully routed design.
54 
 
55 
Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
56 
 
57 
Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
58 
 
59 
Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
60 
 
61 
Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
62 
 
63 
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs
64 
 
65 
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 24 secs
66 
Total REAL time to Router completion: 5 mins 24 secs
67 
Total CPU time to Router completion: 5 mins 13 secs
68 
 
69 
Partition Implementation Status
70 
-------------------------------
71 
 
72 
  No Partitions were found in this design.
73 
 
74 
-------------------------------
75 
 
76 
Generating "PAR" statistics.
77 
 
78 
**************************
79 
Generating Clock Report
80 
**************************
81 
 
82 
+---------------------+--------------+------+------+------------+-------------+
83 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
84 
+---------------------+--------------+------+------+------------+-------------+
85 
|         clk_i_BUFGP | BUFGCTRL_X0Y1| No   | 3403 |  0.334     |  1.843      |
86 
+---------------------+--------------+------+------+------------+-------------+
87 
 
88 
* Net Skew is the difference between the minimum and maximum routing
89 
only delays for the net. Note this is different from Clock Skew which
90 
is reported in TRCE timing report. Clock Skew is the difference between
91 
the minimum and maximum path delays which includes logic delays.
92 
 
93 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
94 
 
95 
Asterisk (*) preceding a constraint indicates it was not met.
96 
   This may be due to a setup or hold violation.
97 
 
98 
----------------------------------------------------------------------------------------------------------
99 
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
100 
                                            |             |    Slack   | Achievable | Errors |    Score
101 
----------------------------------------------------------------------------------------------------------
102 
  TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH | SETUP       |     0.026ns|     2.974ns|       0|           0
103 
   50%                                      | HOLD        |     0.296ns|            |       0|           0
104 
------------------------------------------------------------------------------------------------------
105 
 
106 
 
107 
All constraints were met.
108 
 
109 
 
110 
Generating Pad Report.
111 
 
112 
All signals are completely routed.
113 
 
114 
Total REAL time to PAR completion: 5 mins 42 secs
115 
Total CPU time to PAR completion: 5 mins 30 secs
116 
 
117 
Peak Memory Usage:  425 MB
118 
 
119 
Placer: Placement generated during map.
120 
Routing: Completed - No errors found.
121 
Timing: Completed - No errors found.
122 
 
123 
Number of error messages: 0
124 
Number of warning messages: 0
125 
Number of info messages: 0
126 
 
127 
Writing design to file ../out/aes.map.ncd
128 
 
129 
 
130 
 
131 
PAR done!

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.