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[/] [aes_pipe/] [trunk/] [syn/] [Xilinx/] [log/] [aes.twr] - Blame information for rev 10

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Line No. Rev Author Line
1 10 subhasis25 
--------------------------------------------------------------------------------
2 
Release 11.1 Trace  (lin)
3 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4 
 
5 
/opt/Xilinx/11.1/ISE/bin/lin/unwrapped/trce -v 10 -fastpaths -xml
6 
../log/aes.twx ../out/aes.map.ncd -o ../log/aes.twr ../out/aes.pcf
7 
 
8 
Design file:              aes.map.ncd
9 
Physical constraint file: aes.pcf
10 
Device,package,speed:     xc5vlx50t,ff1136,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
11 
Report level:             verbose report, limited to 10 items per constraint
12 
 
13 
Environment Variable      Effect
14 
--------------------      ------
15 
NONE                      No environment variables were set
16 
--------------------------------------------------------------------------------
17 
 
18 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
19 
   option. All paths that are not constrained will be reported in the
20 
   unconstrained paths section(s) of the report.
21 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
22 
   a 50 Ohm transmission line loading model.  For the details of this model,
23 
   and for more information on accounting for different loading conditions,
24 
   please see the device datasheet.
25 
 
26 
================================================================================
27 
Timing constraint: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
28 
 
29 
 59472 paths analyzed, 27896 endpoints analyzed, 0 failing endpoints
30 
 
31 
 Minimum period is   2.974ns.
32 
--------------------------------------------------------------------------------
33 
Slack (setup path):     0.026ns (requirement - (data path - clock path skew + uncertainty))
34 
  Source:               proc[0].mix/outrkey<2>_1_5 (FF)
35 
  Destination:          proc[1].add/dataout<2>_1_5 (FF)
36 
  Requirement:          3.000ns
37 
  Data Path Delay:      2.793ns (Levels of Logic = 1)
38 
  Clock Path Skew:      -0.146ns (1.244 - 1.390)
39 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
40 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
41 
  Clock Uncertainty:    0.035ns
42 
 
43 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
44 
    Total System Jitter (TSJ):  0.070ns
45 
    Total Input Jitter (TIJ):   0.000ns
46 
    Discrete Jitter (DJ):       0.000ns
47 
    Phase Error (PE):           0.000ns
48 
 
49 
  Maximum Data Path: proc[0].mix/outrkey<2>_1_5 to proc[1].add/dataout<2>_1_5
50 
    Location             Delay type         Delay(ns)  Physical Resource
51 
                                                       Logical Resource(s)
52 
    -------------------------------------------------  -------------------
53 
    SLICE_X20Y103.BQ     Tcko                  0.471   proc[0].mix/outrkey<2>_1_7
54 
                                                       proc[0].mix/outrkey<2>_1_5
55 
    SLICE_X47Y110.B6     net (fanout=4)        2.295   proc[0].mix/outrkey<2>_1_5
56 
    SLICE_X47Y110.CLK    Tas                   0.027   proc[1].add/dataout<2>_1_7
57 
                                                       proc[1].add/Mxor_added<2><1>_Result<5>1
58 
                                                       proc[1].add/dataout<2>_1_5
59 
    -------------------------------------------------  ---------------------------
60 
    Total                                      2.793ns (0.498ns logic, 2.295ns route)
61 
                                                       (17.8% logic, 82.2% route)
62 
 
63 
--------------------------------------------------------------------------------
64 
Slack (setup path):     0.026ns (requirement - (data path - clock path skew + uncertainty))
65 
  Source:               add_f_1/dataout<1>_1_1 (FF)
66 
  Destination:          sbox_f_1/g0[1].g1[1].sub/byteout_5 (FF)
67 
  Requirement:          3.000ns
68 
  Data Path Delay:      2.850ns (Levels of Logic = 2)
69 
  Clock Path Skew:      -0.089ns (1.226 - 1.315)
70 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
71 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
72 
  Clock Uncertainty:    0.035ns
73 
 
74 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
75 
    Total System Jitter (TSJ):  0.070ns
76 
    Total Input Jitter (TIJ):   0.000ns
77 
    Discrete Jitter (DJ):       0.000ns
78 
    Phase Error (PE):           0.000ns
79 
 
80 
  Maximum Data Path: add_f_1/dataout<1>_1_1 to sbox_f_1/g0[1].g1[1].sub/byteout_5
81 
    Location             Delay type         Delay(ns)  Physical Resource
82 
                                                       Logical Resource(s)
83 
    -------------------------------------------------  -------------------
84 
    SLICE_X52Y59.BQ      Tcko                  0.471   add_f_1/dataout<1>_1_3
85 
                                                       add_f_1/dataout<1>_1_1
86 
    SLICE_X59Y62.C1      net (fanout=32)       1.538   add_f_1/dataout<1>_1_1
87 
    SLICE_X59Y62.C       Tilo                  0.094   sbox_f_1/g0[2].g1[0].sub_Mrom_byteout_rom000022
88 
                                                       sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101
89 
    SLICE_X56Y61.B5      net (fanout=1)        0.546   sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101
90 
    SLICE_X56Y61.CLK     Tas                   0.201   sbox_f_1/g0[1].g1[1].sub/byteout<5>
91 
                                                       sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7
92 
                                                       sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7_rt
93 
                                                       sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f8
94 
                                                       sbox_f_1/g0[1].g1[1].sub/byteout_5
95 
    -------------------------------------------------  ---------------------------
96 
    Total                                      2.850ns (0.766ns logic, 2.084ns route)
97 
                                                       (26.9% logic, 73.1% route)
98 
 
99 
--------------------------------------------------------------------------------
100 
Slack (setup path):     0.027ns (requirement - (data path - clock path skew + uncertainty))
101 
  Source:               proc[3].add/dataout<3>_1_4 (FF)
102 
  Destination:          proc[3].sbox/g0[3].g1[1].sub/byteout_4 (FF)
103 
  Requirement:          3.000ns
104 
  Data Path Delay:      2.814ns (Levels of Logic = 2)
105 
  Clock Path Skew:      -0.124ns (1.168 - 1.292)
106 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
107 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
108 
  Clock Uncertainty:    0.035ns
109 
 
110 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
111 
    Total System Jitter (TSJ):  0.070ns
112 
    Total Input Jitter (TIJ):   0.000ns
113 
    Discrete Jitter (DJ):       0.000ns
114 
    Phase Error (PE):           0.000ns
115 
 
116 
  Maximum Data Path: proc[3].add/dataout<3>_1_4 to proc[3].sbox/g0[3].g1[1].sub/byteout_4
117 
    Location             Delay type         Delay(ns)  Physical Resource
118 
                                                       Logical Resource(s)
119 
    -------------------------------------------------  -------------------
120 
    SLICE_X24Y89.AQ      Tcko                  0.471   proc[3].add/dataout<3>_1_7
121 
                                                       proc[3].add/dataout<3>_1_4
122 
    SLICE_X29Y84.B1      net (fanout=32)       1.591   proc[3].add/dataout<3>_1_4
123 
    SLICE_X29Y84.B       Tilo                  0.094   proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
124 
                                                       proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
125 
    SLICE_X28Y84.D6      net (fanout=1)        0.433   proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
126 
    SLICE_X28Y84.CLK     Tas                   0.225   proc[3].sbox/g0[3].g1[1].sub/byteout<4>
127 
                                                       proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f7_0
128 
                                                       proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f71_rt
129 
                                                       proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f8
130 
                                                       proc[3].sbox/g0[3].g1[1].sub/byteout_4
131 
    -------------------------------------------------  ---------------------------
132 
    Total                                      2.814ns (0.790ns logic, 2.024ns route)
133 
                                                       (28.1% logic, 71.9% route)
134 
 
135 
--------------------------------------------------------------------------------
136 
Slack (setup path):     0.029ns (requirement - (data path - clock path skew + uncertainty))
137 
  Source:               proc[4].add/dataout<0>_3_5 (FF)
138 
  Destination:          proc[4].sbox/g0[0].g1[3].sub/byteout_1 (FF)
139 
  Requirement:          3.000ns
140 
  Data Path Delay:      2.833ns (Levels of Logic = 2)
141 
  Clock Path Skew:      -0.103ns (1.169 - 1.272)
142 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
143 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
144 
  Clock Uncertainty:    0.035ns
145 
 
146 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
147 
    Total System Jitter (TSJ):  0.070ns
148 
    Total Input Jitter (TIJ):   0.000ns
149 
    Discrete Jitter (DJ):       0.000ns
150 
    Phase Error (PE):           0.000ns
151 
 
152 
  Maximum Data Path: proc[4].add/dataout<0>_3_5 to proc[4].sbox/g0[0].g1[3].sub/byteout_1
153 
    Location             Delay type         Delay(ns)  Physical Resource
154 
                                                       Logical Resource(s)
155 
    -------------------------------------------------  -------------------
156 
    SLICE_X24Y60.BQ      Tcko                  0.471   proc[4].add/dataout<0>_3_7
157 
                                                       proc[4].add/dataout<0>_3_5
158 
    SLICE_X19Y52.A4      net (fanout=32)       1.447   proc[4].add/dataout<0>_3_5
159 
    SLICE_X19Y52.A       Tilo                  0.094   proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom0000141
160 
                                                       proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024
161 
    SLICE_X15Y51.D6      net (fanout=1)        0.569   proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024
162 
    SLICE_X15Y51.CLK     Tas                   0.252   proc[4].sbox/g0[0].g1[3].sub/byteout<1>
163 
                                                       proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f7_0
164 
                                                       proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f71_rt
165 
                                                       proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f8
166 
                                                       proc[4].sbox/g0[0].g1[3].sub/byteout_1
167 
    -------------------------------------------------  ---------------------------
168 
    Total                                      2.833ns (0.817ns logic, 2.016ns route)
169 
                                                       (28.8% logic, 71.2% route)
170 
 
171 
--------------------------------------------------------------------------------
172 
Slack (setup path):     0.031ns (requirement - (data path - clock path skew + uncertainty))
173 
  Source:               proc[7].add/dataout<0>_1_4 (FF)
174 
  Destination:          proc[7].sbox/g0[0].g1[1].sub/byteout_3 (FF)
175 
  Requirement:          3.000ns
176 
  Data Path Delay:      2.875ns (Levels of Logic = 2)
177 
  Clock Path Skew:      -0.059ns (1.245 - 1.304)
178 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
179 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
180 
  Clock Uncertainty:    0.035ns
181 
 
182 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
183 
    Total System Jitter (TSJ):  0.070ns
184 
    Total Input Jitter (TIJ):   0.000ns
185 
    Discrete Jitter (DJ):       0.000ns
186 
    Phase Error (PE):           0.000ns
187 
 
188 
  Maximum Data Path: proc[7].add/dataout<0>_1_4 to proc[7].sbox/g0[0].g1[1].sub/byteout_3
189 
    Location             Delay type         Delay(ns)  Physical Resource
190 
                                                       Logical Resource(s)
191 
    -------------------------------------------------  -------------------
192 
    SLICE_X29Y13.AQ      Tcko                  0.450   proc[7].add/dataout<0>_1_7
193 
                                                       proc[7].add/dataout<0>_1_4
194 
    SLICE_X27Y8.A1       net (fanout=32)       1.693   proc[7].add/dataout<0>_1_4
195 
    SLICE_X27Y8.A        Tilo                  0.094   proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
196 
                                                       proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
197 
    SLICE_X27Y10.D5      net (fanout=1)        0.386   proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
198 
    SLICE_X27Y10.CLK     Tas                   0.252   proc[7].sbox/g0[0].g1[1].sub/byteout<3>
199 
                                                       proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f7_0
200 
                                                       proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f71_rt
201 
                                                       proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f8
202 
                                                       proc[7].sbox/g0[0].g1[1].sub/byteout_3
203 
    -------------------------------------------------  ---------------------------
204 
    Total                                      2.875ns (0.796ns logic, 2.079ns route)
205 
                                                       (27.7% logic, 72.3% route)
206 
 
207 
--------------------------------------------------------------------------------
208 
Slack (setup path):     0.036ns (requirement - (data path - clock path skew + uncertainty))
209 
  Source:               proc[8].add/dataout<1>_3_4 (FF)
210 
  Destination:          proc[8].sbox/g0[1].g1[3].sub/byteout_3 (FF)
211 
  Requirement:          3.000ns
212 
  Data Path Delay:      2.786ns (Levels of Logic = 2)
213 
  Clock Path Skew:      -0.143ns (1.130 - 1.273)
214 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
215 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
216 
  Clock Uncertainty:    0.035ns
217 
 
218 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
219 
    Total System Jitter (TSJ):  0.070ns
220 
    Total Input Jitter (TIJ):   0.000ns
221 
    Discrete Jitter (DJ):       0.000ns
222 
    Phase Error (PE):           0.000ns
223 
 
224 
  Maximum Data Path: proc[8].add/dataout<1>_3_4 to proc[8].sbox/g0[1].g1[3].sub/byteout_3
225 
    Location             Delay type         Delay(ns)  Physical Resource
226 
                                                       Logical Resource(s)
227 
    -------------------------------------------------  -------------------
228 
    SLICE_X36Y35.AQ      Tcko                  0.471   proc[8].add/dataout<1>_3_7
229 
                                                       proc[8].add/dataout<1>_3_4
230 
    SLICE_X35Y42.C3      net (fanout=32)       1.552   proc[8].add/dataout<1>_3_4
231 
    SLICE_X35Y42.C       Tilo                  0.094   sbox_f_1/g0[3].g1[2].sub_Mrom_byteout_rom000083
232 
                                                       proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063
233 
    SLICE_X32Y42.D6      net (fanout=1)        0.444   proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063
234 
    SLICE_X32Y42.CLK     Tas                   0.225   proc[8].sbox/g0[1].g1[3].sub/byteout<3>
235 
                                                       proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f7_0
236 
                                                       proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f71_rt
237 
                                                       proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f8
238 
                                                       proc[8].sbox/g0[1].g1[3].sub/byteout_3
239 
    -------------------------------------------------  ---------------------------
240 
    Total                                      2.786ns (0.790ns logic, 1.996ns route)
241 
                                                       (28.4% logic, 71.6% route)
242 
 
243 
--------------------------------------------------------------------------------
244 
Slack (setup path):     0.036ns (requirement - (data path - clock path skew + uncertainty))
245 
  Source:               proc[8].mix/g0[1].mix/out2_2 (FF)
246 
  Destination:          add_f_1/dataout<2>_1_2 (FF)
247 
  Requirement:          3.000ns
248 
  Data Path Delay:      2.762ns (Levels of Logic = 1)
249 
  Clock Path Skew:      -0.167ns (1.208 - 1.375)
250 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
251 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
252 
  Clock Uncertainty:    0.035ns
253 
 
254 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
255 
    Total System Jitter (TSJ):  0.070ns
256 
    Total Input Jitter (TIJ):   0.000ns
257 
    Discrete Jitter (DJ):       0.000ns
258 
    Phase Error (PE):           0.000ns
259 
 
260 
  Maximum Data Path: proc[8].mix/g0[1].mix/out2_2 to add_f_1/dataout<2>_1_2
261 
    Location             Delay type         Delay(ns)  Physical Resource
262 
                                                       Logical Resource(s)
263 
    -------------------------------------------------  -------------------
264 
    SLICE_X55Y36.CQ      Tcko                  0.450   proc[8].mix/g0[1].mix/out2<5>
265 
                                                       proc[8].mix/g0[1].mix/out2_2
266 
    SLICE_X57Y73.C5      net (fanout=1)        2.283   proc[8].mix/g0[1].mix/out2<2>
267 
    SLICE_X57Y73.CLK     Tas                   0.029   add_f_1/dataout<2>_1_3
268 
                                                       add_f_1/Mxor_added<2><1>_Result<2>1
269 
                                                       add_f_1/dataout<2>_1_2
270 
    -------------------------------------------------  ---------------------------
271 
    Total                                      2.762ns (0.479ns logic, 2.283ns route)
272 
                                                       (17.3% logic, 82.7% route)
273 
 
274 
--------------------------------------------------------------------------------
275 
Slack (setup path):     0.040ns (requirement - (data path - clock path skew + uncertainty))
276 
  Source:               proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)
277 
  Destination:          proc[5].mix/g0[0].mix/out1_3 (FF)
278 
  Requirement:          3.000ns
279 
  Data Path Delay:      2.871ns (Levels of Logic = 1)
280 
  Clock Path Skew:      -0.054ns (1.331 - 1.385)
281 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
282 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
283 
  Clock Uncertainty:    0.035ns
284 
 
285 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
286 
    Total System Jitter (TSJ):  0.070ns
287 
    Total Input Jitter (TIJ):   0.000ns
288 
    Discrete Jitter (DJ):       0.000ns
289 
    Phase Error (PE):           0.000ns
290 
 
291 
  Maximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3
292 
    Location             Delay type         Delay(ns)  Physical Resource
293 
                                                       Logical Resource(s)
294 
    -------------------------------------------------  -------------------
295 
    SLICE_X0Y32.BQ       Tcko                  0.471   proc[5].sbox/g0[1].g1[1].sub/byteout<2>
296 
                                                       proc[5].sbox/g0[1].g1[1].sub/byteout_2
297 
    SLICE_X10Y18.A6      net (fanout=7)        2.253   proc[5].sbox/g0[1].g1[1].sub/byteout<2>
298 
    SLICE_X10Y18.CLK     Tas                   0.147   proc[5].mix/g0[0].mix/out1<3>
299 
                                                       proc[5].mix/g0[0].mix/out1_xor0000<3>1
300 
                                                       proc[5].mix/g0[0].mix/out1_xor0000<3>_f7
301 
                                                       proc[5].mix/g0[0].mix/out1_3
302 
    -------------------------------------------------  ---------------------------
303 
    Total                                      2.871ns (0.618ns logic, 2.253ns route)
304 
                                                       (21.5% logic, 78.5% route)
305 
 
306 
--------------------------------------------------------------------------------
307 
Slack (setup path):     0.041ns (requirement - (data path - clock path skew + uncertainty))
308 
  Source:               proc[6].add/dataout<2>_0_5 (FF)
309 
  Destination:          proc[6].sbox/g0[2].g1[0].sub/byteout_4 (FF)
310 
  Requirement:          3.000ns
311 
  Data Path Delay:      2.742ns (Levels of Logic = 2)
312 
  Clock Path Skew:      -0.182ns (1.254 - 1.436)
313 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
314 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
315 
  Clock Uncertainty:    0.035ns
316 
 
317 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
318 
    Total System Jitter (TSJ):  0.070ns
319 
    Total Input Jitter (TIJ):   0.000ns
320 
    Discrete Jitter (DJ):       0.000ns
321 
    Phase Error (PE):           0.000ns
322 
 
323 
  Maximum Data Path: proc[6].add/dataout<2>_0_5 to proc[6].sbox/g0[2].g1[0].sub/byteout_4
324 
    Location             Delay type         Delay(ns)  Physical Resource
325 
                                                       Logical Resource(s)
326 
    -------------------------------------------------  -------------------
327 
    SLICE_X14Y16.BQ      Tcko                  0.450   proc[6].add/dataout<2>_0_7
328 
                                                       proc[6].add/dataout<2>_0_5
329 
    SLICE_X20Y20.C2      net (fanout=32)       1.524   proc[6].add/dataout<2>_0_5
330 
    SLICE_X20Y20.C       Tilo                  0.094   proc[6].sbox/g0[2].g1[0].sub/byteout<4>
331 
                                                       proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082
332 
    SLICE_X20Y20.D6      net (fanout=1)        0.449   proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082
333 
    SLICE_X20Y20.CLK     Tas                   0.225   proc[6].sbox/g0[2].g1[0].sub/byteout<4>
334 
                                                       proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f7_0
335 
                                                       proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f71_rt
336 
                                                       proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f8
337 
                                                       proc[6].sbox/g0[2].g1[0].sub/byteout_4
338 
    -------------------------------------------------  ---------------------------
339 
    Total                                      2.742ns (0.769ns logic, 1.973ns route)
340 
                                                       (28.0% logic, 72.0% route)
341 
 
342 
--------------------------------------------------------------------------------
343 
Slack (setup path):     0.041ns (requirement - (data path - clock path skew + uncertainty))
344 
  Source:               proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)
345 
  Destination:          proc[5].mix/g0[0].mix/out1_3 (FF)
346 
  Requirement:          3.000ns
347 
  Data Path Delay:      2.870ns (Levels of Logic = 1)
348 
  Clock Path Skew:      -0.054ns (1.331 - 1.385)
349 
  Source Clock:         clk_i_BUFGP rising at 0.000ns
350 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
351 
  Clock Uncertainty:    0.035ns
352 
 
353 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
354 
    Total System Jitter (TSJ):  0.070ns
355 
    Total Input Jitter (TIJ):   0.000ns
356 
    Discrete Jitter (DJ):       0.000ns
357 
    Phase Error (PE):           0.000ns
358 
 
359 
  Maximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3
360 
    Location             Delay type         Delay(ns)  Physical Resource
361 
                                                       Logical Resource(s)
362 
    -------------------------------------------------  -------------------
363 
    SLICE_X0Y32.BQ       Tcko                  0.471   proc[5].sbox/g0[1].g1[1].sub/byteout<2>
364 
                                                       proc[5].sbox/g0[1].g1[1].sub/byteout_2
365 
    SLICE_X10Y18.B6      net (fanout=7)        2.260   proc[5].sbox/g0[1].g1[1].sub/byteout<2>
366 
    SLICE_X10Y18.CLK     Tas                   0.139   proc[5].mix/g0[0].mix/out1<3>
367 
                                                       proc[5].mix/g0[0].mix/out1_xor0000<3>2
368 
                                                       proc[5].mix/g0[0].mix/out1_xor0000<3>_f7
369 
                                                       proc[5].mix/g0[0].mix/out1_3
370 
    -------------------------------------------------  ---------------------------
371 
    Total                                      2.870ns (0.610ns logic, 2.260ns route)
372 
                                                       (21.3% logic, 78.7% route)
373 
 
374 
--------------------------------------------------------------------------------
375 
 
376 
Hold Paths: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
377 
--------------------------------------------------------------------------------
378 
Slack (hold path):      0.296ns (requirement - (clock path skew + uncertainty - data path))
379 
  Source:               proc[0].sbox/nextkey<0>_2_5 (FF)
380 
  Destination:          proc[0].mix/outrkey<0>_2_5 (FF)
381 
  Requirement:          0.000ns
382 
  Data Path Delay:      0.452ns (Levels of Logic = 0)
383 
  Clock Path Skew:      0.156ns (1.377 - 1.221)
384 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
385 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
386 
  Clock Uncertainty:    0.000ns
387 
 
388 
  Minimum Data Path: proc[0].sbox/nextkey<0>_2_5 to proc[0].mix/outrkey<0>_2_5
389 
    Location             Delay type         Delay(ns)  Physical Resource
390 
                                                       Logical Resource(s)
391 
    -------------------------------------------------  -------------------
392 
    SLICE_X55Y79.BQ      Tcko                  0.414   proc[0].sbox/nextkey<0>_2_7
393 
                                                       proc[0].sbox/nextkey<0>_2_5
394 
    SLICE_X56Y80.BX      net (fanout=1)        0.280   proc[0].sbox/nextkey<0>_2_5
395 
    SLICE_X56Y80.CLK     Tckdi       (-Th)     0.242   proc[0].mix/outrkey<0>_2_7
396 
                                                       proc[0].mix/outrkey<0>_2_5
397 
    -------------------------------------------------  ---------------------------
398 
    Total                                      0.452ns (0.172ns logic, 0.280ns route)
399 
                                                       (38.1% logic, 61.9% route)
400 
 
401 
--------------------------------------------------------------------------------
402 
Slack (hold path):      0.339ns (requirement - (clock path skew + uncertainty - data path))
403 
  Source:               proc[1].sbox/nextkey<0>_0_5 (FF)
404 
  Destination:          proc[1].mix/outrkey<0>_0_5 (FF)
405 
  Requirement:          0.000ns
406 
  Data Path Delay:      0.472ns (Levels of Logic = 0)
407 
  Clock Path Skew:      0.133ns (1.348 - 1.215)
408 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
409 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
410 
  Clock Uncertainty:    0.000ns
411 
 
412 
  Minimum Data Path: proc[1].sbox/nextkey<0>_0_5 to proc[1].mix/outrkey<0>_0_5
413 
    Location             Delay type         Delay(ns)  Physical Resource
414 
                                                       Logical Resource(s)
415 
    -------------------------------------------------  -------------------
416 
    SLICE_X43Y99.BQ      Tcko                  0.414   proc[1].sbox/nextkey<0>_0_7
417 
                                                       proc[1].sbox/nextkey<0>_0_5
418 
    SLICE_X43Y101.BX     net (fanout=1)        0.289   proc[1].sbox/nextkey<0>_0_5
419 
    SLICE_X43Y101.CLK    Tckdi       (-Th)     0.231   proc[1].mix/outrkey<0>_0_7
420 
                                                       proc[1].mix/outrkey<0>_0_5
421 
    -------------------------------------------------  ---------------------------
422 
    Total                                      0.472ns (0.183ns logic, 0.289ns route)
423 
                                                       (38.8% logic, 61.2% route)
424 
 
425 
--------------------------------------------------------------------------------
426 
Slack (hold path):      0.412ns (requirement - (clock path skew + uncertainty - data path))
427 
  Source:               proc[0].add/step1/sub1/byteout_5 (FF)
428 
  Destination:          proc[0].sbox/nextkey<0>_0_5 (FF)
429 
  Requirement:          0.000ns
430 
  Data Path Delay:      0.499ns (Levels of Logic = 1)
431 
  Clock Path Skew:      0.087ns (0.577 - 0.490)
432 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
433 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
434 
  Clock Uncertainty:    0.000ns
435 
 
436 
  Minimum Data Path: proc[0].add/step1/sub1/byteout_5 to proc[0].sbox/nextkey<0>_0_5
437 
    Location             Delay type         Delay(ns)  Physical Resource
438 
                                                       Logical Resource(s)
439 
    -------------------------------------------------  -------------------
440 
    SLICE_X45Y79.BQ      Tcko                  0.414   proc[0].add/step1/sub1/byteout<5>
441 
                                                       proc[0].add/step1/sub1/byteout_5
442 
    SLICE_X46Y79.B6      net (fanout=4)        0.281   proc[0].add/step1/sub1/byteout<5>
443 
    SLICE_X46Y79.CLK     Tah         (-Th)     0.196   proc[0].sbox/nextkey<0>_0_7
444 
                                                       proc[0].sbox/Mxor_nextkey<0>_0_xor0000_Result<5>1
445 
                                                       proc[0].sbox/nextkey<0>_0_5
446 
    -------------------------------------------------  ---------------------------
447 
    Total                                      0.499ns (0.218ns logic, 0.281ns route)
448 
                                                       (43.7% logic, 56.3% route)
449 
 
450 
--------------------------------------------------------------------------------
451 
Slack (hold path):      0.419ns (requirement - (clock path skew + uncertainty - data path))
452 
  Source:               proc[1].sbox/nextkey<1>_1_2 (FF)
453 
  Destination:          proc[1].mix/outrkey<1>_1_2 (FF)
454 
  Requirement:          0.000ns
455 
  Data Path Delay:      0.491ns (Levels of Logic = 0)
456 
  Clock Path Skew:      0.072ns (0.543 - 0.471)
457 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
458 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
459 
  Clock Uncertainty:    0.000ns
460 
 
461 
  Minimum Data Path: proc[1].sbox/nextkey<1>_1_2 to proc[1].mix/outrkey<1>_1_2
462 
    Location             Delay type         Delay(ns)  Physical Resource
463 
                                                       Logical Resource(s)
464 
    -------------------------------------------------  -------------------
465 
    SLICE_X27Y108.CQ     Tcko                  0.414   proc[1].sbox/nextkey<1>_1_3
466 
                                                       proc[1].sbox/nextkey<1>_1_2
467 
    SLICE_X22Y108.CX     net (fanout=1)        0.295   proc[1].sbox/nextkey<1>_1_2
468 
    SLICE_X22Y108.CLK    Tckdi       (-Th)     0.218   proc[1].mix/outrkey<1>_1_3
469 
                                                       proc[1].mix/outrkey<1>_1_2
470 
    -------------------------------------------------  ---------------------------
471 
    Total                                      0.491ns (0.196ns logic, 0.295ns route)
472 
                                                       (39.9% logic, 60.1% route)
473 
 
474 
--------------------------------------------------------------------------------
475 
Slack (hold path):      0.420ns (requirement - (clock path skew + uncertainty - data path))
476 
  Source:               proc[6].add/step1/c0_3_4 (FF)
477 
  Destination:          proc[6].sbox/nextkey<3>_0_4 (FF)
478 
  Requirement:          0.000ns
479 
  Data Path Delay:      0.474ns (Levels of Logic = 1)
480 
  Clock Path Skew:      0.054ns (0.493 - 0.439)
481 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
482 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
483 
  Clock Uncertainty:    0.000ns
484 
 
485 
  Minimum Data Path: proc[6].add/step1/c0_3_4 to proc[6].sbox/nextkey<3>_0_4
486 
    Location             Delay type         Delay(ns)  Physical Resource
487 
                                                       Logical Resource(s)
488 
    -------------------------------------------------  -------------------
489 
    SLICE_X31Y24.AQ      Tcko                  0.414   proc[6].add/step1/c0_3_7
490 
                                                       proc[6].add/step1/c0_3_4
491 
    SLICE_X33Y24.A6      net (fanout=1)        0.257   proc[6].add/step1/c0_3_4
492 
    SLICE_X33Y24.CLK     Tah         (-Th)     0.197   proc[6].sbox/nextkey<3>_0_7
493 
                                                       proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1
494 
                                                       proc[6].sbox/nextkey<3>_0_4
495 
    -------------------------------------------------  ---------------------------
496 
    Total                                      0.474ns (0.217ns logic, 0.257ns route)
497 
                                                       (45.8% logic, 54.2% route)
498 
 
499 
--------------------------------------------------------------------------------
500 
Slack (hold path):      0.421ns (requirement - (clock path skew + uncertainty - data path))
501 
  Source:               proc[8].add/step1/c0_3_0 (FF)
502 
  Destination:          proc[8].sbox/nextkey<3>_0_0 (FF)
503 
  Requirement:          0.000ns
504 
  Data Path Delay:      0.461ns (Levels of Logic = 1)
505 
  Clock Path Skew:      0.040ns (0.546 - 0.506)
506 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
507 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
508 
  Clock Uncertainty:    0.000ns
509 
 
510 
  Minimum Data Path: proc[8].add/step1/c0_3_0 to proc[8].sbox/nextkey<3>_0_0
511 
    Location             Delay type         Delay(ns)  Physical Resource
512 
                                                       Logical Resource(s)
513 
    -------------------------------------------------  -------------------
514 
    SLICE_X51Y36.AQ      Tcko                  0.414   proc[8].add/step1/c0_3_3
515 
                                                       proc[8].add/step1/c0_3_0
516 
    SLICE_X48Y36.A6      net (fanout=1)        0.266   proc[8].add/step1/c0_3_0
517 
    SLICE_X48Y36.CLK     Tah         (-Th)     0.219   proc[8].sbox/nextkey<3>_0_3
518 
                                                       proc[8].sbox/Mxor_nextkey<3>_0_xor0000_Result<0>1
519 
                                                       proc[8].sbox/nextkey<3>_0_0
520 
    -------------------------------------------------  ---------------------------
521 
    Total                                      0.461ns (0.195ns logic, 0.266ns route)
522 
                                                       (42.3% logic, 57.7% route)
523 
 
524 
--------------------------------------------------------------------------------
525 
Slack (hold path):      0.422ns (requirement - (clock path skew + uncertainty - data path))
526 
  Source:               proc[3].add/step1/c0_3_4 (FF)
527 
  Destination:          proc[3].sbox/nextkey<3>_0_4 (FF)
528 
  Requirement:          0.000ns
529 
  Data Path Delay:      0.480ns (Levels of Logic = 1)
530 
  Clock Path Skew:      0.058ns (0.470 - 0.412)
531 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
532 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
533 
  Clock Uncertainty:    0.000ns
534 
 
535 
  Minimum Data Path: proc[3].add/step1/c0_3_4 to proc[3].sbox/nextkey<3>_0_4
536 
    Location             Delay type         Delay(ns)  Physical Resource
537 
                                                       Logical Resource(s)
538 
    -------------------------------------------------  -------------------
539 
    SLICE_X33Y70.AQ      Tcko                  0.414   proc[3].add/step1/c0_3_7
540 
                                                       proc[3].add/step1/c0_3_4
541 
    SLICE_X30Y70.A6      net (fanout=1)        0.263   proc[3].add/step1/c0_3_4
542 
    SLICE_X30Y70.CLK     Tah         (-Th)     0.197   proc[3].sbox/nextkey<3>_0_7
543 
                                                       proc[3].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1
544 
                                                       proc[3].sbox/nextkey<3>_0_4
545 
    -------------------------------------------------  ---------------------------
546 
    Total                                      0.480ns (0.217ns logic, 0.263ns route)
547 
                                                       (45.2% logic, 54.8% route)
548 
 
549 
--------------------------------------------------------------------------------
550 
Slack (hold path):      0.422ns (requirement - (clock path skew + uncertainty - data path))
551 
  Source:               proc[6].mix/g0[2].mix/out1_1 (FF)
552 
  Destination:          proc[7].add/dataout<1>_2_1 (FF)
553 
  Requirement:          0.000ns
554 
  Data Path Delay:      0.464ns (Levels of Logic = 1)
555 
  Clock Path Skew:      0.042ns (0.542 - 0.500)
556 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
557 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
558 
  Clock Uncertainty:    0.000ns
559 
 
560 
  Minimum Data Path: proc[6].mix/g0[2].mix/out1_1 to proc[7].add/dataout<1>_2_1
561 
    Location             Delay type         Delay(ns)  Physical Resource
562 
                                                       Logical Resource(s)
563 
    -------------------------------------------------  -------------------
564 
    SLICE_X27Y20.AQ      Tcko                  0.414   proc[6].mix/g0[2].mix/out1<2>
565 
                                                       proc[6].mix/g0[2].mix/out1_1
566 
    SLICE_X24Y20.B6      net (fanout=1)        0.272   proc[6].mix/g0[2].mix/out1<1>
567 
    SLICE_X24Y20.CLK     Tah         (-Th)     0.222   proc[7].add/dataout<1>_2_3
568 
                                                       proc[7].add/Mxor_added<1><2>_Result<1>1
569 
                                                       proc[7].add/dataout<1>_2_1
570 
    -------------------------------------------------  ---------------------------
571 
    Total                                      0.464ns (0.192ns logic, 0.272ns route)
572 
                                                       (41.4% logic, 58.6% route)
573 
 
574 
--------------------------------------------------------------------------------
575 
Slack (hold path):      0.422ns (requirement - (clock path skew + uncertainty - data path))
576 
  Source:               add_f_1/step1/c2_3_2 (FF)
577 
  Destination:          sbox_f_1/nextkey<3>_2_2 (FF)
578 
  Requirement:          0.000ns
579 
  Data Path Delay:      0.486ns (Levels of Logic = 1)
580 
  Clock Path Skew:      0.064ns (0.559 - 0.495)
581 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
582 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
583 
  Clock Uncertainty:    0.000ns
584 
 
585 
  Minimum Data Path: add_f_1/step1/c2_3_2 to sbox_f_1/nextkey<3>_2_2
586 
    Location             Delay type         Delay(ns)  Physical Resource
587 
                                                       Logical Resource(s)
588 
    -------------------------------------------------  -------------------
589 
    SLICE_X49Y45.CQ      Tcko                  0.414   add_f_1/step1/c2_3_3
590 
                                                       add_f_1/step1/c2_3_2
591 
    SLICE_X50Y44.C6      net (fanout=1)        0.267   add_f_1/step1/c2_3_2
592 
    SLICE_X50Y44.CLK     Tah         (-Th)     0.195   sbox_f_1/nextkey<3>_2_3
593 
                                                       sbox_f_1/Mxor_nextkey<3>_2_xor0000_Result<2>1
594 
                                                       sbox_f_1/nextkey<3>_2_2
595 
    -------------------------------------------------  ---------------------------
596 
    Total                                      0.486ns (0.219ns logic, 0.267ns route)
597 
                                                       (45.1% logic, 54.9% route)
598 
 
599 
--------------------------------------------------------------------------------
600 
Slack (hold path):      0.423ns (requirement - (clock path skew + uncertainty - data path))
601 
  Source:               proc[6].add/step1/c0_3_7 (FF)
602 
  Destination:          proc[6].sbox/nextkey<3>_0_7 (FF)
603 
  Requirement:          0.000ns
604 
  Data Path Delay:      0.477ns (Levels of Logic = 1)
605 
  Clock Path Skew:      0.054ns (0.493 - 0.439)
606 
  Source Clock:         clk_i_BUFGP rising at 3.000ns
607 
  Destination Clock:    clk_i_BUFGP rising at 3.000ns
608 
  Clock Uncertainty:    0.000ns
609 
 
610 
  Minimum Data Path: proc[6].add/step1/c0_3_7 to proc[6].sbox/nextkey<3>_0_7
611 
    Location             Delay type         Delay(ns)  Physical Resource
612 
                                                       Logical Resource(s)
613 
    -------------------------------------------------  -------------------
614 
    SLICE_X31Y24.DQ      Tcko                  0.414   proc[6].add/step1/c0_3_7
615 
                                                       proc[6].add/step1/c0_3_7
616 
    SLICE_X33Y24.D6      net (fanout=1)        0.258   proc[6].add/step1/c0_3_7
617 
    SLICE_X33Y24.CLK     Tah         (-Th)     0.195   proc[6].sbox/nextkey<3>_0_7
618 
                                                       proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<7>1
619 
                                                       proc[6].sbox/nextkey<3>_0_7
620 
    -------------------------------------------------  ---------------------------
621 
    Total                                      0.477ns (0.219ns logic, 0.258ns route)
622 
                                                       (45.9% logic, 54.1% route)
623 
 
624 
--------------------------------------------------------------------------------
625 
 
626 
Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
627 
--------------------------------------------------------------------------------
628 
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
629 
  Period: 3.000ns
630 
  Low pulse: 1.500ns
631 
  Low pulse limit: 0.527ns (Trpw)
632 
  Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SR
633 
  Logical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR
634 
  Location pin: SLICE_X38Y26.SR
635 
  Clock network: rst_i_BUFGP
636 
--------------------------------------------------------------------------------
637 
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
638 
  Period: 3.000ns
639 
  High pulse: 1.500ns
640 
  High pulse limit: 0.527ns (Trpw)
641 
  Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SR
642 
  Logical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR
643 
  Location pin: SLICE_X38Y26.SR
644 
  Clock network: rst_i_BUFGP
645 
--------------------------------------------------------------------------------
646 
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
647 
  Period: 3.000ns
648 
  Low pulse: 1.500ns
649 
  Low pulse limit: 0.527ns (Trpw)
650 
  Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SR
651 
  Logical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR
652 
  Location pin: SLICE_X59Y24.SR
653 
  Clock network: rst_i_BUFGP
654 
--------------------------------------------------------------------------------
655 
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
656 
  Period: 3.000ns
657 
  High pulse: 1.500ns
658 
  High pulse limit: 0.527ns (Trpw)
659 
  Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SR
660 
  Logical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR
661 
  Location pin: SLICE_X59Y24.SR
662 
  Clock network: rst_i_BUFGP
663 
--------------------------------------------------------------------------------
664 
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
665 
  Period: 3.000ns
666 
  Low pulse: 1.500ns
667 
  Low pulse limit: 0.527ns (Trpw)
668 
  Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SR
669 
  Logical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR
670 
  Location pin: SLICE_X58Y42.SR
671 
  Clock network: rst_i_BUFGP
672 
--------------------------------------------------------------------------------
673 
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
674 
  Period: 3.000ns
675 
  High pulse: 1.500ns
676 
  High pulse limit: 0.527ns (Trpw)
677 
  Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SR
678 
  Logical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR
679 
  Location pin: SLICE_X58Y42.SR
680 
  Clock network: rst_i_BUFGP
681 
--------------------------------------------------------------------------------
682 
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
683 
  Period: 3.000ns
684 
  Low pulse: 1.500ns
685 
  Low pulse limit: 0.527ns (Trpw)
686 
  Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SR
687 
  Logical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR
688 
  Location pin: SLICE_X42Y7.SR
689 
  Clock network: rst_i_BUFGP
690 
--------------------------------------------------------------------------------
691 
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
692 
  Period: 3.000ns
693 
  High pulse: 1.500ns
694 
  High pulse limit: 0.527ns (Trpw)
695 
  Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SR
696 
  Logical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR
697 
  Location pin: SLICE_X42Y7.SR
698 
  Clock network: rst_i_BUFGP
699 
--------------------------------------------------------------------------------
700 
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
701 
  Period: 3.000ns
702 
  Low pulse: 1.500ns
703 
  Low pulse limit: 0.527ns (Trpw)
704 
  Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SR
705 
  Logical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR
706 
  Location pin: SLICE_X33Y11.SR
707 
  Clock network: rst_i_BUFGP
708 
--------------------------------------------------------------------------------
709 
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
710 
  Period: 3.000ns
711 
  High pulse: 1.500ns
712 
  High pulse limit: 0.527ns (Trpw)
713 
  Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SR
714 
  Logical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR
715 
  Location pin: SLICE_X33Y11.SR
716 
  Clock network: rst_i_BUFGP
717 
--------------------------------------------------------------------------------
718 
 
719 
 
720 
All constraints were met.
721 
 
722 
 
723 
Data Sheet report:
724 
-----------------
725 
All values displayed in nanoseconds (ns)
726 
 
727 
Clock to Setup on destination clock clk_i
728 
---------------+---------+---------+---------+---------+
729 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
730 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
731 
---------------+---------+---------+---------+---------+
732 
clk_i          |    2.974|         |         |         |
733 
---------------+---------+---------+---------+---------+
734 
 
735 
 
736 
Timing summary:
737 
---------------
738 
 
739 
Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
740 
 
741 
Constraints cover 59472 paths, 0 nets, and 69148 connections
742 
 
743 
Design statistics:
744 
   Minimum period:   2.974ns{1}   (Maximum frequency: 336.247MHz)
745 
 
746 
 
747 
------------------------------------Footnotes-----------------------------------
748 
1)  The minimum period statistic assumes all single cycle delays.
749 
 
750 
Analysis completed Thu Mar 25 15:34:03 2010
751 
--------------------------------------------------------------------------------
752 
 
753 
Trace Settings:
754 
-------------------------
755 
Trace Settings
756 
 
757 
Peak Memory Usage: 381 MB
758 
 
759 
 
760 
 

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