OpenCores
URL https://opencores.org/ocsvn/ag_6502/ag_6502/trunk

Subversion Repositories ag_6502

[/] [ag_6502/] [trunk/] [digger/] [chip1.ucf] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 olegodints
 
2
 
3
NET "b1" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
4
NET "b2" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
5
NET "b3" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
6
NET "b4" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
7
 
8
NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33";
9
 
10
NET "ROT_A" LOC = K18 | IOSTANDARD = "LVTTL" | PULLUP;
11
NET "ROT_B" LOC = G18 | IOSTANDARD = "LVTTL" | PULLUP;
12
NET "ROT_CENTER" LOC = V16 | IOSTANDARD = "LVTTL" | PULLDOWN;
13
 
14
NET "LED<7>" LOC = F9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
15
NET "LED<6>" LOC = E9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
16
NET "LED<5>" LOC = D11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
17
NET "LED<4>" LOC = C11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
18
NET "LED<3>" LOC = F11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
19
NET "LED<2>" LOC = E11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
20
NET "LED<1>" LOC = E12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
21
NET "LED<0>" LOC = F12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
22
 
23
NET "VGA_RED" LOC = H14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
24
NET "VGA_GREEN" LOC = H15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
25
NET "VGA_BLUE" LOC = G15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
26
NET "VGA_HSYNC" LOC = F15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
27
NET "VGA_VSYNC" LOC = F14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
28
 
29
NET "J4<0>" LOC = D7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
30
NET "J4<1>" LOC = C7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
31
NET "J4<2>" LOC = F8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
32
NET "J4<3>" LOC = E8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
33
#Created by Constraints Editor (xc3s500e-fg320-4) - 2012/01/19
34
NET "clk" TNM_NET = clk;
35
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
36
 
37
#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
38
NET "SPI_MOSI" LOC = T4 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
39
NET "SPI_MISO" LOC = N10 | IOSTANDARD = "LVCMOS33";
40
NET "SPI_SCK" LOC = U16 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
41
NET "DAC_CS" LOC = N8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
42
NET "DAC_CLR" LOC = P8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
43
 
44
NET "spi_amp_cs" LOC = N7 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
45
NET "spi_rom_cs" LOC = U3 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
46
NET "platformflash_oe" LOC = T3 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
47
NET "strataflash_oe" LOC = C18 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
48
NET "strataflash_ce" LOC = D16 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
49
NET "strataflash_we" LOC = D17 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
50
NET "spi_adc_conv" LOC = P11 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
51
 
52
NET "PS2_CLK" LOC = G14  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
53
NET "PS2_DATA" LOC = G13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
54
NET "PS2_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
55
 
56
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
57
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
58
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
59
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.