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[/] [ag_6502/] [trunk/] [digger/] [chip1.v] - Blame information for rev 5

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1 5 olegodints
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:   BMSTU
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// Engineer:  Oleg Odintsov
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// 
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// Create Date:    18:21:00 01/17/2012 
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// Design Name: 
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// Project Name:    Agat Hardware Project
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rot_driver(input clk,
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                                input rot_a, input rot_b,
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                                output wire rot_dir, output wire rot_event_out);
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        reg rot_a_latch = 0, rot_b_latch = 0;
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        assign rot_dir = rot_b_latch, rot_event_out = rot_a_latch;
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        always @(posedge clk) begin
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                case ({rot_a, rot_b})
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                2'b00: rot_a_latch <= 1;
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                2'b11: rot_a_latch <= 0;
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                2'b10: rot_b_latch <= 1;
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                2'b01: rot_b_latch <= 0;
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                endcase
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        end
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endmodule
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module btn_driver(input clk, input btn, output reg sig = 0);
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        parameter nskip = 'hfff;
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        integer counter = 0;
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        wire lock = counter?1:0;
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        always @(posedge clk) begin
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                if (counter) counter <= counter - 1;
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                if (!lock && sig != btn) begin
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                        sig <= btn;
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                        counter <= nskip;
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                end
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        end
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endmodule
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module chip1(
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         input clk,
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    input b1,
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    input b2,
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    input b3,
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    input b4,
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         input[3:0] SW,
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         input rot_a, rot_b, rot_center,
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    output[7:0] led,
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    output vga_red,
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    output vga_green,
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    output vga_blue,
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    output vga_hsync,
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    output vga_vsync,
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         output [3:0]j4,
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         input spi_miso, output spi_mosi, output spi_sck, output dac_cs, output dac_clr,
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         output spi_rom_cs,
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         output spi_amp_cs,
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         output spi_adc_conv,
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         output strataflash_oe,
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         output strataflash_ce,
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    output strataflash_we,
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         output platformflash_oe,
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         input  ps2_clk,
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         input  ps2_data
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    );
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         // access to DAC
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         assign spi_mosi = 0, spi_sck = 0, dac_cs = 0, dac_clr = 0;
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         // block other devices to access to DAC
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         assign spi_rom_cs = 1, spi_amp_cs = 1, spi_adc_conv = 0;
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         assign strataflash_oe = 1, strataflash_ce = 1, strataflash_we = 1;
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         assign platformflash_oe = 0;
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         wire[4:0] vga_bus;
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         assign {vga_red, vga_green, vga_blue, vga_hsync, vga_vsync} = vga_bus;
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         wire[1:0] ps2_bus = {ps2_clk, ps2_data};
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         wire rot_dir, rot_event;
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         wire clk_cpu;
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         wire b1v, b2v, b3v, b4v, brc;
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         rot_driver rot(clk_cpu, rot_a, rot_b, rot_dir, rot_event);
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         btn_driver b1d(clk_cpu, b1, b1v);
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         btn_driver b2d(clk_cpu, b2, b2v);
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         btn_driver b3d(clk_cpu, b3, b3v);
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         btn_driver b4d(clk_cpu, b4, b4v);
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         btn_driver rrd(clk_cpu, rot_center, brc);
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         reg rot_v = 0;
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         always @(posedge rot_event) begin
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                rot_v <= rot_dir;
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         end
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//       assign j4 = 0, vga_bus = 0;
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         wire[4:0] btns = {brc, b4v | (rot_event & ~rot_v), b3v, b2v, b1v | (rot_event & rot_v)};
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         ag_main agate(clk, btns, SW, led, j4, vga_bus, ps2_bus, clk_cpu);
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endmodule

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