URL https://opencores.org/ocsvn/ag_6502/ag_6502/trunk

Subversion Repositories ag_6502

[/] [ag_6502/] [trunk/] [digger/] [clkdiv.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	olegodints	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 23:20:37 02/23/2012`
7			`// Design Name:`
8			`// Module Name: clkdiv`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22			`module clk_div(input clk, output clk1);`
23			`parameter divide = 16;`
24			`wire clk0;`
25
26			`DCM_SP #(`
27			`.CLKDV_DIVIDE(divide) // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
28			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
29			`) DCM_SP_inst (`
30			`.CLKDV(clk1), // Divided DCM CLK out (CLKDV_DIVIDE)`
31			`.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)`
32			`.CLK0(clk0),`
33			`.CLKFB(clk0),`
34			`.RST(0)`
35			`);`
36
37			`endmodule`