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[/] [ag_6502/] [trunk/] [fighter/] [ag_6502.v] - Blame information for rev 3

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1 3 olegodints
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:   BMSTU
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// Engineer:  Oleg Odintsov
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// 
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// Create Date:    10:50:36 02/15/2012 
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// Design Name: 
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// Module Name:    my6502 
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// Project Name:    Agat Hardware Project
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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// Specify following define to allow external 
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//              clocking for phi1 and phi2
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//      In such case you may use ag6502_ext_clock module
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//              with baseclk frequency ~ 10 x phi_0
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`define AG6502_EXTERNAL_CLOCK
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`ifndef AG6502_EXTERNAL_CLOCK
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module ag6502_clock(input phi_0, output phi_1, output phi_2);
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        wire phi_01;
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        not#3(phi_1,phi_0);
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        or(phi_01,~phi_0, phi_1);
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        not#1(phi_2, phi_01);
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endmodule
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`else
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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        parameter DELAY = 1; // delay in semi-waves of baseclk
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        initial phi_1 = 0;
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        integer cnt = 0;
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        always @(posedge baseclk) begin
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                if (phi_0 != phi_1) begin
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                        if (!cnt) begin phi_1 <= ~phi_1; cnt <= DELAY; end
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                        else cnt <= cnt - 1;
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                end
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        end
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endmodule
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// baseclk is used to simulate delays on a real hardware
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module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
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        parameter DELAY1 = 3, DELAY2 = 1; // delays in semi-waves of baseclk
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        wire phi_1_neg, phi_01;
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        ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
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        assign phi_1 = ~phi_1_neg;
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        and(phi_01, phi_0, phi_1_neg);
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        ag6502_phase_shift#DELAY2 d2(baseclk, phi_01, phi_2);
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endmodule
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`endif
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69
 
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`define ALU_ORA 3'd0
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`define ALU_AND 3'd1
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`define ALU_EOR 3'd2
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`define ALU_ADC 3'd3
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`define ALU_ASL 3'd4
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`define ALU_LSR 3'd5
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`define ALU_ROL 3'd6
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`define ALU_ROR 3'd7
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module ag6502_decimal(ADD, D_IN, NEG, CORR);
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        input wire[4:0] ADD;
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        input wire D_IN, NEG;
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        output wire[4:0] CORR;
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        wire C9 = {ADD[4]^NEG, ADD[3:0]} > 5'd9;
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        assign CORR = D_IN?{C9^NEG, C9?ADD[3:0] + (NEG?4'd10:4'd6): ADD[3:0]}: ADD;
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endmodule
88
 
89
 
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module ag6502_alu(A, B, OP, NEG, C_IN, D_IN, R, C_OUT, V_OUT);
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        input wire[7:0] A, B;
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        input wire[2:0] OP;
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        input wire C_IN, D_IN, NEG;
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        output wire[7:0] R;
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        output wire C_OUT, V_OUT;
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        wire[4:0] ADD_L;
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        ag6502_decimal DL({1'b0, A[3:0]} + {1'b0, B[3:0]} + C_IN, D_IN, NEG, ADD_L);
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        wire CF_H = ADD_L[4];
100
 
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        wire[4:0] ADD_H;
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        ag6502_decimal DH({1'b0, A[7:4]} + {1'b0, B[7:4]} + CF_H, D_IN, NEG, ADD_H);
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        assign
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                {C_OUT,R} = (OP==`ALU_ORA)? A | B:
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                                (OP==`ALU_AND)? A & B:
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                                (OP==`ALU_EOR)? A ^ B:
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                                (OP==`ALU_ADC)? {ADD_H, ADD_L[3:0]}:
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                                (OP==`ALU_ASL)? {A[7], A[6:0], 1'b0}:
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                                (OP==`ALU_LSR)? {A[0], 1'b0, A[7:1]}:
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                                (OP==`ALU_ROL)? {A[7], A[6:0], C_IN}:
112
                                (OP==`ALU_ROR)? {A[0], C_IN, A[7:1]}:
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                                8'bX;
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        assign V_OUT = (A[7] == B[7]) && (A[7] != R[7]);
115
endmodule
116
 
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/*
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        System AB/DB discipline:
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        1. For CPU
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                Phi1 up => CPU set ab/db_out buses
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                Phi2 down => CPU reads data from db_in
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        2. For Memory / other devices
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                Phi2 up => perform read/write operation
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*/
125
 
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127
module ag6502(input phi_0,
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`ifdef AG6502_EXTERNAL_CLOCK
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                input phi_1, input phi_2,
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`else
131
                output phi_1, output phi_2,
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`endif
133
                output reg[15:0] ab,
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                output wire read,
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                input[7:0] db_in, output reg[7:0] db_out,
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                input rdy,
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                input rst, input irq, input nmi,
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                input so,
139
                output sync);
140
 
141
`ifndef AG6502_EXTERNAL_CLOCK
142
        ag6502_clock cgen(phi_0, phi_1, phi_2);
143
`endif
144
 
145
        reg rdyg = 1;
146
 
147
        reg[2:0] T = 7;
148
        reg[7:0] IR ='h18;
149
 
150
        reg[15:0] PC = 0;
151
        wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
152
        reg[7:0] EAL, EAH;
153
        wire[15:0] EA = {EAH, EAL};
154
 
155
        reg FLAG_C, FLAG_Z, FLAG_I, FLAG_D, FLAG_B, FLAG_V, FLAG_N;
156
 
157
        reg[7:0] AC, X, Y, S = 0;
158
        wire[7:0] P = {FLAG_N, FLAG_V, 1'b1, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C};
159
        wire[7:0] SB;
160
 
161
 
162
        wire[7:0] ALU_A, ALU_B;
163
        wire[7:0] RES;
164
        wire[2:0] ALU_OP;
165
        reg[8:0] eALU; // with carry
166
        wire[7:0] ALU = eALU;
167
        wire ALU_CF = eALU[8];
168
 
169
        wire CF_IN, DF_IN;
170
        wire CF_OUT, VF_OUT;
171
 
172
        reg so_prev = 0;
173
        reg nmi_prev = 0;
174
        wire irq_active = ~irq & ~FLAG_I;
175
        wire nmi_active = ~nmi & nmi_prev;
176
        wire int_active = irq_active | nmi_active;
177
        wire rst_active = ~rst;
178
        wire so_active = so & ~so_prev;
179
 
180
        wire[1:0] vec_bits=
181
                        nmi_active?2'b01:
182
                        rst_active?2'b10:
183
                        2'b11;
184
 
185
        wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
186
 
187
        wire[7:0] IR_eff = int_active?8'b0:IR;
188
 
189
        wire[10:0] L = {T, IR_eff};
190
 
191
        `include "states.v"
192
 
193
        assign read = ~A_RW_W;
194
        assign sync = !T;
195
 
196
        assign SB = A_SB_DB? db_in:
197
                                        A_SB_AC? AC:
198
                                        A_SB_X? X:
199
                                        A_SB_Y? Y:
200
                                        A_SB_S? S:
201
                                        A_SB_P? P:
202
                                        A_SB_ALU? ALU:
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                                        A_SB_0? 8'b0:
204
                                        A_SB_PCH? PCH:
205
                                        A_SB_PCL? PCL:
206
                                        8'bX;
207
 
208
        assign CF_IN = A_ALU_CF_0? 1'b0:
209
                                        A_ALU_CF_1? 1'b1:
210
                                        A_ALU_CF_ALUC? ALU_CF:
211
                                        FLAG_C;
212
 
213
        assign DF_IN = A_ALU_DF_D? FLAG_D: 1'b0;
214
 
215
        assign ALU_A =
216
                                        A_ALU_A_AC? AC:
217
                                        A_ALU_A_X? X:
218
                                        A_ALU_A_Y? Y:
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                                        A_ALU_A_DB? db_in:
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                                        A_ALU_A_EAL? EAL:
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                                        A_ALU_A_ALU? ALU:
222
                                        A_ALU_A_S? S:
223
                                        A_ALU_A_SIGN? (EAL[7]?8'b11111111:8'b00000001):
224
                                        8'bX;
225
 
226
        assign ALU_B = A_ALU_B_SB? SB:
227
                                        A_ALU_B_NOTSB? ~SB:
228
                                        8'bX;
229
 
230
        assign ALU_OP = A_ALU_OP_ADC? `ALU_ADC:
231
                                        A_ALU_OP_ORA? `ALU_ORA:
232
                                        A_ALU_OP_EOR? `ALU_EOR:
233
                                        A_ALU_OP_AND? `ALU_AND:
234
                                        A_ALU_OP_ASL? `ALU_ASL:
235
                                        A_ALU_OP_LSR? `ALU_LSR:
236
                                        A_ALU_OP_ROL? `ALU_ROL:
237
                                        A_ALU_OP_ROR? `ALU_ROR:
238
                                        8'bX;
239
 
240
        ag6502_alu alu(ALU_A, ALU_B, ALU_OP, A_ALU_B_NOTSB, CF_IN, DF_IN, RES, CF_OUT, VF_OUT);
241
 
242
        always @(posedge phi_1) begin
243
                if (E_AB__PC) ab <= PC;
244
                else if (E_AB__EA) ab <= EA;
245
                else if (E_AB__S) ab <= {8'b1, S};
246
 
247
                if (E_DB__SB) db_out <= SB;
248
                else if (E_DB__PCH) db_out <= PCH;
249
                else if (E_DB__PCL) db_out <= PCL;
250
                else if (E_DB__P) db_out <= P;
251
                else if (E_DB__ALU) db_out <= ALU;
252
 
253
                if (read) rdyg <= rdy;
254
        end
255
 
256
 
257
        wire cond;
258
 
259
        assign cond =
260
                        E_T__0IFNF__IR_5_?(FLAG_N != IR[5]):
261
                        E_T__0IFVF__IR_5_?(FLAG_V != IR[5]):
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                        E_T__0IFCF__IR_5_?(FLAG_C != IR[5]):
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                        E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
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                        E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
265
                        E_T__0IF_C7F? CF_OUT == EAL[7]:
266
                        E_T__0;
267
 
268
        always @(negedge phi_2) if (rdyg) begin
269
                if (E_PC__PC_1) PC <= PC + 1;
270
                else if (E_PC__EA) PC <= EA;
271
                else begin
272
                        if (E_PCH__RES) PC[15:8] <= RES;
273
                        if (E_PCL__ALU) PC[7:0] <= ALU;
274
                        else if (E_PCL__RES) PC[7:0] <= RES;
275
                        else if (E_PCL__EAL) PC[7:0] <= EAL;
276
                        else if (E_PCL__DB) PC[7:0] <= db_in;
277
                end
278
 
279
                if (!T) begin
280
                        IR <= db_in;
281
                        if (!db_in) begin // BRK instruction
282
                                {EAH, EAL} <= vec_addr;
283
                        end
284
                        nmi_prev <= nmi;
285
                end
286
 
287
                if (E_N_Z__SB) begin FLAG_Z <= !SB; FLAG_N <= SB[7]; end
288
                else if (E_N_Z__RES) begin FLAG_Z <= !RES; FLAG_N <= RES[7]; end
289
                else if (E_N_Z__SB_RES) begin FLAG_Z <= !RES; FLAG_N <= SB[7]; end
290
 
291
                if (E_C__RES) FLAG_C <= CF_OUT;
292
                if (E_V__RES) FLAG_V <= VF_OUT;
293
                else if (E_V__SB_6_) FLAG_V <= SB[6];
294
 
295
                if (E_EAL__DB) EAL <= db_in;
296
                else if (E_EAL__ALU) EAL <= ALU;
297
 
298
 
299
                if (E_EA__DB) {EAH, EAL} <= { 8'b0, db_in };
300
                else if (E_EAH__DB) EAH <= db_in;
301
                else if (E_EAH__ALU) EAH <= ALU;
302
 
303
                if (E_AC__SB) AC <= SB;
304
                else if (E_AC__RES) AC <= RES;
305
 
306
                if (E_S__ALU) S <= ALU;
307
 
308
                if (E_X__SB) X <= SB;
309
                else if (E_X__RES) X <= RES;
310
 
311
                if (E_Y__SB) Y <= SB;
312
                else if (E_Y__RES) Y <= RES;
313
 
314
                if (E_S__SB) S <= SB;
315
                if (E_P__SB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {SB[7], SB[6], SB[4], SB[3], SB[2], SB[1], SB[0]};
316
                else if (E_P__DB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {db_in[7], db_in[6], db_in[4], db_in[3], db_in[2], db_in[1], db_in[0]};
317
 
318
                if (E_CF__IR_5_) FLAG_C <= IR[5];
319
                if (E_IF__IR_5_) FLAG_I <= IR[5];
320
                if (E_DF__IR_5_) FLAG_D <= IR[5];
321
                if (E_VF__0) FLAG_V <= 0;
322
                else if (so_active) FLAG_V <= 1;
323
                so_prev <= so;
324
 
325
                eALU <= {CF_OUT, RES};
326
 
327
                if (cond) begin
328
                        T <= 0;
329
                        if (!IR_eff) begin
330
                                FLAG_B <= !IR;
331
                                FLAG_I <= 1;
332
                        end
333
                end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
334
 
335
                if (rst_active) begin
336
                        T <= 1;
337
                        IR <= 0;
338
                        {EAH, EAL} <= vec_addr;
339
                end
340
        end
341
 
342
 
343
endmodule
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