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[/] [ag_6502/] [trunk/] [fighter/] [clkdiv.v] - Blame information for rev 3

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1 3 olegodints
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    23:20:37 02/23/2012 
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// Design Name: 
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// Module Name:    clkdiv 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clk_div(input clk, output clk1);
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        parameter divide = 16;
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        wire clk0;
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   DCM_SP #(
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      .CLKDV_DIVIDE(divide) // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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                          //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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   ) DCM_SP_inst (
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      .CLKDV(clk1),   // Divided DCM CLK out (CLKDV_DIVIDE)
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      .CLKIN(clk),   // Clock input (from IBUFG, BUFG or DCM)
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                .CLK0(clk0),
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                .CLKFB(clk0),
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                .RST(0)
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   );
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endmodule

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