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[/] [ahb2wishbone/] [branches/] [toomuch/] [svtb/] [avm_svtb/] [ahb_wb_top.sv] - Blame information for rev 10

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1 7 toomuch
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//*****************************************************************************************************************
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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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//
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//File name             :       ahb_wb_top.sv
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//Designer              :       Sanjay kumar
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//Date                  :       3rd Aug'2007
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//Description           :       ahb_wb_top:Top module instantiating all components and scheduling tasks
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//Revision              :       1.0
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//*****************************************************************************************************************
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// top module
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`include "../../src/ahb2wb.v"
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`timescale 1ns/ 1ps
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import ahb_wb_pkg::*;
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import global::*;
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module ahb_wb_top;
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logic clk ='b0;
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logic reset ='b1;
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        ahb_wb_if inf1(); // interface instance from ahb to bridge
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        stimulus_gen TB_M(inf1.master_ab,clk,reset); // AHB master instance
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        ahb2wb DUT ( // interface connection from AHB(stimulus gen) to bridge
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                   .hclk(inf1.slave_ab.hclk),
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                   .hresetn(inf1.slave_ab.hresetn),
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                   .haddr(inf1.slave_ab.haddr),
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                   .hwdata(inf1.slave_ab.hwdata),
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                   .htrans(inf1.slave_ab.htrans),
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                   .hburst(inf1.slave_ab.hburst),
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                   .hsize(inf1.slave_ab.hsize),
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                   .hwrite(inf1.slave_ab.hwrite),
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                   .hsel(inf1.slave_ab.hsel),
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                   .hready(inf1.slave_ab.hready),
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                   .hrdata(inf1.slave_ab.hrdata),
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                   .hresp(inf1.slave_ab.hresp),
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                   // interface connection from bridge to wishbone(memory)
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                   .cyc_o(inf1.master_bw.cyc_o),
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                   .stb_o(inf1.master_bw.stb_o),
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                   .we_o(inf1.master_bw.we_o),
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                   .dat_o(inf1.master_bw.dat_o),
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                   .adr_o(inf1.master_bw.adr_o),
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                   .ack_i(inf1.master_bw.ack_i),
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                   .dat_i(inf1.master_bw.dat_i),
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                   .clk_i(inf1.master_bw.clk_i),
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                   .rst_i(inf1.master_bw.rst_i));
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        ahb_wb_env env; // enviornment class
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// reset generation
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initial
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        begin
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                env = new(inf1);
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                $display ("\n@%0d:Testcase begin",$time);
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                #13  reset='b0;
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                #33 reset ='b1;
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                $display ("\n@%0d:Reset done",$time);
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                TB_M.initial_setup();
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                $display ("\n@%0d:Initial setup done",$time);
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                env.do_test();
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                $display ("\n@%0d do_test over",$time);
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                $finish;
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        end
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//clock generation
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initial
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        forever
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                #(cyc_prd/2)  clk = ~clk;
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endmodule

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