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[/] [ahb_master/] [trunk/] [src/] [base/] [axi2ahb_ctrl.v] - Blame information for rev 2

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INCLUDE def_axi2ahb.txt
OUTFILE PREFIX_axi2ahb_ctrl.v
 
module  PREFIX_axi2ahb_ctrl (PORTS);
 
 
   input                  clk;
   input                  reset;
 
   revport                GROUP_AHB;
 
   output                 ahb_finish;
   output                 rdata_phase;
   output                 wdata_phase;
   output                 data_last;
 
   input                  rdata_ready;
   input                  wdata_ready;
   input                  cmd_empty;
   input                  cmd_read;
   input [ADDR_BITS-1:0]  cmd_addr;
   input [3:0]            cmd_len;
   input [1:0]            cmd_size;
 
   parameter              TRANS_IDLE   = 2'b00;
   parameter              TRANS_BUSY   = 2'b01;
   parameter              TRANS_NONSEQ = 2'b10;
   parameter              TRANS_SEQ    = 2'b11;
 
   parameter              BURST_SINGLE = 3'b000;
   parameter              BURST_INCR4  = 3'b011;
   parameter              BURST_INCR8  = 3'b101;
   parameter              BURST_INCR16 = 3'b111;
 
 
   wire                   data_ready;
   wire                   ahb_idle;
   wire                   ahb_ack;
   wire                   ahb_ack_last;
   wire                   ahb_start;
   wire                   ahb_last;
   wire                   data_last;
   reg [4:0]              cmd_counter;
   reg                    rdata_phase;
   reg                    wdata_phase;
   reg [1:0]              HTRANS;
   reg [2:0]              HBURST;
   reg [1:0]              HSIZE;
   reg                    HWRITE;
   reg [ADDR_BITS-1:0]    HADDR;
 
 
   assign                 ahb_finish   = ahb_ack_last;
 
   assign                 data_ready   = cmd_read ? rdata_ready : wdata_ready;
 
   assign                 ahb_idle     = HTRANS == TRANS_IDLE;
   assign                 ahb_ack      = HTRANS[1] & HREADY;
   assign                 ahb_ack_last = ahb_last & ahb_ack;
   assign                 ahb_start    = (~cmd_empty) & data_ready & ahb_idle;
   assign                 data_last    = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
 
   always @(posedge clk or posedge reset)
     if (reset)
       cmd_counter <= #FFD 4'd0;
     else if (ahb_ack_last)
       cmd_counter <= #FFD 4'd0;
     else if (ahb_ack)
       cmd_counter <= #FFD cmd_counter + 1'b1;
 
   assign             ahb_last = cmd_counter == cmd_len;
 
   always @(posedge clk or posedge reset)
     if (reset)
       rdata_phase <= #FFD 1'b0;
     else if (ahb_ack & (~HWRITE))
       rdata_phase <= #FFD 1'b1;
     else if (data_last)
       rdata_phase <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       wdata_phase <= #FFD 1'b0;
     else if (ahb_ack & HWRITE)
       wdata_phase <= #FFD 1'b1;
     else if (data_last)
       wdata_phase <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HTRANS <= #FFD TRANS_IDLE;
     else if (ahb_start)
       HTRANS <= #FFD TRANS_NONSEQ;
     else if (ahb_ack_last)
       HTRANS <= #FFD TRANS_IDLE;
     else if (ahb_ack)
       HTRANS <= #FFD TRANS_SEQ;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HBURST <= #FFD BURST_SINGLE;
     else if (ahb_start & (cmd_len == 4'd0))
       HBURST <= #FFD BURST_SINGLE;
     else if (ahb_start & (cmd_len == 4'd3))
       HBURST <= #FFD BURST_INCR4;
     else if (ahb_start & (cmd_len == 4'd7))
       HBURST <= #FFD BURST_INCR8;
     else if (ahb_start & (cmd_len == 4'd15))
       HBURST <= #FFD BURST_INCR16;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HSIZE <= #FFD 2'b00;
     else if (ahb_start)
       HSIZE <= cmd_size;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HWRITE <= #FFD 2'b00;
     else if (ahb_start)
       HWRITE <= (~cmd_read);
 
   always @(posedge clk or posedge reset)
     if (reset)
       HADDR <= #FFD {ADDR_BITS{1'b0}};
     else if (ahb_start)
       HADDR <= #FFD cmd_addr;
     else if (ahb_ack_last)
       HADDR <= #FFD {ADDR_BITS{1'b0}};
     else if (ahb_ack)
       HADDR <= #FFD HADDR + (
                              HSIZE == 2'b00 ? 4'd1 :
                              HSIZE == 2'b01 ? 4'd2 :
                              HSIZE == 2'b10 ? 4'd4 :
                              HSIZE == 2'b11 ? 4'd8 :
                              4'd0);
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc
2			`INCLUDE def_axi2ahb.txt`
3			`OUTFILE PREFIX_axi2ahb_ctrl.v`
4
5			`module PREFIX_axi2ahb_ctrl (PORTS);`
6
7
8			`input clk;`
9			`input reset;`
10
11			`revport GROUP_AHB;`
12
13			`output ahb_finish;`
14			`output rdata_phase;`
15			`output wdata_phase;`
16			`output data_last;`
17
18			`input rdata_ready;`
19			`input wdata_ready;`
20			`input cmd_empty;`
21			`input cmd_read;`
22			`input [ADDR_BITS-1:0] cmd_addr;`
23			`input [3:0] cmd_len;`
24			`input [1:0] cmd_size;`
25
26			`parameter TRANS_IDLE = 2'b00;`
27			`parameter TRANS_BUSY = 2'b01;`
28			`parameter TRANS_NONSEQ = 2'b10;`
29			`parameter TRANS_SEQ = 2'b11;`
30
31			`parameter BURST_SINGLE = 3'b000;`
32			`parameter BURST_INCR4 = 3'b011;`
33			`parameter BURST_INCR8 = 3'b101;`
34			`parameter BURST_INCR16 = 3'b111;`
35
36
37			`wire data_ready;`
38			`wire ahb_idle;`
39			`wire ahb_ack;`
40			`wire ahb_ack_last;`
41			`wire ahb_start;`
42			`wire ahb_last;`
43			`wire data_last;`
44			`reg [4:0] cmd_counter;`
45			`reg rdata_phase;`
46			`reg wdata_phase;`
47			`reg [1:0] HTRANS;`
48			`reg [2:0] HBURST;`
49			`reg [1:0] HSIZE;`
50			`reg HWRITE;`
51			`reg [ADDR_BITS-1:0] HADDR;`
52
53
54			`assign ahb_finish = ahb_ack_last;`
55
56			`assign data_ready = cmd_read ? rdata_ready : wdata_ready;`
57
58			`assign ahb_idle = HTRANS == TRANS_IDLE;`
59			`assign ahb_ack = HTRANS[1] & HREADY;`
60			`assign ahb_ack_last = ahb_last & ahb_ack;`
61			`assign ahb_start = (~cmd_empty) & data_ready & ahb_idle;`
62			`assign data_last = HREADY & (ahb_idle \|\| (HTRANS == TRANS_NONSEQ));`
63
64			`always @(posedge clk or posedge reset)`
65			`if (reset)`
66			`cmd_counter <= #FFD 4'd0;`
67			`else if (ahb_ack_last)`
68			`cmd_counter <= #FFD 4'd0;`
69			`else if (ahb_ack)`
70			`cmd_counter <= #FFD cmd_counter + 1'b1;`
71
72			`assign ahb_last = cmd_counter == cmd_len;`
73
74			`always @(posedge clk or posedge reset)`
75			`if (reset)`
76			`rdata_phase <= #FFD 1'b0;`
77			`else if (ahb_ack & (~HWRITE))`
78			`rdata_phase <= #FFD 1'b1;`
79			`else if (data_last)`
80			`rdata_phase <= #FFD 1'b0;`
81
82			`always @(posedge clk or posedge reset)`
83			`if (reset)`
84			`wdata_phase <= #FFD 1'b0;`
85			`else if (ahb_ack & HWRITE)`
86			`wdata_phase <= #FFD 1'b1;`
87			`else if (data_last)`
88			`wdata_phase <= #FFD 1'b0;`
89
90			`always @(posedge clk or posedge reset)`
91			`if (reset)`
92			`HTRANS <= #FFD TRANS_IDLE;`
93			`else if (ahb_start)`
94			`HTRANS <= #FFD TRANS_NONSEQ;`
95			`else if (ahb_ack_last)`
96			`HTRANS <= #FFD TRANS_IDLE;`
97			`else if (ahb_ack)`
98			`HTRANS <= #FFD TRANS_SEQ;`
99
100			`always @(posedge clk or posedge reset)`
101			`if (reset)`
102			`HBURST <= #FFD BURST_SINGLE;`
103			`else if (ahb_start & (cmd_len == 4'd0))`
104			`HBURST <= #FFD BURST_SINGLE;`
105			`else if (ahb_start & (cmd_len == 4'd3))`
106			`HBURST <= #FFD BURST_INCR4;`
107			`else if (ahb_start & (cmd_len == 4'd7))`
108			`HBURST <= #FFD BURST_INCR8;`
109			`else if (ahb_start & (cmd_len == 4'd15))`
110			`HBURST <= #FFD BURST_INCR16;`
111
112			`always @(posedge clk or posedge reset)`
113			`if (reset)`
114			`HSIZE <= #FFD 2'b00;`
115			`else if (ahb_start)`
116			`HSIZE <= cmd_size;`
117
118			`always @(posedge clk or posedge reset)`
119			`if (reset)`
120			`HWRITE <= #FFD 2'b00;`
121			`else if (ahb_start)`
122			`HWRITE <= (~cmd_read);`
123
124			`always @(posedge clk or posedge reset)`
125			`if (reset)`
126			`HADDR <= #FFD {ADDR_BITS{1'b0}};`
127			`else if (ahb_start)`
128			`HADDR <= #FFD cmd_addr;`
129			`else if (ahb_ack_last)`
130			`HADDR <= #FFD {ADDR_BITS{1'b0}};`
131			`else if (ahb_ack)`
132			`HADDR <= #FFD HADDR + (`
133			`HSIZE == 2'b00 ? 4'd1 :`
134			`HSIZE == 2'b01 ? 4'd2 :`
135			`HSIZE == 2'b10 ? 4'd4 :`
136			`HSIZE == 2'b11 ? 4'd8 :`
137			`4'd0);`
138
139
140			`endmodule`
141
142

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[/] [ahb_master/] [trunk/] [src/] [base/] [axi2ahb_ctrl.v] - Blame information for rev 2