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[/] [ahb_master/] [trunk/] [src/] [base/] [axi2ahb_ctrl.v] - Blame information for rev 5

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1 2 eyalhoc
 
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INCLUDE def_axi2ahb.txt
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OUTFILE PREFIX_axi2ahb_ctrl.v
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module  PREFIX_axi2ahb_ctrl (PORTS);
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   input                  clk;
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   input                  reset;
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   revport                GROUP_AHB;
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   output                 ahb_finish;
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   output                 rdata_phase;
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   output                 wdata_phase;
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   output                 data_last;
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   input                  rdata_ready;
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   input                  wdata_ready;
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   input                  cmd_empty;
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   input                  cmd_read;
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   input [ADDR_BITS-1:0]  cmd_addr;
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   input [3:0]            cmd_len;
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   input [1:0]            cmd_size;
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   parameter              TRANS_IDLE   = 2'b00;
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   parameter              TRANS_BUSY   = 2'b01;
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   parameter              TRANS_NONSEQ = 2'b10;
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   parameter              TRANS_SEQ    = 2'b11;
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   parameter              BURST_SINGLE = 3'b000;
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   parameter              BURST_INCR4  = 3'b011;
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   parameter              BURST_INCR8  = 3'b101;
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   parameter              BURST_INCR16 = 3'b111;
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   wire                   data_ready;
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   wire                   ahb_idle;
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   wire                   ahb_ack;
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   wire                   ahb_ack_last;
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   wire                   ahb_start;
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   wire                   ahb_last;
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   wire                   data_last;
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   reg [4:0]              cmd_counter;
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   reg                    rdata_phase;
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   reg                    wdata_phase;
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   wire                   data_phase;
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   reg [1:0]              HTRANS;
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   reg [2:0]              HBURST;
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   reg [1:0]              HSIZE;
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   reg                    HWRITE;
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   reg [ADDR_BITS-1:0]    HADDR;
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   assign                 ahb_finish   = ahb_ack_last;
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   assign                 data_ready   = cmd_read ? rdata_ready : wdata_ready;
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   assign                 data_phase   = wdata_phase | rdata_phase;
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   assign                 ahb_idle     = HTRANS == TRANS_IDLE;
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   assign                 ahb_ack      = HTRANS[1] & HREADY;
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   assign                 ahb_ack_last = ahb_last & ahb_ack;
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   assign                 ahb_start    = (~cmd_empty) & data_ready & ahb_idle & (HREADY | (~data_phase));
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   assign                 data_last    = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
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   always @(posedge clk or posedge reset)
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     if (reset)
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       cmd_counter <= #FFD 4'd0;
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     else if (ahb_ack_last)
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       cmd_counter <= #FFD 4'd0;
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     else if (ahb_ack)
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       cmd_counter <= #FFD cmd_counter + 1'b1;
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   assign             ahb_last = cmd_counter == cmd_len;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       rdata_phase <= #FFD 1'b0;
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     else if (ahb_ack & (~HWRITE))
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       rdata_phase <= #FFD 1'b1;
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     else if (data_last)
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       rdata_phase <= #FFD 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       wdata_phase <= #FFD 1'b0;
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     else if (ahb_ack & HWRITE)
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       wdata_phase <= #FFD 1'b1;
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     else if (data_last)
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       wdata_phase <= #FFD 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HTRANS <= #FFD TRANS_IDLE;
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     else if (ahb_start)
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       HTRANS <= #FFD TRANS_NONSEQ;
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     else if (ahb_ack_last)
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       HTRANS <= #FFD TRANS_IDLE;
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     else if (ahb_ack)
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       HTRANS <= #FFD TRANS_SEQ;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HBURST <= #FFD BURST_SINGLE;
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     else if (ahb_start & (cmd_len == 4'd0))
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       HBURST <= #FFD BURST_SINGLE;
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     else if (ahb_start & (cmd_len == 4'd3))
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       HBURST <= #FFD BURST_INCR4;
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     else if (ahb_start & (cmd_len == 4'd7))
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       HBURST <= #FFD BURST_INCR8;
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     else if (ahb_start & (cmd_len == 4'd15))
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       HBURST <= #FFD BURST_INCR16;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HSIZE <= #FFD 2'b00;
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     else if (ahb_start)
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       HSIZE <= cmd_size;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HWRITE <= #FFD 2'b00;
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     else if (ahb_start)
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       HWRITE <= (~cmd_read);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HADDR <= #FFD {ADDR_BITS{1'b0}};
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     else if (ahb_start)
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       HADDR <= #FFD cmd_addr;
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     else if (ahb_ack_last)
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       HADDR <= #FFD {ADDR_BITS{1'b0}};
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     else if (ahb_ack)
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       HADDR <= #FFD HADDR + (
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                              HSIZE == 2'b00 ? 4'd1 :
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                              HSIZE == 2'b01 ? 4'd2 :
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                              HSIZE == 2'b10 ? 4'd4 :
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                              HSIZE == 2'b11 ? 4'd8 :
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                              4'd0);
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endmodule
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