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[/] [ahb_master/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 7

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_ic_decerr.v
 
module PREFIX_ic_decerr(PORTS);
 
   input                          clk;
   input                          reset;
 
   input                          AWIDOK;
   input                          ARIDOK;
   port                           GROUP_IC_AXI;
 
 
   parameter                      RESP_SLVERR = 2'b10;
   parameter                      RESP_DECERR = 2'b11;
 
 
   reg                            AWREADY;
   reg [ID_BITS-1:0]               BID;
   reg [1:0]                       BRESP;
   reg                            BVALID;
   reg                            ARREADY;
   reg [ID_BITS-1:0]               RID;
   reg [1:0]                       RRESP;
   reg                            RVALID;
   reg [4-1:0]                    rvalid_cnt;
 
 
IFDEF TRUE (USER_BITS>0)
   assign                         BUSER = 'd0;
   assign                         RUSER = 'd0;
ENDIF TRUE (USER_BITS>0)
 
   assign                         RDATA = {DATA_BITS{1'b0}};
 
 
   //WRITE
   assign                         WREADY = 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          AWREADY <= #FFD 1'b1;
          BID     <= #FFD {ID_BITS{1'b0}};
          BRESP   <= #FFD 2'b00;
       end
     else if (BVALID & BREADY)
       begin
          AWREADY <= #FFD 1'b1;
       end
     else if (AWVALID & AWREADY)
       begin
          AWREADY <= #FFD 1'b0;
          BID     <= #FFD AWID;
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
   always @(posedge clk or posedge reset)
     if (reset)
       BVALID <= #FFD 1'b0;
     else if (WVALID & WREADY & WLAST)
       BVALID <= #FFD 1'b1;
     else if (BVALID & BREADY)
       BVALID <= #FFD 1'b0;
 
 
   //READ   
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          ARREADY <= #FFD 1'b1;
          RID     <= #FFD {ID_BITS{1'b0}};
          RRESP   <= #FFD 2'b00;
       end
     else if (RVALID & RREADY & RLAST)
       begin
          ARREADY <= #FFD 1'b1;
       end
     else if (ARVALID & ARREADY)
       begin
          ARREADY <= #FFD 1'b0;
          RID     <= #FFD ARID;
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY & RLAST)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY)
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
     else if (ARVALID & ARREADY)
       rvalid_cnt <= #FFD ARLEN;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       RVALID <= #FFD 1'b0;
     else if (RVALID & RREADY & RLAST)
       RVALID <= #FFD 1'b0;
     else if (ARVALID & ARREADY)
       RVALID <= #FFD 1'b1;
 
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
 
 
 
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29
30			`OUTFILE PREFIX_ic_decerr.v`
31
32			`module PREFIX_ic_decerr(PORTS);`
33
34			`input clk;`
35			`input reset;`
36
37			`input AWIDOK;`
38			`input ARIDOK;`
39			`port GROUP_IC_AXI;`
40
41
42			`parameter RESP_SLVERR = 2'b10;`
43			`parameter RESP_DECERR = 2'b11;`
44
45
46			`reg AWREADY;`
47			`reg [ID_BITS-1:0] BID;`
48			`reg [1:0] BRESP;`
49			`reg BVALID;`
50			`reg ARREADY;`
51			`reg [ID_BITS-1:0] RID;`
52			`reg [1:0] RRESP;`
53			`reg RVALID;`
54			`reg [4-1:0] rvalid_cnt;`
55
56
57			`IFDEF TRUE (USER_BITS>0)`
58			`assign BUSER = 'd0;`
59			`assign RUSER = 'd0;`
60			`ENDIF TRUE (USER_BITS>0)`
61
62			`assign RDATA = {DATA_BITS{1'b0}};`
63
64
65			`//WRITE`
66			`assign WREADY = 1'b1;`
67
68			`always @(posedge clk or posedge reset)`
69			`if (reset)`
70			`begin`
71			`AWREADY <= #FFD 1'b1;`
72			`BID <= #FFD {ID_BITS{1'b0}};`
73			`BRESP <= #FFD 2'b00;`
74			`end`
75			`else if (BVALID & BREADY)`
76			`begin`
77			`AWREADY <= #FFD 1'b1;`
78			`end`
79			`else if (AWVALID & AWREADY)`
80			`begin`
81			`AWREADY <= #FFD 1'b0;`
82			`BID <= #FFD AWID;`
83			`BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;`
84			`end`
85
86			`always @(posedge clk or posedge reset)`
87			`if (reset)`
88			`BVALID <= #FFD 1'b0;`
89			`else if (WVALID & WREADY & WLAST)`
90			`BVALID <= #FFD 1'b1;`
91			`else if (BVALID & BREADY)`
92			`BVALID <= #FFD 1'b0;`
93
94
95			`//READ`
96			`always @(posedge clk or posedge reset)`
97			`if (reset)`
98			`begin`
99			`ARREADY <= #FFD 1'b1;`
100			`RID <= #FFD {ID_BITS{1'b0}};`
101			`RRESP <= #FFD 2'b00;`
102			`end`
103			`else if (RVALID & RREADY & RLAST)`
104			`begin`
105			`ARREADY <= #FFD 1'b1;`
106			`end`
107			`else if (ARVALID & ARREADY)`
108			`begin`
109			`ARREADY <= #FFD 1'b0;`
110			`RID <= #FFD ARID;`
111			`RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;`
112			`end`
113
114
115			`always @(posedge clk or posedge reset)`
116			`if (reset)`
117			`rvalid_cnt <= #FFD {4{1'b0}};`
118			`else if (RVALID & RREADY & RLAST)`
119			`rvalid_cnt <= #FFD {4{1'b0}};`
120			`else if (RVALID & RREADY)`
121			`rvalid_cnt <= #FFD rvalid_cnt - 1'b1;`
122			`else if (ARVALID & ARREADY)`
123			`rvalid_cnt <= #FFD ARLEN;`
124
125
126			`always @(posedge clk or posedge reset)`
127			`if (reset)`
128			`RVALID <= #FFD 1'b0;`
129			`else if (RVALID & RREADY & RLAST)`
130			`RVALID <= #FFD 1'b0;`
131			`else if (ARVALID & ARREADY)`
132			`RVALID <= #FFD 1'b1;`
133
134			`assign RLAST = (rvalid_cnt == 'd0) & RVALID;`
135
136
137
138
139
140
141			`endmodule`
142
143

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[/] [ahb_master/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 7