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[/] [ahb_master/] [trunk/] [src/] [gen/] [prgen_fifo.v] - Blame information for rev 12

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
IFDEF STUB
OUTFILE prgen_fifo_stub.v
module prgen_fifo_stub(PORTS);
ELSE STUB
OUTFILE prgen_fifo.v
module prgen_fifo(PORTS);
ENDIF STUB
 
   parameter                  WIDTH      = 8;
   parameter                  DEPTH_FULL = 8;
 
   parameter                  SINGLE     = DEPTH_FULL == 1;
   parameter                  DEPTH      = SINGLE ? 1 : DEPTH_FULL -1;
   parameter                  DEPTH_BITS =
                              (DEPTH <= 2)   ? 1 :
                              (DEPTH <= 4)   ? 2 :
                              (DEPTH <= 8)   ? 3 :
                              (DEPTH <= 16)  ? 4 :
                              (DEPTH <= 32)  ? 5 :
                              (DEPTH <= 64)  ? 6 :
                              (DEPTH <= 128) ? 7 :
                              (DEPTH <= 256) ? 8 :
                              (DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
   parameter                  LAST_LINE  = DEPTH-1;
 
 
 
   input                      clk;
   input                      reset;
 
   input                      push;
   input                      pop;
   input [WIDTH-1:0]           din;
   output [WIDTH-1:0]          dout;
   IF STUB output [DEPTH_BITS:0] fullness;
   output                     empty;
   output                     full;
 
 
   wire                       reg_push;
   wire                       reg_pop;
   wire                       fifo_push;
   wire                       fifo_pop;
 
   reg [DEPTH-1:0]             full_mask_in;
   reg [DEPTH-1:0]             full_mask_out;
   reg [DEPTH-1:0]             full_mask;
   reg [WIDTH-1:0]             fifo [DEPTH-1:0];
   wire                       fifo_empty;
   wire                       next;
   reg [WIDTH-1:0]             dout;
   reg                        dout_empty;
   reg [DEPTH_BITS-1:0]       ptr_in;
   reg [DEPTH_BITS-1:0]       ptr_out;
 
 
 
 
   assign                     reg_push  = push & fifo_empty & (dout_empty | pop);
   assign                     reg_pop   = pop & fifo_empty;
   assign                     fifo_push = !SINGLE & push & (~reg_push);
   assign                     fifo_pop  = !SINGLE & pop & (~reg_pop);
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          dout       <= #FFD {WIDTH{1'b0}};
          dout_empty <= #FFD 1'b1;
       end
     else if (reg_push)
       begin
          dout       <= #FFD din;
          dout_empty <= #FFD 1'b0;
       end
     else if (reg_pop)
       begin
          dout       <= #FFD {WIDTH{1'b0}};
          dout_empty <= #FFD 1'b1;
       end
     else if (fifo_pop)
       begin
          dout       <= #FFD fifo[ptr_out];
          dout_empty <= #FFD 1'b0;
       end
 
   always @(posedge clk or posedge reset)
     if (reset)
       ptr_in <= #FFD {DEPTH_BITS{1'b0}};
     else if (fifo_push)
       ptr_in <= #FFD ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       ptr_out <= #FFD {DEPTH_BITS{1'b0}};
     else if (fifo_pop)
       ptr_out <= #FFD ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
 
   always @(posedge clk)
     if (fifo_push)
       fifo[ptr_in] <= #FFD din;
 
 
   always @(/*AUTOSENSE*/fifo_push or ptr_in)
     begin
        full_mask_in = {DEPTH{1'b0}};
        full_mask_in[ptr_in] = fifo_push;
     end
 
   always @(/*AUTOSENSE*/fifo_pop or ptr_out)
     begin
        full_mask_out = {DEPTH{1'b0}};
        full_mask_out[ptr_out] = fifo_pop;
     end
 
   always @(posedge clk or posedge reset)
     if (reset)
       full_mask <= #FFD {DEPTH{1'b0}};
     else if (fifo_push | fifo_pop)
       full_mask <= #FFD (full_mask & (~full_mask_out)) | full_mask_in;
 
 
   assign next       = |full_mask;
   assign fifo_empty = ~next;
   assign empty      = fifo_empty & dout_empty;
   assign full       = SINGLE ? !dout_empty : &full_mask;
 
 
 
IFDEF STUB
  reg [DEPTH_BITS:0] fullness;
 
   always @(posedge clk or posedge reset)
     if (reset)
       fullness <= #FFD {DEPTH_BITS+1{1'b0}};
     else if (push | pop)
       fullness <= #FFD fullness + push - pop;
 
   wire              overflow  = full & fifo_push & (~fifo_pop);
   wire              underflow = empty & fifo_pop & (~fifo_push);
 
   always @(posedge overflow)
     begin
        #1;
        if (overflow)
          begin
             $display("-E-%m - overflow.\tTime: %0d ns", $time);
             #1000;
             $finish;
          end
     end
   always @(posedge underflow)
     begin
        #1;
        if (underflow)
          begin
             $display("-E-%m - underflow.\tTime: %0d ns", $time);
             #1000;
             $finish;
          end
     end
ENDIF STUB
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`/////////////////////////////////////////////////////////////////////`
29
30			`IFDEF STUB`
31			`OUTFILE prgen_fifo_stub.v`
32			`module prgen_fifo_stub(PORTS);`
33			`ELSE STUB`
34			`OUTFILE prgen_fifo.v`
35			`module prgen_fifo(PORTS);`
36			`ENDIF STUB`
37
38			`parameter WIDTH = 8;`
39			`parameter DEPTH_FULL = 8;`
40
41			`parameter SINGLE = DEPTH_FULL == 1;`
42			`parameter DEPTH = SINGLE ? 1 : DEPTH_FULL -1;`
43			`parameter DEPTH_BITS =`
44			`(DEPTH <= 2) ? 1 :`
45			`(DEPTH <= 4) ? 2 :`
46			`(DEPTH <= 8) ? 3 :`
47			`(DEPTH <= 16) ? 4 :`
48			`(DEPTH <= 32) ? 5 :`
49			`(DEPTH <= 64) ? 6 :`
50			`(DEPTH <= 128) ? 7 :`
51			`(DEPTH <= 256) ? 8 :`
52			`(DEPTH <= 512) ? 9 : 0; //0 is ilegal`
53
54			`parameter LAST_LINE = DEPTH-1;`
55
56
57
58			`input clk;`
59			`input reset;`
60
61			`input push;`
62			`input pop;`
63			`input [WIDTH-1:0] din;`
64			`output [WIDTH-1:0] dout;`
65			`IF STUB output [DEPTH_BITS:0] fullness;`
66			`output empty;`
67			`output full;`
68
69
70			`wire reg_push;`
71			`wire reg_pop;`
72			`wire fifo_push;`
73			`wire fifo_pop;`
74
75			`reg [DEPTH-1:0] full_mask_in;`
76			`reg [DEPTH-1:0] full_mask_out;`
77			`reg [DEPTH-1:0] full_mask;`
78			`reg [WIDTH-1:0] fifo [DEPTH-1:0];`
79			`wire fifo_empty;`
80			`wire next;`
81			`reg [WIDTH-1:0] dout;`
82			`reg dout_empty;`
83			`reg [DEPTH_BITS-1:0] ptr_in;`
84			`reg [DEPTH_BITS-1:0] ptr_out;`
85
86
87
88
89			`assign reg_push = push & fifo_empty & (dout_empty \| pop);`
90			`assign reg_pop = pop & fifo_empty;`
91			`assign fifo_push = !SINGLE & push & (~reg_push);`
92			`assign fifo_pop = !SINGLE & pop & (~reg_pop);`
93
94
95			`always @(posedge clk or posedge reset)`
96			`if (reset)`
97			`begin`
98			`dout <= #FFD {WIDTH{1'b0}};`
99			`dout_empty <= #FFD 1'b1;`
100			`end`
101			`else if (reg_push)`
102			`begin`
103			`dout <= #FFD din;`
104			`dout_empty <= #FFD 1'b0;`
105			`end`
106			`else if (reg_pop)`
107			`begin`
108			`dout <= #FFD {WIDTH{1'b0}};`
109			`dout_empty <= #FFD 1'b1;`
110			`end`
111			`else if (fifo_pop)`
112			`begin`
113			`dout <= #FFD fifo[ptr_out];`
114			`dout_empty <= #FFD 1'b0;`
115			`end`
116
117			`always @(posedge clk or posedge reset)`
118			`if (reset)`
119			`ptr_in <= #FFD {DEPTH_BITS{1'b0}};`
120			`else if (fifo_push)`
121			`ptr_in <= #FFD ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;`
122
123			`always @(posedge clk or posedge reset)`
124			`if (reset)`
125			`ptr_out <= #FFD {DEPTH_BITS{1'b0}};`
126			`else if (fifo_pop)`
127			`ptr_out <= #FFD ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;`
128
129			`always @(posedge clk)`
130			`if (fifo_push)`
131			`fifo[ptr_in] <= #FFD din;`
132
133
134			`always @(/AUTOSENSE/fifo_push or ptr_in)`
135			`begin`
136			`full_mask_in = {DEPTH{1'b0}};`
137			`full_mask_in[ptr_in] = fifo_push;`
138			`end`
139
140			`always @(/AUTOSENSE/fifo_pop or ptr_out)`
141			`begin`
142			`full_mask_out = {DEPTH{1'b0}};`
143			`full_mask_out[ptr_out] = fifo_pop;`
144			`end`
145
146			`always @(posedge clk or posedge reset)`
147			`if (reset)`
148			`full_mask <= #FFD {DEPTH{1'b0}};`
149			`else if (fifo_push \| fifo_pop)`
150			`full_mask <= #FFD (full_mask & (~full_mask_out)) \| full_mask_in;`
151
152
153			`assign next = \|full_mask;`
154			`assign fifo_empty = ~next;`
155			`assign empty = fifo_empty & dout_empty;`
156			`assign full = SINGLE ? !dout_empty : &full_mask;`
157
158
159
160			`IFDEF STUB`
161			`reg [DEPTH_BITS:0] fullness;`
162
163			`always @(posedge clk or posedge reset)`
164			`if (reset)`
165			`fullness <= #FFD {DEPTH_BITS+1{1'b0}};`
166			`else if (push \| pop)`
167			`fullness <= #FFD fullness + push - pop;`
168
169			`wire overflow = full & fifo_push & (~fifo_pop);`
170			`wire underflow = empty & fifo_pop & (~fifo_push);`
171
172			`always @(posedge overflow)`
173			`begin`
174			`#1;`
175			`if (overflow)`
176			`begin`
177			`$display("-E-%m - overflow.\tTime: %0d ns", $time);`
178			`#1000;`
179			`$finish;`
180			`end`
181			`end`
182			`always @(posedge underflow)`
183			`begin`
184			`#1;`
185			`if (underflow)`
186			`begin`
187			`$display("-E-%m - underflow.\tTime: %0d ns", $time);`
188			`#1000;`
189			`$finish;`
190			`end`
191			`end`
192			`ENDIF STUB`
193
194			`endmodule`
195
196

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[/] [ahb_master/] [trunk/] [src/] [gen/] [prgen_fifo.v] - Blame information for rev 12