In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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The RobustVerilog top source file is ahb_slave.v, it calls the top definition file named def_ahb_slave.txt.
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The default definition file def_ahb_slave.txt generates an AHB slave with a 32 bit data bus.
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Changing the stub parameters should be made only in def_ahb_slave.txt in the src/base directory (adding trace, address bits, data width etc.).