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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_mem.v] - Blame information for rev 4

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1 2 eyalhoc
 
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OUTFILE PREFIX_mem.v
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INCLUDE def_ahb_slave.txt
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ITER BX EXPR(DATA_BITS/8)
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module PREFIX_mem (PORTS);
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   parameter                    MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
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   parameter                    ADDR_LSB  = LOG2(EXPR(DATA_BITS/8));
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   input                        clk;
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   input                        reset;
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   revport                      GROUP_STUB_MEM;
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   reg [DATA_BITS-1:0]          Mem [MEM_WORDS-1:0];
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   reg [DATA_BITS-1:0]          DOUT;
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   wire [DATA_BITS-1:0]         BitSEL;
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   wire [ADDR_BITS-1:ADDR_LSB]  ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
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   wire [ADDR_BITS-1:ADDR_LSB]  ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
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   assign                       BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
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   always @(posedge clk)
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     if (WR)
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       Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       DOUT <= #FFD {DATA_BITS{1'b0}};
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     else if (RD)
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       DOUT <= #FFD Mem[ADDR_RD_word];
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endmodule

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