OpenCores
URL https://opencores.org/ocsvn/ahb_slave/ahb_slave/trunk

Subversion Repositories ahb_slave

[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_mem.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
 
2
OUTFILE PREFIX_mem.v
3
 
4
INCLUDE def_ahb_slave.txt
5
 
6
ITER BX EXPR(DATA_BITS/8)
7
module PREFIX_mem (PORTS);
8
 
9
   parameter                    MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
10
   parameter                    ADDR_LSB  = LOG2(EXPR(DATA_BITS/8));
11
 
12
   input                        clk;
13
   input                        reset;
14
   revport                      GROUP_STUB_MEM;
15
 
16
   reg [DATA_BITS-1:0]          Mem [MEM_WORDS-1:0];
17
   reg [DATA_BITS-1:0]          DOUT;
18
   wire [DATA_BITS-1:0]         BitSEL;
19
   wire [ADDR_BITS-1:ADDR_LSB]  ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
20
   wire [ADDR_BITS-1:ADDR_LSB]  ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
21
 
22
 
23
   assign                       BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
24
 
25
   always @(posedge clk)
26
     if (WR)
27
       Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
28
 
29
   always @(posedge clk or posedge reset)
30
     if (reset)
31
       DOUT <= #FFD {DATA_BITS{1'b0}};
32
     else if (RD)
33
       DOUT <= #FFD Mem[ADDR_RD_word];
34
 
35
 
36
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.