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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Blame information for rev 3

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OUTFILE PREFIX_ram.v
 
INCLUDE def_ahb_slave.txt
 
CHECK CONST(#FFD)
CHECK CONST(PREFIX)
CHECK CONST(ADDR_BITS)
CHECK CONST(DATA_BITS)
 
module PREFIX_ram(PORTS);
 
   input                      clk;
   input                      reset;
 
   revport                    GROUP_STUB_AHB;
 
   port                       GROUP_STUB_MEM;
 
 
`include "prgen_rand.v"
 
 
   //---------------- config parameters ------------------------
   reg                        stall_enable  = 1;  //enable stall on HREADY
   integer                    burst_chance  = 1;  //chance for burst on HREADY stall
   integer                    burst_len     = 10; //length of stall burst in cycles
   integer                    burst_val     = 90; //chance for stall during burst
   integer                    stall_chance  = 10; //chance for stall
 
   reg [ADDR_BITS-1:0]         HRESP_addr = {ADDR_BITS{1'b1}};   //address for response error
   reg [ADDR_BITS-1:0]         TIMEOUT_addr = {ADDR_BITS{1'b1}}; //address for timeout response (no HREADY)
   //-----------------------------------------------------------
 
 
   integer                    burst_stall;
   integer                    stall_chance_valid;
 
   reg                        HRESP;
   reg                        timeout_stall;
 
   reg [1:0]                   HSIZE_d;
   wire                       WR_pre;
   reg                        WR_pre_d;
   wire                       WR;
   wire [ADDR_BITS-1:0]       ADDR_WR_pre;
   reg [ADDR_BITS-1:0]         ADDR_WR;
   reg                        data_phase;
 
   wire [7:0]                  BSEL_wide;
 
   reg                        STALL_pre;
   reg                        STALL;
 
 
   parameter                  TRANS_IDLE   = 2'b00;
   parameter                  TRANS_STALL   = 2'b01;
   parameter                  TRANS_NONSEQ = 2'b10;
   parameter                  TRANS_SEQ    = 2'b11;
 
 
   task set_stall;
      begin
         stall_chance_valid = stall_chance;
      end
   endtask
 
   initial
     begin
        #FFD;
        set_stall;
 
        if (burst_chance > 0)
          forever
            begin
               burst_stall = rand_chance(burst_chance);
 
               if (burst_stall)
                 begin
                    #FFD;
                    stall_chance_valid = burst_val;
                    repeat (burst_len) @(posedge clk);
                    set_stall;
                 end
               else
                 begin
                    @(posedge clk);
                 end
            end
     end
 
 
   always @(posedge clk)
       begin
          #FFD;
          STALL_pre = rand_chance(stall_chance_valid);
       end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       STALL <= #FFD 1'b0;
     else if (stall_enable)
       STALL <= #FFD STALL_pre;
     else
       STALL <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       timeout_stall <= #FFD 1'b0;
     else if ((|HTRANS) & (TIMEOUT_addr == HADDR))
       timeout_stall <= #FFD 1'b1;
     else if (TIMEOUT_addr == 0)
       timeout_stall <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HRESP <= #FFD 1'b0;
     else if ((|HTRANS) & (HRESP_addr == HADDR))
       HRESP <= #FFD 1'b1;
     else if (HREADY)
       HRESP <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       data_phase <= #FFD 1'b0;
     else if (RD)
       data_phase <= #FFD 1'b1;
     else if (HREADY)
       data_phase <= #FFD 1'b0;
 
   assign                     HRDATA = HREADY & data_phase ? DOUT : 'd0;
   assign                     HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);
 
 
   assign                     WR_pre      = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ));
   assign                     WR          = WR_pre_d & HREADY;
   assign                     RD          = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY;
   assign                     ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;
   assign                     ADDR_RD     = {ADDR_BITS{RD}} & HADDR;
   assign                     DIN         = HWDATA;
 
   IFDEF TRUE(DATA_BITS==32)
   assign                     BSEL        = ADDR_WR[2] ? BSEL_wide[7:4] : BSEL_wide[3:0];
   ELSE TRUE(DATA_BITS==32)
   assign                     BSEL        = BSEL_wide;
   ENDIF TRUE(DATA_BITS==32)
 
   assign                     BSEL_wide    =
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd0) ? 8'b0000_0001 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd1) ? 8'b0000_0010 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd2) ? 8'b0000_0100 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd3) ? 8'b0000_1000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd4) ? 8'b0001_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd5) ? 8'b0010_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd6) ? 8'b0100_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd7) ? 8'b1000_0000 :
 
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd0) ? 8'b0000_0011 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd1) ? 8'b0000_1100 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd2) ? 8'b0011_0000 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd3) ? 8'b1100_0000 :
 
                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd0)   ? 8'b0000_1111 :
                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd1)   ? 8'b1111_0000 :
 
                              8'b1111_1111;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          WR_pre_d <= #FFD 1'b0;
          ADDR_WR <= #FFD {ADDR_BITS{1'b0}};
          HSIZE_d <= #FFD 2'b0;
       end
     else if (HREADY)
       begin
          WR_pre_d <= #FFD WR_pre;
          ADDR_WR <= #FFD ADDR_WR_pre;
          HSIZE_d <= #FFD HSIZE;
       end
 
 
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc
2			`OUTFILE PREFIX_ram.v`
3
4			`INCLUDE def_ahb_slave.txt`
5
6			`CHECK CONST(#FFD)`
7			`CHECK CONST(PREFIX)`
8			`CHECK CONST(ADDR_BITS)`
9			`CHECK CONST(DATA_BITS)`
10
11			`module PREFIX_ram(PORTS);`
12
13			`input clk;`
14			`input reset;`
15
16			`revport GROUP_STUB_AHB;`
17
18			`port GROUP_STUB_MEM;`
19
20
21			`include "prgen_rand.v"
22
23
24			`//---------------- config parameters ------------------------`
25			`reg stall_enable = 1; //enable stall on HREADY`
26			`integer burst_chance = 1; //chance for burst on HREADY stall`
27			`integer burst_len = 10; //length of stall burst in cycles`
28			`integer burst_val = 90; //chance for stall during burst`
29			`integer stall_chance = 10; //chance for stall`
30
31			`reg [ADDR_BITS-1:0] HRESP_addr = {ADDR_BITS{1'b1}}; //address for response error`
32			`reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}}; //address for timeout response (no HREADY)`
33			`//-----------------------------------------------------------`
34
35
36			`integer burst_stall;`
37			`integer stall_chance_valid;`
38
39			`reg HRESP;`
40			`reg timeout_stall;`
41
42			`reg [1:0] HSIZE_d;`
43			`wire WR_pre;`
44	3	eyalhoc	`reg WR_pre_d;`
45			`wire WR;`
46	2	eyalhoc	`wire [ADDR_BITS-1:0] ADDR_WR_pre;`
47			`reg [ADDR_BITS-1:0] ADDR_WR;`
48			`reg data_phase;`
49
50			`wire [7:0] BSEL_wide;`
51
52			`reg STALL_pre;`
53			`reg STALL;`
54
55
56			`parameter TRANS_IDLE = 2'b00;`
57			`parameter TRANS_STALL = 2'b01;`
58			`parameter TRANS_NONSEQ = 2'b10;`
59			`parameter TRANS_SEQ = 2'b11;`
60
61
62			`task set_stall;`
63			`begin`
64			`stall_chance_valid = stall_chance;`
65			`end`
66			`endtask`
67
68			`initial`
69			`begin`
70			`#FFD;`
71			`set_stall;`
72
73			`if (burst_chance > 0)`
74			`forever`
75			`begin`
76			`burst_stall = rand_chance(burst_chance);`
77
78			`if (burst_stall)`
79			`begin`
80			`#FFD;`
81			`stall_chance_valid = burst_val;`
82			`repeat (burst_len) @(posedge clk);`
83			`set_stall;`
84			`end`
85			`else`
86			`begin`
87			`@(posedge clk);`
88			`end`
89			`end`
90			`end`
91
92
93			`always @(posedge clk)`
94			`begin`
95			`#FFD;`
96			`STALL_pre = rand_chance(stall_chance_valid);`
97			`end`
98
99
100			`always @(posedge clk or posedge reset)`
101			`if (reset)`
102			`STALL <= #FFD 1'b0;`
103			`else if (stall_enable)`
104			`STALL <= #FFD STALL_pre;`
105			`else`
106			`STALL <= #FFD 1'b0;`
107
108			`always @(posedge clk or posedge reset)`
109			`if (reset)`
110			`timeout_stall <= #FFD 1'b0;`
111			`else if ((\|HTRANS) & (TIMEOUT_addr == HADDR))`
112			`timeout_stall <= #FFD 1'b1;`
113			`else if (TIMEOUT_addr == 0)`
114			`timeout_stall <= #FFD 1'b0;`
115
116			`always @(posedge clk or posedge reset)`
117			`if (reset)`
118			`HRESP <= #FFD 1'b0;`
119			`else if ((\|HTRANS) & (HRESP_addr == HADDR))`
120			`HRESP <= #FFD 1'b1;`
121			`else if (HREADY)`
122			`HRESP <= #FFD 1'b0;`
123
124			`always @(posedge clk or posedge reset)`
125			`if (reset)`
126			`data_phase <= #FFD 1'b0;`
127			`else if (RD)`
128			`data_phase <= #FFD 1'b1;`
129			`else if (HREADY)`
130			`data_phase <= #FFD 1'b0;`
131
132			`assign HRDATA = HREADY & data_phase ? DOUT : 'd0;`
133			`assign HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);`
134
135
136			`assign WR_pre = HWRITE & ((HTRANS == TRANS_NONSEQ) \| (HTRANS == TRANS_SEQ));`
137	3	eyalhoc	`assign WR = WR_pre_d & HREADY;`
138	2	eyalhoc	`assign RD = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) \| (HTRANS == TRANS_SEQ)) & HREADY;`
139			`assign ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;`
140			`assign ADDR_RD = {ADDR_BITS{RD}} & HADDR;`
141			`assign DIN = HWDATA;`
142
143			`IFDEF TRUE(DATA_BITS==32)`
144			`assign BSEL = ADDR_WR[2] ? BSEL_wide[7:4] : BSEL_wide[3:0];`
145			`ELSE TRUE(DATA_BITS==32)`
146			`assign BSEL = BSEL_wide;`
147			`ENDIF TRUE(DATA_BITS==32)`
148
149			`assign BSEL_wide =`
150			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd0) ? 8'b0000_0001 :`
151			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd1) ? 8'b0000_0010 :`
152			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd2) ? 8'b0000_0100 :`
153			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd3) ? 8'b0000_1000 :`
154			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd4) ? 8'b0001_0000 :`
155			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd5) ? 8'b0010_0000 :`
156			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd6) ? 8'b0100_0000 :`
157			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd7) ? 8'b1000_0000 :`
158
159			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd0) ? 8'b0000_0011 :`
160			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd1) ? 8'b0000_1100 :`
161			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd2) ? 8'b0011_0000 :`
162			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd3) ? 8'b1100_0000 :`
163
164			`(HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd0) ? 8'b0000_1111 :`
165			`(HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd1) ? 8'b1111_0000 :`
166
167			`8'b1111_1111;`
168
169
170			`always @(posedge clk or posedge reset)`
171			`if (reset)`
172			`begin`
173	3	eyalhoc	`WR_pre_d <= #FFD 1'b0;`
174	2	eyalhoc	`ADDR_WR <= #FFD {ADDR_BITS{1'b0}};`
175			`HSIZE_d <= #FFD 2'b0;`
176			`end`
177			`else if (HREADY)`
178			`begin`
179	3	eyalhoc	`WR_pre_d <= #FFD WR_pre;`
180	2	eyalhoc	`ADDR_WR <= #FFD ADDR_WR_pre;`
181			`HSIZE_d <= #FFD HSIZE;`
182			`end`
183
184
185			`endmodule`
186
187
188
189

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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Blame information for rev 3