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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 eyalhoc
 
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OUTFILE PREFIX_ram.v
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INCLUDE def_ahb_slave.txt
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CHECK CONST(#FFD)
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CHECK CONST(PREFIX)
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CHECK CONST(ADDR_BITS)
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CHECK CONST(DATA_BITS)
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module PREFIX_ram(PORTS);
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   input                      clk;
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   input                      reset;
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   revport                    GROUP_STUB_AHB;
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   port                       GROUP_STUB_MEM;
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21 4 eyalhoc
CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
22 2 eyalhoc
`include "prgen_rand.v"
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   //---------------- config parameters ------------------------
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   reg                        stall_enable  = 1;  //enable stall on HREADY
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   integer                    burst_chance  = 1;  //chance for burst on HREADY stall
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   integer                    burst_len     = 10; //length of stall burst in cycles
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   integer                    burst_val     = 90; //chance for stall during burst
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   integer                    stall_chance  = 10; //chance for stall
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   reg [ADDR_BITS-1:0]         HRESP_addr = {ADDR_BITS{1'b1}};   //address for response error
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   reg [ADDR_BITS-1:0]         TIMEOUT_addr = {ADDR_BITS{1'b1}}; //address for timeout response (no HREADY)
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   //-----------------------------------------------------------
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   integer                    burst_stall;
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   integer                    stall_chance_valid;
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   reg                        HRESP;
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   reg                        timeout_stall;
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   reg [1:0]                   HSIZE_d;
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   wire                       WR_pre;
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   reg                        WR_pre_d;
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   wire                       WR;
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   wire [ADDR_BITS-1:0]       ADDR_WR_pre;
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   reg [ADDR_BITS-1:0]         ADDR_WR;
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   reg                        data_phase;
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   wire [7:0]                  BSEL_wide;
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   reg                        STALL_pre;
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   reg                        STALL;
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   parameter                  TRANS_IDLE   = 2'b00;
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   parameter                  TRANS_STALL   = 2'b01;
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   parameter                  TRANS_NONSEQ = 2'b10;
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   parameter                  TRANS_SEQ    = 2'b11;
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   task set_stall;
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      begin
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         stall_chance_valid = stall_chance;
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      end
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   endtask
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   initial
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     begin
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        #FFD;
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        set_stall;
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        if (burst_chance > 0)
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          forever
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            begin
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               burst_stall = rand_chance(burst_chance);
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               if (burst_stall)
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                 begin
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                    #FFD;
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                    stall_chance_valid = burst_val;
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                    repeat (burst_len) @(posedge clk);
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                    set_stall;
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                 end
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               else
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                 begin
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                    @(posedge clk);
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                 end
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            end
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     end
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   always @(posedge clk)
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       begin
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          #FFD;
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          STALL_pre = rand_chance(stall_chance_valid);
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       end
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   always @(posedge clk or posedge reset)
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     if (reset)
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       STALL <= #FFD 1'b0;
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     else if (stall_enable)
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       STALL <= #FFD STALL_pre;
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     else
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       STALL <= #FFD 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       timeout_stall <= #FFD 1'b0;
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     else if ((|HTRANS) & (TIMEOUT_addr == HADDR))
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       timeout_stall <= #FFD 1'b1;
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     else if (TIMEOUT_addr == 0)
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       timeout_stall <= #FFD 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       HRESP <= #FFD 1'b0;
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     else if ((|HTRANS) & (HRESP_addr == HADDR))
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       HRESP <= #FFD 1'b1;
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     else if (HREADY)
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       HRESP <= #FFD 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       data_phase <= #FFD 1'b0;
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     else if (RD)
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       data_phase <= #FFD 1'b1;
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     else if (HREADY)
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       data_phase <= #FFD 1'b0;
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   assign                     HRDATA = HREADY & data_phase ? DOUT : 'd0;
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   assign                     HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);
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   assign                     WR_pre      = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ));
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   assign                     WR          = WR_pre_d & HREADY;
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   assign                     RD          = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY;
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   assign                     ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;
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   assign                     ADDR_RD     = {ADDR_BITS{RD}} & HADDR;
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   assign                     DIN         = HWDATA;
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   IFDEF TRUE(DATA_BITS==32)
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   assign                     BSEL        = ADDR_WR[2] ? BSEL_wide[7:4] : BSEL_wide[3:0];
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   ELSE TRUE(DATA_BITS==32)
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   assign                     BSEL        = BSEL_wide;
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   ENDIF TRUE(DATA_BITS==32)
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   assign                     BSEL_wide    =
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd0) ? 8'b0000_0001 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd1) ? 8'b0000_0010 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd2) ? 8'b0000_0100 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd3) ? 8'b0000_1000 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd4) ? 8'b0001_0000 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd5) ? 8'b0010_0000 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd6) ? 8'b0100_0000 :
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                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd7) ? 8'b1000_0000 :
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                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd0) ? 8'b0000_0011 :
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                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd1) ? 8'b0000_1100 :
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                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd2) ? 8'b0011_0000 :
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                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd3) ? 8'b1100_0000 :
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                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd0)   ? 8'b0000_1111 :
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                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd1)   ? 8'b1111_0000 :
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                              8'b1111_1111;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
174 3 eyalhoc
          WR_pre_d <= #FFD 1'b0;
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          ADDR_WR <= #FFD {ADDR_BITS{1'b0}};
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          HSIZE_d <= #FFD 2'b0;
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       end
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     else if (HREADY)
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       begin
180 3 eyalhoc
          WR_pre_d <= #FFD WR_pre;
181 2 eyalhoc
          ADDR_WR <= #FFD ADDR_WR_pre;
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          HSIZE_d <= #FFD HSIZE;
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       end
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endmodule
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