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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Blame information for rev 4

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OUTFILE PREFIX_ram.v
 
INCLUDE def_ahb_slave.txt
 
CHECK CONST(#FFD)
CHECK CONST(PREFIX)
CHECK CONST(ADDR_BITS)
CHECK CONST(DATA_BITS)
 
module PREFIX_ram(PORTS);
 
   input                      clk;
   input                      reset;
 
   revport                    GROUP_STUB_AHB;
 
   port                       GROUP_STUB_MEM;
 
 
CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
`include "prgen_rand.v"
 
 
   //---------------- config parameters ------------------------
   reg                        stall_enable  = 1;  //enable stall on HREADY
   integer                    burst_chance  = 1;  //chance for burst on HREADY stall
   integer                    burst_len     = 10; //length of stall burst in cycles
   integer                    burst_val     = 90; //chance for stall during burst
   integer                    stall_chance  = 10; //chance for stall
 
   reg [ADDR_BITS-1:0]         HRESP_addr = {ADDR_BITS{1'b1}};   //address for response error
   reg [ADDR_BITS-1:0]         TIMEOUT_addr = {ADDR_BITS{1'b1}}; //address for timeout response (no HREADY)
   //-----------------------------------------------------------
 
 
   integer                    burst_stall;
   integer                    stall_chance_valid;
 
   reg                        HRESP;
   reg                        timeout_stall;
 
   reg [1:0]                   HSIZE_d;
   wire                       WR_pre;
   reg                        WR_pre_d;
   wire                       WR;
   wire [ADDR_BITS-1:0]       ADDR_WR_pre;
   reg [ADDR_BITS-1:0]         ADDR_WR;
   reg                        data_phase;
 
   wire [7:0]                  BSEL_wide;
 
   reg                        STALL_pre;
   reg                        STALL;
 
 
   parameter                  TRANS_IDLE   = 2'b00;
   parameter                  TRANS_STALL   = 2'b01;
   parameter                  TRANS_NONSEQ = 2'b10;
   parameter                  TRANS_SEQ    = 2'b11;
 
 
   task set_stall;
      begin
         stall_chance_valid = stall_chance;
      end
   endtask
 
   initial
     begin
        #FFD;
        set_stall;
 
        if (burst_chance > 0)
          forever
            begin
               burst_stall = rand_chance(burst_chance);
 
               if (burst_stall)
                 begin
                    #FFD;
                    stall_chance_valid = burst_val;
                    repeat (burst_len) @(posedge clk);
                    set_stall;
                 end
               else
                 begin
                    @(posedge clk);
                 end
            end
     end
 
 
   always @(posedge clk)
       begin
          #FFD;
          STALL_pre = rand_chance(stall_chance_valid);
       end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       STALL <= #FFD 1'b0;
     else if (stall_enable)
       STALL <= #FFD STALL_pre;
     else
       STALL <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       timeout_stall <= #FFD 1'b0;
     else if ((|HTRANS) & (TIMEOUT_addr == HADDR))
       timeout_stall <= #FFD 1'b1;
     else if (TIMEOUT_addr == 0)
       timeout_stall <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       HRESP <= #FFD 1'b0;
     else if ((|HTRANS) & (HRESP_addr == HADDR))
       HRESP <= #FFD 1'b1;
     else if (HREADY)
       HRESP <= #FFD 1'b0;
 
   always @(posedge clk or posedge reset)
     if (reset)
       data_phase <= #FFD 1'b0;
     else if (RD)
       data_phase <= #FFD 1'b1;
     else if (HREADY)
       data_phase <= #FFD 1'b0;
 
   assign                     HRDATA = HREADY & data_phase ? DOUT : 'd0;
   assign                     HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);
 
 
   assign                     WR_pre      = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ));
   assign                     WR          = WR_pre_d & HREADY;
   assign                     RD          = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY;
   assign                     ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;
   assign                     ADDR_RD     = {ADDR_BITS{RD}} & HADDR;
   assign                     DIN         = HWDATA;
 
   IFDEF TRUE(DATA_BITS==32)
   assign                     BSEL        = ADDR_WR[2] ? BSEL_wide[7:4] : BSEL_wide[3:0];
   ELSE TRUE(DATA_BITS==32)
   assign                     BSEL        = BSEL_wide;
   ENDIF TRUE(DATA_BITS==32)
 
   assign                     BSEL_wide    =
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd0) ? 8'b0000_0001 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd1) ? 8'b0000_0010 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd2) ? 8'b0000_0100 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd3) ? 8'b0000_1000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd4) ? 8'b0001_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd5) ? 8'b0010_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd6) ? 8'b0100_0000 :
                              (HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd7) ? 8'b1000_0000 :
 
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd0) ? 8'b0000_0011 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd1) ? 8'b0000_1100 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd2) ? 8'b0011_0000 :
                              (HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd3) ? 8'b1100_0000 :
 
                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd0)   ? 8'b0000_1111 :
                              (HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd1)   ? 8'b1111_0000 :
 
                              8'b1111_1111;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          WR_pre_d <= #FFD 1'b0;
          ADDR_WR <= #FFD {ADDR_BITS{1'b0}};
          HSIZE_d <= #FFD 2'b0;
       end
     else if (HREADY)
       begin
          WR_pre_d <= #FFD WR_pre;
          ADDR_WR <= #FFD ADDR_WR_pre;
          HSIZE_d <= #FFD HSIZE;
       end
 
 
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc
2			`OUTFILE PREFIX_ram.v`
3
4			`INCLUDE def_ahb_slave.txt`
5
6			`CHECK CONST(#FFD)`
7			`CHECK CONST(PREFIX)`
8			`CHECK CONST(ADDR_BITS)`
9			`CHECK CONST(DATA_BITS)`
10
11			`module PREFIX_ram(PORTS);`
12
13			`input clk;`
14			`input reset;`
15
16			`revport GROUP_STUB_AHB;`
17
18			`port GROUP_STUB_MEM;`
19
20
21	4	eyalhoc	`CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)`
22	2	eyalhoc	`include "prgen_rand.v"
23
24
25			`//---------------- config parameters ------------------------`
26			`reg stall_enable = 1; //enable stall on HREADY`
27			`integer burst_chance = 1; //chance for burst on HREADY stall`
28			`integer burst_len = 10; //length of stall burst in cycles`
29			`integer burst_val = 90; //chance for stall during burst`
30			`integer stall_chance = 10; //chance for stall`
31
32			`reg [ADDR_BITS-1:0] HRESP_addr = {ADDR_BITS{1'b1}}; //address for response error`
33			`reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}}; //address for timeout response (no HREADY)`
34			`//-----------------------------------------------------------`
35
36
37			`integer burst_stall;`
38			`integer stall_chance_valid;`
39
40			`reg HRESP;`
41			`reg timeout_stall;`
42
43			`reg [1:0] HSIZE_d;`
44			`wire WR_pre;`
45	3	eyalhoc	`reg WR_pre_d;`
46			`wire WR;`
47	2	eyalhoc	`wire [ADDR_BITS-1:0] ADDR_WR_pre;`
48			`reg [ADDR_BITS-1:0] ADDR_WR;`
49			`reg data_phase;`
50
51			`wire [7:0] BSEL_wide;`
52
53			`reg STALL_pre;`
54			`reg STALL;`
55
56
57			`parameter TRANS_IDLE = 2'b00;`
58			`parameter TRANS_STALL = 2'b01;`
59			`parameter TRANS_NONSEQ = 2'b10;`
60			`parameter TRANS_SEQ = 2'b11;`
61
62
63			`task set_stall;`
64			`begin`
65			`stall_chance_valid = stall_chance;`
66			`end`
67			`endtask`
68
69			`initial`
70			`begin`
71			`#FFD;`
72			`set_stall;`
73
74			`if (burst_chance > 0)`
75			`forever`
76			`begin`
77			`burst_stall = rand_chance(burst_chance);`
78
79			`if (burst_stall)`
80			`begin`
81			`#FFD;`
82			`stall_chance_valid = burst_val;`
83			`repeat (burst_len) @(posedge clk);`
84			`set_stall;`
85			`end`
86			`else`
87			`begin`
88			`@(posedge clk);`
89			`end`
90			`end`
91			`end`
92
93
94			`always @(posedge clk)`
95			`begin`
96			`#FFD;`
97			`STALL_pre = rand_chance(stall_chance_valid);`
98			`end`
99
100
101			`always @(posedge clk or posedge reset)`
102			`if (reset)`
103			`STALL <= #FFD 1'b0;`
104			`else if (stall_enable)`
105			`STALL <= #FFD STALL_pre;`
106			`else`
107			`STALL <= #FFD 1'b0;`
108
109			`always @(posedge clk or posedge reset)`
110			`if (reset)`
111			`timeout_stall <= #FFD 1'b0;`
112			`else if ((\|HTRANS) & (TIMEOUT_addr == HADDR))`
113			`timeout_stall <= #FFD 1'b1;`
114			`else if (TIMEOUT_addr == 0)`
115			`timeout_stall <= #FFD 1'b0;`
116
117			`always @(posedge clk or posedge reset)`
118			`if (reset)`
119			`HRESP <= #FFD 1'b0;`
120			`else if ((\|HTRANS) & (HRESP_addr == HADDR))`
121			`HRESP <= #FFD 1'b1;`
122			`else if (HREADY)`
123			`HRESP <= #FFD 1'b0;`
124
125			`always @(posedge clk or posedge reset)`
126			`if (reset)`
127			`data_phase <= #FFD 1'b0;`
128			`else if (RD)`
129			`data_phase <= #FFD 1'b1;`
130			`else if (HREADY)`
131			`data_phase <= #FFD 1'b0;`
132
133			`assign HRDATA = HREADY & data_phase ? DOUT : 'd0;`
134			`assign HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);`
135
136
137			`assign WR_pre = HWRITE & ((HTRANS == TRANS_NONSEQ) \| (HTRANS == TRANS_SEQ));`
138	3	eyalhoc	`assign WR = WR_pre_d & HREADY;`
139	2	eyalhoc	`assign RD = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) \| (HTRANS == TRANS_SEQ)) & HREADY;`
140			`assign ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;`
141			`assign ADDR_RD = {ADDR_BITS{RD}} & HADDR;`
142			`assign DIN = HWDATA;`
143
144			`IFDEF TRUE(DATA_BITS==32)`
145			`assign BSEL = ADDR_WR[2] ? BSEL_wide[7:4] : BSEL_wide[3:0];`
146			`ELSE TRUE(DATA_BITS==32)`
147			`assign BSEL = BSEL_wide;`
148			`ENDIF TRUE(DATA_BITS==32)`
149
150			`assign BSEL_wide =`
151			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd0) ? 8'b0000_0001 :`
152			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd1) ? 8'b0000_0010 :`
153			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd2) ? 8'b0000_0100 :`
154			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd3) ? 8'b0000_1000 :`
155			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd4) ? 8'b0001_0000 :`
156			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd5) ? 8'b0010_0000 :`
157			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd6) ? 8'b0100_0000 :`
158			`(HSIZE_d == 2'b00) & (ADDR_WR[2:0] == 3'd7) ? 8'b1000_0000 :`
159
160			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd0) ? 8'b0000_0011 :`
161			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd1) ? 8'b0000_1100 :`
162			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd2) ? 8'b0011_0000 :`
163			`(HSIZE_d == 2'b01) & (ADDR_WR[2:1] == 2'd3) ? 8'b1100_0000 :`
164
165			`(HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd0) ? 8'b0000_1111 :`
166			`(HSIZE_d == 2'b10) & (ADDR_WR[2] == 1'd1) ? 8'b1111_0000 :`
167
168			`8'b1111_1111;`
169
170
171			`always @(posedge clk or posedge reset)`
172			`if (reset)`
173			`begin`
174	3	eyalhoc	`WR_pre_d <= #FFD 1'b0;`
175	2	eyalhoc	`ADDR_WR <= #FFD {ADDR_BITS{1'b0}};`
176			`HSIZE_d <= #FFD 2'b0;`
177			`end`
178			`else if (HREADY)`
179			`begin`
180	3	eyalhoc	`WR_pre_d <= #FFD WR_pre;`
181	2	eyalhoc	`ADDR_WR <= #FFD ADDR_WR_pre;`
182			`HSIZE_d <= #FFD HSIZE;`
183			`end`
184
185
186			`endmodule`
187
188
189
190

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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Blame information for rev 4