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[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_trace.v] - Blame information for rev 8

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1 7 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_trace.v
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INCLUDE def_ahb_slave.txt
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module PREFIX_trace(PORTS);
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   parameter                  SLAVE_NUM = 0;
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   input                      clk;
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   input                      reset;
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   input                      GROUP_STUB_MEM;
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   reg                        RD_d;
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   reg [ADDR_BITS-1:0]         ADDR_RD_d;
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   wire [31:0]                 ADDR_WR_disp =  ADDR_WR;
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   wire [31:0]                 ADDR_RD_disp =  ADDR_RD_d;
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   reg [64*8-1:0]             filename;
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   integer                    file_ptr;
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   initial
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     begin
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        //erase trace
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        file_ptr = $fopen({"PREFIX.trc"}, "w");
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        $fwrite(file_ptr, "\n");
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        $fclose(file_ptr);
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     end
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
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          ADDR_RD_d <= #FFD 'd0;
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          RD_d <= #FFD 'd0;
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       end
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     else
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       begin
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          ADDR_RD_d <= #FFD ADDR_RD;
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          RD_d <= #FFD RD;
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       end
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   always @(posedge clk)
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     if (WR)
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       begin
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          file_ptr = $fopen({"PREFIX.trc"}, "a");
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          $fwrite(file_ptr, "%16d: PREFIX%0d WR: Addr: 0x%EXPR(ADDR_BITS/4)h, Data: 0x%EXPR(DATA_BITS/4)h, Bsel: 0x%EXPR(DATA_BITS/32)h\n", $time, SLAVE_NUM, ADDR_WR_disp, DIN, BSEL);
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          $fclose(file_ptr);
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       end
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   always @(posedge clk)
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     if (RD_d)
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       begin
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          file_ptr = $fopen({"PREFIX.trc"}, "a");
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          $fwrite(file_ptr, "%16d: PREFIX%0d RD: Addr: 0x%EXPR(ADDR_BITS/4)h, Data: 0x%EXPR(DATA_BITS/4)h\n", $time, SLAVE_NUM, ADDR_RD_disp, DOUT);
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          $fclose(file_ptr);
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       end
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endmodule
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