Subversion Repositories ahb_system_generator

#!/usr/bin/perl  

use Tk;

use Time::Local;

#use strict;

#use strict 'subs';

#LOCAL VARIABLES

my $infile="./ahb_generate.conf";

my $conffile="./ahb_configure.vhd";

my $matfile="./ahb_matrix.vhd";

my $sysfile="./ahb_system.vhd";

my $tbfile="./ahb_tb.vhd";

my @master_list;

my @slave_list;

my @mst_list;

my @slv_list;

my @pslv_list;

my $inst_name;

my $entity;

my $num_arb;

my $num_arb_msts;

my $def_arb_mst;

my @arb_master_list;

my @arb_slave_list;

my $num_brg;

my $num_brg_slvs;

my $def_brg_slv;

my $brg_master;

my @brg_slave_list;

my $num_apb;

my $num_apb_slvs;

my $apb_max_addr;

my $apb_slave_id;

my @apb_slave_list;

my $alg_number;

my @alg_list = qw/"Fixed" "Round-Robin" "Pseudo-Random" "Locked-Fixed" "Locked-R-R" "Locked-P-R"/;

my @gen_signal;

my @gen_ahb_signal;

my @gen_conf;

my @gen_comp;

my @gen_tbcomp;

my @gen_uut;

my @ass_signal;

my $curr_line;

my $cnt;

my $item;

my $chk=0;

my @tmp_chk;

my @tmp_lst;

my $tmp;

my $mat;

my @matrix;

# GUI SHAPING

my (@pt)=qw/-side top -fill both -anchor n -pady 10/;

my (@pc)=qw/-side top -fill both -anchor center -pady 10/;

my (@pw)=qw/-side left -fill both -anchor w -padx 10/;

my (@pe)=qw/-side right -fill both -anchor e -padx 10/;

# GUI FSM

my $state='WinGlobal';

my $i=0;

my $j;

my $a;

my $b;

my $c;

my $d;

my $e;

my $f;

my $mw;

my $frame;

my $done='disabled';

my $masters=-1;

my $slaves=-1;

my $pslaves=-1;

my $arbs=-1;

my $ahbs=-1;

my $apbs=-1;

my @master;

my @slave;

my @pslave;

my @arb;

my @ahb;

my @apb;

my @uut;

my @tmp_mat;

sub ResetConf

{

$state='WinGlobal';

$masters=-1;

$slaves=-1;

$pslaves=-1;

$arbs=-1;

$ahbs=-1;

$apbs=-1;

$#master=-1;

$#slave=-1;

$#pslave=-1;

$#arb=-1;

$#ahb=-1;

$#apb=-1;

}

sub ReadConf

{

$state='WinGlobal';

seek(file1,0,0);

$masters=-1;

$slaves=-1;

$pslaves=-1;

$arbs=-1;

$ahbs=-1;

$apbs=-1;

while(defined($curr_line=<file1>)) {

    chop $curr_line;

    if($curr_line =~ /^#/) {

       print "# Comment skipped ...\n";

    } elsif($curr_line =~ /^(ahb_master),(\w+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+)$/){

     $masters++;

     print "Reading AHB Master $masters...\n";

     $master[$masters]{"module"}=$1;

     $master[$masters]{"name"}=$2;

     $master[$masters]{"id"}=$masters;

     $master[$masters]{"fifo_ln"}=$3;

     $master[$masters]{"fifo_he"}=$4;

     $master[$masters]{"fifo_hf"}=$5;

     $master[$masters]{"num_bits_addr"}=$6;

     $master[$masters]{"write_burst"}=$7;

     $master[$masters]{"read_burst"}=$8;

     $master[$masters]{"write_lat"}=$9;

     $master[$masters]{"read_lat"}=$10;

         $uut[$masters]{"base_addr"}=$11;

    } elsif($curr_line =~ /^(ahb_slave),(\w+),\((.*)\),(\w+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+),(\d+)$/){

     $slaves++;

     print "Reading AHB Slave $slaves...\n";

     $slave[$slaves]{"module"}=$1;

     $slave[$slaves]{"name"}=$2;

     foreach $item (split(',',$3)) {

       $slave[$slaves]{"list"} .= " $item";

       }

     $slave[$slaves]{"id"}=$slaves;

     $slave[$slaves]{"type"}=$4;

     $slave[$slaves]{"add_h"}=$5;

     $slave[$slaves]{"add_l"}=$6;

     $slave[$slaves]{"add_hh"}=$7;

     $slave[$slaves]{"add_ll"}=$8;

     $slave[$slaves]{"alg"}=$9;

     $slave[$slaves]{"fifo_ln"}=$10;

     $slave[$slaves]{"fifo_he"}=$11;

     $slave[$slaves]{"fifo_hf"}=$12;

     $slave[$slaves]{"num_bits_addr"}=$13;

     $slave[$slaves]{"write_burst"}=$14;

     $slave[$slaves]{"read_burst"}=$15;

     $slave[$slaves]{"write_lat"}=$16;

     $slave[$slaves]{"read_lat"}=$17;

    } elsif($curr_line =~ /^(apb_slave),(\w+),(\d+),(\d+),(\d+),(\d+),(\d+)$/){

     $pslaves++;

     print "Reading APB Slave $pslaves...\n";

     $pslave[$pslaves]{"module"}=$1;

     $pslave[$pslaves]{"name"}=$2;

     $pslave[$pslaves]{"id"}=$pslaves;

     $pslave[$pslaves]{"add_h"}=$3;

     $pslave[$pslaves]{"add_l"}=$4;

     $pslave[$pslaves]{"add_hh"}=$5;

     $pslave[$pslaves]{"add_ll"}=$6;

     $pslave[$pslaves]{"num_bits_addr"}=$7;

    } elsif($curr_line =~ /^(ahb_arbiter),(\w+),(\d+),\((.*)\),\((.*)\),(\d+)$/){

     $arbs++;

     print "Reading AHB Arbiter $arbs...\n";

     $arb[$arbs]{"module"}=$1;

     $arb[$arbs]{"name"}=$2;

     $arb[$arbs]{"id"}=$arbs;

     $arb[$arbs]{"def"}=$3;

     foreach $item (split(',',$4)) {

       $arb[$arbs]{"m_list"} .= " $item";

       }

     foreach $item (split(',',$5)) {

       $arb[$arbs]{"s_list"} .= " $item";

       }

     $arb[$arbs]{"alg"}=$6;

    } elsif($curr_line =~ /^(ahb_bridge),(\w+),(\d+),(\d+),\((.*)\),(\d+)$/){

     $ahbs++;

     print "Reading AHB Bridge $ahbs...\n";

     $ahb[$ahbs]{"module"}=$1;

     $ahb[$ahbs]{"name"}=$2;

     $ahb[$ahbs]{"id"}=$ahbs;

     $ahb[$ahbs]{"alg"}=$3;

     $ahb[$ahbs]{"def"}=$4;

     foreach $item (split(',',$5)) {

       $ahb[$ahbs]{"list"} .= " $item";

       }

     $ahb[$ahbs]{"mst"}=$6;

    } elsif($curr_line =~ /^(apb_bridge),(\w+),(\d+),(\d+),\((.*)\)$/){

     $apbs++;

     print "Reading APB Bridge $apbs...\n";

     $apb[$apbs]{"module"}=$1;

     $apb[$apbs]{"name"}=$2;

     $apb[$apbs]{"id"}=$apbs;

     $apb[$apbs]{"num_bits_addr"}=$3;

     $apb[$apbs]{"slv"}=$4;

     foreach $item (split(',',$5)) {

       $apb[$apbs]{"list"} .= " $item";

       }

    } else {

        print "#### wrong format!!!\n";

    }

#    close(file1);

}

sub SaveConf

{

$state='WinGlobal';

open(file1,">$infile")|| die "Cannot write ahb configuration output file $infile\n";

$i=0;

while($i<=$masters) {

     print file1 "# ahb_master $i: module,name,fifo_length,fifo_he,fifo_hf,num_bits_adds,write_burst,read_burst,write_lat,read_lat,UUT_BaseAddr\n";

     print file1 "$master[$i]{\"module\"},";

     print file1 "$master[$i]{\"name\"},";

     print file1 "$master[$i]{\"fifo_ln\"},";

     print file1 "$master[$i]{\"fifo_he\"},";

     print file1 "$master[$i]{\"fifo_hf\"},";

     print file1 "$master[$i]{\"num_bits_addr\"},";

     print file1 "$master[$i]{\"write_burst\"},";

     print file1 "$master[$i]{\"read_burst\"},";

     print file1 "$master[$i]{\"write_lat\"},";

     print file1 "$master[$i]{\"read_lat\"},";

         print file1 "$uut[$i]{\"base_addr\"}\n";

     $i++;

     }

$i=0;

while($i<=$slaves) {

     print file1 "# ahb_slave $i:

# module,name,NOT_USED,type,add_h,add_l,remap add_h,remap add_l,NOT_USED,fifo_le,fifo_he,fifo_hf,num_bits_adds,write_burst,read_burst,write_lat,read_lat\n";

     print file1 "$slave[$i]{\"module\"},";

     print file1 "$slave[$i]{\"name\"},";

     print file1 "(";

     $_=$slave[$i]{"list"};

     s/^[ ]+//g;

     s/[ ]+$//g;

     s/[ ]+/,/g;

     print file1 "$_),";

#     print file1 "$slave[$i]{\"id\"},";

     print file1 "$slave[$i]{\"type\"},";

     print file1 "$slave[$i]{\"add_h\"},";

     print file1 "$slave[$i]{\"add_l\"},";

     print file1 "$slave[$i]{\"add_hh\"},";

     print file1 "$slave[$i]{\"add_ll\"},";

     print file1 "$slave[$i]{\"alg\"},";

     print file1 "$slave[$i]{\"fifo_ln\"},";

     print file1 "$slave[$i]{\"fifo_he\"},";

     print file1 "$slave[$i]{\"fifo_hf\"},";

     print file1 "$slave[$i]{\"num_bits_addr\"},";

     print file1 "$slave[$i]{\"write_burst\"},";

     print file1 "$slave[$i]{\"read_burst\"},";

     print file1 "$slave[$i]{\"write_lat\"},";

     print file1 "$slave[$i]{\"read_lat\"}\n";

     $i++;

}

$i=0;

while($i<=$pslaves) {

     print file1 "# apb_slave $i: module,name,add_h,add_l,remap add_h,remap add_l,num_bits_adds\n";

     print file1 "$pslave[$i]{\"module\"},";

     print file1 "$pslave[$i]{\"name\"},";

#     print file1 "$pslave[$i]{\"id\"},";

     print file1 "$pslave[$i]{\"add_h\"},";

     print file1 "$pslave[$i]{\"add_l\"},";

     print file1 "$pslave[$i]{\"add_hh\"},";

     print file1 "$pslave[$i]{\"add_ll\"},";

     print file1 "$pslave[$i]{\"num_bits_addr\"}\n";

     $i++;

 }

$i=0;

while($i<=$arbs) {

     print file1 "# ahb_arbiter $i: module,name,default master,master_list,slave_list,arbitration type\n";

     print file1 "$arb[$i]{\"module\"},";

     print file1 "$arb[$i]{\"name\"},";

#     print file1 "$arb[$i]{\"id\"},";

     print file1 "$arb[$i]{\"def\"},";

     print file1 "(";

     $_=$arb[$i]{"m_list"};

     s/^[ ]+//g;

     s/[ ]+$//g;

     s/[ ]+/,/g;

     print file1 "$_),";

     print file1 "(";

     $_=$arb[$i]{"s_list"};

     s/^[ ]+//g;

     s/[ ]+$//g;

     s/[ ]+/,/g;

     print file1 "$_),";

     print file1 "$arb[$i]{\"alg\"}\n";

     $i++;

}

$i=0;

while($i<=$ahbs) {

     print file1 "# ahb_bridge $i: module,name,arbitration type,default slave,slave_list,master\n";

     print file1 "$ahb[$i]{\"module\"},";

     print file1 "$ahb[$i]{\"name\"},";

#     print file1 "$ahb[$i]{\"id\"},";

     print file1 "$ahb[$i]{\"alg\"},";

     print file1 "$ahb[$i]{\"def\"},";

     print file1 "(";

     $_=$ahb[$i]{"list"};

     s/^[ ]+//g;

     s/[ ]+$//g;

     s/[ ]+/,/g;

     print file1 "$_),";

     print file1 "$ahb[$ahbs]{\"mst\"}\n";

     $i++;

}

$i=0;

while($i<=$apbs) {

     print file1 "# apb_bridge $i: module,name,num_bits_adds,slave,periph list\n";

     print file1 "$apb[$i]{\"module\"},";

     print file1 "$apb[$i]{\"name\"},";

#     print file1 "$apb[$i]{\"id\"},";

     print file1 "$apb[$i]{\"num_bits_addr\"},";

     print file1 "$apb[$i]{\"slv\"},";

     print file1 "(";

     $_=$apb[$i]{"list"};

     s/^[ ]+//g;

     s/[ ]+$//g;

     s/[ ]+/,/g;

     print file1 "$_)\n";

     $i++;

 }

}

sub gen_master

{

    my $tmp_mst=shift(@_);

    @gen_tbcomp = (@gen_tbcomp, "

$tmp_mst->{\"name\"}: ahb_master

generic map(

        fifohempty_level => $tmp_mst->{\"fifo_he\"},

        fifohfull_level => $tmp_mst->{\"fifo_hf\"},

        fifo_length => $tmp_mst->{\"fifo_ln\"})

port map (

        hresetn => hresetn,

        hclk => hclk,

        mst_in => ahb_mst_$tmp_mst->{\"id\"}_in,

        mst_out => ahb_mst_$tmp_mst->{\"id\"}_out,

        dma_start => dma_start($tmp_mst->{\"id\"}),

        m_wrap_out => m_wrap_out($tmp_mst->{\"id\"}),

        m_wrap_in => m_wrap_in($tmp_mst->{\"id\"}),

        eot_int => eot_int($tmp_mst->{\"id\"}),

        slv_running => zero,

        mst_running => open);

$tmp_mst->{\"name\"}_wrap: mst_wrap

generic map(

--synopsys translate_off

dump_file => \"m$tmp_mst->{\"id\"}.log\",

dump_type => dump_all,

--synopsys translate_on

ahb_max_addr => $tmp_mst->{\"num_bits_addr\"},

m_const_lat_write => $tmp_mst->{\"write_lat\"},

m_const_lat_read => $tmp_mst->{\"read_lat\"},

m_write_burst => $tmp_mst->{\"write_burst\"},

m_read_burst => $tmp_mst->{\"read_burst\"})

port map(

        hresetn => hresetn,

        clk => hclk,

        conf => conf($tmp_mst->{\"id\"}),

        dma_start => dma_start($tmp_mst->{\"id\"}),

        m_wrap_in => m_wrap_out($tmp_mst->{\"id\"}),

        m_wrap_out => m_wrap_in($tmp_mst->{\"id\"}));

");

    @gen_uut = (@gen_uut, "

uut_stimulator_$tmp_mst->{\"id\"}: uut_stimulator

generic map(

enable => 1,

stim_type => stim_$tmp_mst->{\"id\"},

eot_enable => 1)

port map(

         hclk => hclk,

         hresetn => hresetn,

         amba_error => zero,

         eot_int => eot_int($tmp_mst->{\"id\"}),

         conf => conf($tmp_mst->{\"id\"}),

         sim_end => sim_end($tmp_mst->{\"id\"}));

");

}

sub gen_slave {

my $tmp_slv=shift(@_);

#if ($tmp_slv->{"type"}=='wait') {

#@gen_tbcomp = (@gen_tbcomp, "

#$tmp_slv->{\"name\"}: ahb_single_slave");

#} else {

@gen_tbcomp = (@gen_tbcomp, "

$tmp_slv->{\"name\"}: ahb_slave_$tmp_slv->{\"type\"}");

#};

@gen_tbcomp = (@gen_tbcomp, "

generic map(

        num_slv => $tmp_slv->{\"id\"},

        fifohempty_level => $tmp_slv->{\"fifo_he\"},

        fifohfull_level => $tmp_slv->{\"fifo_hf\"},

        fifo_length => $tmp_slv->{\"fifo_ln\"})

port map (

        hresetn => hresetn,

        hclk => hclk,

        remap => remap,

        slv_in => ahb_slv_$tmp_slv->{\"id\"}_in,

        slv_out => ahb_slv_$tmp_slv->{\"id\"}_out,

        s_wrap_out => s_wrap_out($tmp_slv->{\"id\"}),

        s_wrap_in => s_wrap_in($tmp_slv->{\"id\"}),

        mst_running => zero,

        prior_in => zero,

        slv_running => open,

        slv_err => open);

$tmp_slv->{\"name\"}_wrap: slv_mem

generic map(

--synopsys translate_off

dump_file => \"s$tmp_slv->{\"id\"}.log\",

dump_type => dump_all,

--synopsys translate_on

ahb_max_addr => $tmp_slv->{\"num_bits_addr\"},

s_const_lat_write => $tmp_slv->{\"write_lat\"},

s_const_lat_read => $tmp_slv->{\"read_lat\"},

s_write_burst => $tmp_slv->{\"write_burst\"},

s_read_burst => $tmp_slv->{\"read_burst\"})

port map(

        hresetn => hresetn,

        clk => hclk,

        conf => no_conf_s,

        dma_start => open,

        s_wrap_in => s_wrap_out($tmp_slv->{\"id\"}),

        s_wrap_out => s_wrap_in($tmp_slv->{\"id\"}));

");

}

sub gen_pslave

{

my $tmp_pslv=shift(@_);

@gen_tbcomp = (@gen_tbcomp, "

$tmp_pslv->{\"name\"}: apb_slave

generic map(

        --synopsys translate_off

        dump_file => \"p$tmp_pslv->{\"id\"}.log\",

        --synopsys translate_on

        apb_slv_addr => $tmp_pslv->{\"num_bits_addr\"})

port map (

        hresetn => hresetn,

        hclk => hclk,

        apb_in => apb_slv_$tmp_pslv->{\"id\"}_in,

        apb_out => apb_slv_$tmp_pslv->{\"id\"}_out);

");

}

sub gen_arbiter

{

    my $tmp_arb=shift(@_);

    @arb_master_list = split(' ',$tmp_arb->{"m_list"});

    $def_arb_mst = $arb_master_list[0];

    $num_arb_msts = $#arb_master_list+1;

    @arb_slave_list = split(' ',$tmp_arb->{"s_list"});

    print "\nModule/ID: $tmp_arb->{\"module\"}, $tmp_arb->{\"id\"}";

    print "\nName: $tmp_arb->{\"name\"}";

    print "\nMasters'list:\n(@arb_master_list)";

    print "\nDefault master: $tmp_arb->{\"def\"}";

    print "\nType of arbitration: ".$alg_list[$tmp_arb->{"alg"}];

    print "\nSlaves'list:\n(@arb_slave_list)\n\n";

    $cnt=0;

    foreach $item (@arb_master_list) {

      ++$mst_list[$item];

      if ($item==$tmp_arb->{"def"}) {$def_arb_mst=$cnt;}

      $cnt++;

      }

    foreach $item (@arb_slave_list) {++$slv_list[$item];}

    @gen_comp = (@gen_comp,"

$tmp_arb->{\"name\"}: $tmp_arb->{\"module\"}

generic map(

num_arb => $tmp_arb->{\"id\"},

num_arb_msts => $num_arb_msts,

num_slvs => ".($#arb_slave_list+1).",

def_arb_mst => $def_arb_mst,

alg_number => $tmp_arb->{\"alg\"})

port map(

  hresetn => hresetn,

  hclk => hclk,

  remap => remap,

  mst_in_v => mst_in_arb_$tmp_arb->{\"id\"}_v(".($num_arb_msts-1)." downto 0),

  mst_out_v => mst_out_arb_$tmp_arb->{\"id\"}_v(".($num_arb_msts-1)." downto 0),

  slv_in_v => slv_in_arb_$tmp_arb->{\"id\"}_v($#arb_slave_list downto 0),

  slv_out_v => slv_out_arb_$tmp_arb->{\"id\"}_v($#arb_slave_list downto 0));

");

    @gen_signal = (@gen_signal,

"signal mst_out_arb_$tmp_arb->{\"id\"}_v: mst_in_v_t(".($num_arb_msts-1)." downto 0);

signal mst_in_arb_$tmp_arb->{\"id\"}_v: mst_out_v_t(".($num_arb_msts-1)." downto 0);

signal slv_out_arb_$tmp_arb->{\"id\"}_v: slv_in_v_t($#arb_slave_list downto 0);

signal slv_in_arb_$tmp_arb->{\"id\"}_v: slv_out_v_t($#arb_slave_list downto 0);

");

    $cnt = $#arb_master_list;

    foreach $item (@arb_master_list){

        @ass_signal = (@ass_signal, "ahb_mst_".$item."_in <= mst_out_arb_$tmp_arb->{\"id\"}_v($cnt);\n");

        @ass_signal = (@ass_signal, "mst_in_arb_$tmp_arb->{\"id\"}_v($cnt) <= ahb_mst_".$item."_out;\n");

        $cnt--;

    }

    $cnt = $#arb_slave_list;

    foreach $item (@arb_slave_list){

        @ass_signal = (@ass_signal, "ahb_slv_".$item."_in <= slv_out_arb_$tmp_arb->{\"id\"}_v($cnt);\n");

        @ass_signal = (@ass_signal, "slv_in_arb_$tmp_arb->{\"id\"}_v($cnt) <= ahb_slv_".$item."_out;\n");

        $cnt--;

    }

}

sub gen_bridge

{

    my $tmp_brg=shift(@_);

    @brg_slave_list = split(' ',$tmp_brg->{"list"});

    $def_brg_slv=$brg_slave_list[0];

    $num_brg_slvs = $#brg_slave_list+1;

    print "Module/ID: $tmp_brg->{\"module\"}, $tmp_brg->{\"id\"}";

    print "\nName: $tmp_brg->{\"name\"}";

    print "\nSlaves'list:\n(@brg_slave_list)";

    print "\nDefault slave: $tmp_brg->{\"def\"}";

    print "\nType of arbitration: ".$alg_list[$tmp_brg->{"alg"}];

    print "\nMaster: $tmp_brg->{\"mst\"}\n\n";

    --$mst_list[$tmp_brg->{"mst"}];

    @gen_signal = (@gen_signal, "signal ahb_mst_$tmp_brg->{\"mst\"}_in: mst_in_t;\n");

    @gen_signal = (@gen_signal, "signal ahb_mst_$tmp_brg->{\"mst\"}_out: mst_out_t;\n");

    $cnt = 0;

    foreach $item (@brg_slave_list) {

      --$slv_list[$item];

      @gen_signal = (@gen_signal, "signal ahb_slv_".$item."_in: slv_in_t;\n");

      @gen_signal = (@gen_signal, "signal ahb_slv_".$item."_out: slv_out_t;\n");

      if ($item==$tmp_brg->{"def"}) {$def_brg_slv=$cnt;}