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[/] [ahbmaster/] [trunk/] [AHBMASTER_FIC.vhd] - Blame information for rev 2

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1 2 uson
-- Converted from AHBMASTER_FIC.v
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-- AHBMASTER_FIC.v
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--`timescale 1 ns / 100 ps
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-------------------------------------------------------------------------------
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-- Title      : Custom AHB master
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-------------------------------------------------------------------------------
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-- File       : AHBMASTER_FIC.vhd
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-- Author     : uson
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-- Company    : 
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-- Device     : microsemi FPGA
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-- Standard   : VHDL
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-- Special Notes: This is code is for refernce only. You shouldn't use it in real 
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-- design as it is
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-------------------------------------------------------------------------------
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-- Description:
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-- This code creates an AHB-Lite master wrapper to FIC 
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-- The AHB interface to Logic will initaite AMBA transaction by sending write/read signals.
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-------------------------------------------------------------------------------
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-- Revisions  : V1.0 
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-------------------------------------------------------------------------------*/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity AHBMASTER_FIC is
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        port (
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                HCLK    : in  std_logic;
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                HRESETn : in  std_logic;
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        --AHB interface to Logic
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                LREAD   : in  std_logic;
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                LWRITE  : in  std_logic;
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                ADDR    : in  std_logic_vector(31 downto 0);
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                DATAIN  : in  std_logic_vector(31 downto 0);
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                DATAOUT : out std_logic_vector(31 downto 0);
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        -- AHB Side Interfacing with FIC 
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                HADDR   : out std_logic_vector(31 downto 0);
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                HTRANS  : out std_logic_vector(1 downto 0);
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                HWRITE  : out std_logic;
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                HSIZE   : out std_logic_vector(2 downto 0);
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                HBURST  : out std_logic_vector(2 downto 0);
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                HPROT   : out std_logic_vector(3 downto 0);
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                HWDATA  : out std_logic_vector(31 downto 0);
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                HRDATA  : in  std_logic_vector(31 downto 0);
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                HREADY  : in  std_logic;
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                HRESP   : in  std_logic_vector(1 downto 0);
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                RESP_err        : out std_logic_vector(1 downto 0);
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                ahb_busy        : out std_logic
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        );
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end AHBMASTER_FIC;
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architecture RTL of AHBMASTER_FIC is
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        -- AHB FSM States
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        signal ahb_fsm_current_state    : std_logic_vector(2 downto 0);
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        constant Idle   : std_logic_vector(2 downto 0) := "000";
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        constant Write_FIC_0    : std_logic_vector(2 downto 0) := "001";
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        constant Write_FIC_1    : std_logic_vector(2 downto 0) := "010";
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        constant Write_FIC_2    : std_logic_vector(2 downto 0) := "011";
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        constant Read_FIC_0     : std_logic_vector(2 downto 0) := "100";
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        constant Read_FIC_1     : std_logic_vector(2 downto 0) := "101";
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        constant Read_FIC_2     : std_logic_vector(2 downto 0) := "110";
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        signal HADDR_int        : std_logic_vector(31 downto 0); --temporary hold the address
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        signal HWDATA_int       : std_logic_vector(31 downto 0); --temporary hold the data
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        signal HSIZE_int        : std_logic_vector(2 downto 0);
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        -- since the current coreahblite is 32 bit, we are using Hsize=10 (32-bit), but can be changed
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-- WARNING(5) in line 54: Please write a signal width part in the following sentence, manually.
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        constant Data_size      : std_logic_vector(7 downto 0) := x"20"; -- 32
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begin
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        RESP_err    <= HRESP;
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        HBURST      <= "000";
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        HPROT       <= "0011";
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        HSIZE_int       <= "010";
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--generate
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--    if (Data_size == 32) begin
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--        assign HSIZE_int  = 2'b10;
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--    end
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--    else if (Data_size == 16) begin
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--        assign HSIZE_int  = 2'b01;
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--    end
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--    else if (Data_size ==  8) begin
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--        assign HSIZE_int  = 2'b00;
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--    end
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--endgenerate
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        -- FSM That Acts as Master on AHB Bus
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        -- Assuming only Non-Sequential & Idle
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        v2v_pr_0:process (HCLK, HRESETn)
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        begin
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                if (HRESETn = '0') then
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                        HADDR   <= x"00000000";
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                        HTRANS  <= "00";                        --Idle
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                        HWRITE  <= '0';
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                        HSIZE   <= "010";                       -- 32 Bit Mode
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                        HWDATA  <= x"00000000";
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                        DATAOUT <= x"00000000";
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                        ahb_fsm_current_state   <= Idle;
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                        ahb_busy        <= '0';
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                elsif (HCLK'event and HCLK = '1') then
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                        case (ahb_fsm_current_state) is
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                        when Idle =>
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                        --0x00
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                                if (LWRITE = '1') then
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                                        ahb_fsm_current_state   <= Write_FIC_0;
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                                        HADDR   <= ADDR;
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                                        HADDR_int       <= ADDR;
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                                        HWDATA_int      <= DATAIN;
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                                        ahb_busy        <= '1';
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                                elsif (LREAD = '1') then
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                                        ahb_fsm_current_state   <= Read_FIC_0;
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                                        HADDR   <= ADDR;
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                                        HADDR_int       <= ADDR;
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                                        ahb_busy        <= '1';
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                                else
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                                        ahb_fsm_current_state   <= Idle;
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                                end if;
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                        when Write_FIC_0 =>
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                        --0x01  store the address+control signals and apply to coreahblite
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                                HTRANS  <= "10";
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                                HSIZE   <= HSIZE_int;
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                                HWRITE  <= '1';
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                                ahb_fsm_current_state   <= Write_FIC_1;
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                                ahb_busy        <= '1';
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                        when Write_FIC_1 =>
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                        --0x02 
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                                if (HREADY = '0') then                                   --keep the address+control signals when slave is not ready yet
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                                        HTRANS  <= "10";
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                                        HSIZE   <= HSIZE_int;
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                                        HWRITE  <= '1';
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                                        HADDR   <= HADDR_int;
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                                        ahb_fsm_current_state   <= Write_FIC_1;
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                                        ahb_busy        <= '1';
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                                else
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                                        HWDATA  <= HWDATA_int;                                  --send the data+go to next state, doesn't need to keep the address+other controls active
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                                        HADDR   <= x"00000000";
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                                        HTRANS  <= "00";
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                                        HWRITE  <= '0';
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                                        ahb_fsm_current_state   <= Write_FIC_2;
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                                        ahb_busy        <= '1';
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                                end if;
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                        when Write_FIC_2 =>
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                        --0x03
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                                if (HREADY = '0') then                                   --keep the data when slave is not ready yet
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                                        ahb_fsm_current_state   <= Write_FIC_2;
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                                        ahb_busy        <= '1';
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                                else
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                                        ahb_fsm_current_state   <= Idle;                --finish the write transfer  
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                                        ahb_busy        <= '0';
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                                end if;
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                        when Read_FIC_0 =>
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                        --0x04 store the address+control signals and apply to coreahblite
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                                HTRANS  <= "10";
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                                HSIZE   <= HSIZE_int;
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                                HWRITE  <= '0';
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                                ahb_fsm_current_state   <= Read_FIC_1;
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                                ahb_busy        <= '1';
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                        when Read_FIC_1 =>
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                        --0x05
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                                if (HREADY = '1') then                                  -- go to next state
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                                        ahb_fsm_current_state   <= Read_FIC_2;
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                                else
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                                        HTRANS  <= "10";                                            --keep the address+control signals when slave is not ready yet
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                                        HSIZE   <= HSIZE_int;
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                                        HWRITE  <= '0';
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                                        HADDR   <= HADDR_int;
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                                        ahb_fsm_current_state   <= Read_FIC_1;
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                                        ahb_busy        <= '1';
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                                end if;
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                        when Read_FIC_2 =>
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                        --0x06                         
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                                if (HREADY = '1') then                                  --read the data+finish the read transfer 
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                                        DATAOUT <= HRDATA;
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                                        ahb_fsm_current_state   <= Idle;
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                                        ahb_busy        <= '0';
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                                else
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                                        ahb_fsm_current_state   <= Read_FIC_2;  --waiting slave to be ready
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                                        ahb_busy        <= '1';
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                                end if;
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                                HADDR   <= x"00000000";                                 --doesn't need to keep the address+other controls any more
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                                HTRANS  <= "00";
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                        end case;
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                end if;
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        end process;
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end RTL;

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