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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAHBLite/] [5.3.101/] [rtl/] [vhdl/] [core/] [coreahblite_matrix4x16.vhd] - Blame information for rev 3

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1 3 uson 
-- ********************************************************************/
2 
-- Actel Corporation Proprietary and Confidential
3 
-- Copyright 2013 Actel Corporation.  All rights reserved.
4 
--
5 
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
6 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
7 
-- IN ADVANCE IN WRITING.
8 
--
9 
-- Description: CoreAHBLite matrix logic for
10 
--                              4 masters by 16 slaves,
11 
--                              instantiates the following modules:
12 
--                              COREAHBLITE_MASTERSTAGE, COREAHBLITE_SLAVESTAGE,
13 
--                              COREAHBLITE_INITCFG
14 
--
15 
--
16 
-- SVN Revision Information:
17 
-- SVN $Revision: 23120 $
18 
-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $
19 
--
20 
--
21 
-- *********************************************************************/
22 
library ieee;
23 
use ieee.std_logic_1164.all;
24 
use ieee.numeric_std.all;
25 
entity COREAHBLITE_MATRIX4X16 is
26 
    generic (
27 
        MEMSPACE          : integer range 0 to 6 := 0;
28 
        HADDR_SHG_CFG     : integer range 0 to 1 := 1;
29 
        SC                : integer range 0 to (2**16)-1:= 0;
30 
        M0_AHBSLOTENABLE  : integer range 0 to (2**17)-1:= (2**17)-1;
31 
        M1_AHBSLOTENABLE  : integer range 0 to (2**17)-1:= (2**17)-1;
32 
        M2_AHBSLOTENABLE  : integer range 0 to (2**17)-1:= (2**17)-1;
33 
        M3_AHBSLOTENABLE  : integer range 0 to (2**17)-1:= (2**17)-1;
34 
                SYNC_RESET       : integer := 0
35 
    );
36 
    port (
37 
        HCLK              : in std_logic;
38 
        HRESETN           : in std_logic;
39 
        REMAP_M0          : in std_logic;
40 
        HADDR_M0          : in std_logic_vector(31 downto 0);
41 
        HMASTLOCK_M0      : in std_logic;
42 
        HSIZE_M0          : in std_logic_vector(2 downto 0);
43 
        HTRANS_M0         : in std_logic;
44 
        HWRITE_M0         : in std_logic;
45 
        HWDATA_M0         : in std_logic_vector(31 downto 0);
46 
        HRESP_M0          : out std_logic;
47 
        HRDATA_M0         : out std_logic_vector(31 downto 0);
48 
        HREADY_M0         : out std_logic;
49 
        HADDR_M1          : in std_logic_vector(31 downto 0);
50 
        HMASTLOCK_M1      : in std_logic;
51 
        HSIZE_M1          : in std_logic_vector(2 downto 0);
52 
        HTRANS_M1         : in std_logic;
53 
        HWRITE_M1         : in std_logic;
54 
        HWDATA_M1         : in std_logic_vector(31 downto 0);
55 
        HRESP_M1          : out std_logic;
56 
        HRDATA_M1         : out std_logic_vector(31 downto 0);
57 
        HREADY_M1         : out std_logic;
58 
        HADDR_M2          : in std_logic_vector(31 downto 0);
59 
        HMASTLOCK_M2      : in std_logic;
60 
        HSIZE_M2          : in std_logic_vector(2 downto 0);
61 
        HTRANS_M2         : in std_logic;
62 
        HWRITE_M2         : in std_logic;
63 
        HWDATA_M2         : in std_logic_vector(31 downto 0);
64 
        HRESP_M2          : out std_logic;
65 
        HRDATA_M2         : out std_logic_vector(31 downto 0);
66 
        HREADY_M2         : out std_logic;
67 
        HADDR_M3          : in std_logic_vector(31 downto 0);
68 
        HMASTLOCK_M3      : in std_logic;
69 
        HSIZE_M3          : in std_logic_vector(2 downto 0);
70 
        HTRANS_M3         : in std_logic;
71 
        HWRITE_M3         : in std_logic;
72 
        HWDATA_M3         : in std_logic_vector(31 downto 0);
73 
        HRESP_M3          : out std_logic;
74 
        HRDATA_M3         : out std_logic_vector(31 downto 0);
75 
        HREADY_M3         : out std_logic;
76 
        HRDATA_S0         : in std_logic_vector(31 downto 0);
77 
        HREADYOUT_S0      : in std_logic;
78 
        HRESP_S0          : in std_logic;
79 
        HSEL_S0           : out std_logic;
80 
        HADDR_S0          : out std_logic_vector(31 downto 0);
81 
        HSIZE_S0          : out std_logic_vector(2 downto 0);
82 
        HTRANS_S0         : out std_logic;
83 
        HWRITE_S0         : out std_logic;
84 
        HWDATA_S0         : out std_logic_vector(31 downto 0);
85 
        HREADY_S0         : out std_logic;
86 
        HMASTLOCK_S0      : out std_logic;
87 
        HRDATA_S1         : in std_logic_vector(31 downto 0);
88 
        HREADYOUT_S1      : in std_logic;
89 
        HRESP_S1          : in std_logic;
90 
        HSEL_S1           : out std_logic;
91 
        HADDR_S1          : out std_logic_vector(31 downto 0);
92 
        HSIZE_S1          : out std_logic_vector(2 downto 0);
93 
        HTRANS_S1         : out std_logic;
94 
        HWRITE_S1         : out std_logic;
95 
        HWDATA_S1         : out std_logic_vector(31 downto 0);
96 
        HREADY_S1         : out std_logic;
97 
        HMASTLOCK_S1      : out std_logic;
98 
        HRDATA_S2         : in std_logic_vector(31 downto 0);
99 
        HREADYOUT_S2      : in std_logic;
100 
        HRESP_S2          : in std_logic;
101 
        HSEL_S2           : out std_logic;
102 
        HADDR_S2          : out std_logic_vector(31 downto 0);
103 
        HSIZE_S2          : out std_logic_vector(2 downto 0);
104 
        HTRANS_S2         : out std_logic;
105 
        HWRITE_S2         : out std_logic;
106 
        HWDATA_S2         : out std_logic_vector(31 downto 0);
107 
        HREADY_S2         : out std_logic;
108 
        HMASTLOCK_S2      : out std_logic;
109 
        HRDATA_S3         : in std_logic_vector(31 downto 0);
110 
        HREADYOUT_S3      : in std_logic;
111 
        HRESP_S3          : in std_logic;
112 
        HSEL_S3           : out std_logic;
113 
        HADDR_S3          : out std_logic_vector(31 downto 0);
114 
        HSIZE_S3          : out std_logic_vector(2 downto 0);
115 
        HTRANS_S3         : out std_logic;
116 
        HWRITE_S3         : out std_logic;
117 
        HWDATA_S3         : out std_logic_vector(31 downto 0);
118 
        HREADY_S3         : out std_logic;
119 
        HMASTLOCK_S3      : out std_logic;
120 
        HRDATA_S4         : in std_logic_vector(31 downto 0);
121 
        HREADYOUT_S4      : in std_logic;
122 
        HRESP_S4          : in std_logic;
123 
        HSEL_S4           : out std_logic;
124 
        HADDR_S4          : out std_logic_vector(31 downto 0);
125 
        HSIZE_S4          : out std_logic_vector(2 downto 0);
126 
        HTRANS_S4         : out std_logic;
127 
        HWRITE_S4         : out std_logic;
128 
        HWDATA_S4         : out std_logic_vector(31 downto 0);
129 
        HREADY_S4         : out std_logic;
130 
        HMASTLOCK_S4      : out std_logic;
131 
        HRDATA_S5         : in std_logic_vector(31 downto 0);
132 
        HREADYOUT_S5      : in std_logic;
133 
        HRESP_S5          : in std_logic;
134 
        HSEL_S5           : out std_logic;
135 
        HADDR_S5          : out std_logic_vector(31 downto 0);
136 
        HSIZE_S5          : out std_logic_vector(2 downto 0);
137 
        HTRANS_S5         : out std_logic;
138 
        HWRITE_S5         : out std_logic;
139 
        HWDATA_S5         : out std_logic_vector(31 downto 0);
140 
        HREADY_S5         : out std_logic;
141 
        HMASTLOCK_S5      : out std_logic;
142 
        HRDATA_S6         : in std_logic_vector(31 downto 0);
143 
        HREADYOUT_S6      : in std_logic;
144 
        HRESP_S6          : in std_logic;
145 
        HSEL_S6           : out std_logic;
146 
        HADDR_S6          : out std_logic_vector(31 downto 0);
147 
        HSIZE_S6          : out std_logic_vector(2 downto 0);
148 
        HTRANS_S6         : out std_logic;
149 
        HWRITE_S6         : out std_logic;
150 
        HWDATA_S6         : out std_logic_vector(31 downto 0);
151 
        HREADY_S6         : out std_logic;
152 
        HMASTLOCK_S6      : out std_logic;
153 
        HRDATA_S7         : in std_logic_vector(31 downto 0);
154 
        HREADYOUT_S7      : in std_logic;
155 
        HRESP_S7          : in std_logic;
156 
        HSEL_S7           : out std_logic;
157 
        HADDR_S7          : out std_logic_vector(31 downto 0);
158 
        HSIZE_S7          : out std_logic_vector(2 downto 0);
159 
        HTRANS_S7         : out std_logic;
160 
        HWRITE_S7         : out std_logic;
161 
        HWDATA_S7         : out std_logic_vector(31 downto 0);
162 
        HREADY_S7         : out std_logic;
163 
        HMASTLOCK_S7      : out std_logic;
164 
        HRDATA_S8         : in std_logic_vector(31 downto 0);
165 
        HREADYOUT_S8      : in std_logic;
166 
        HRESP_S8          : in std_logic;
167 
        HSEL_S8           : out std_logic;
168 
        HADDR_S8          : out std_logic_vector(31 downto 0);
169 
        HSIZE_S8          : out std_logic_vector(2 downto 0);
170 
        HTRANS_S8         : out std_logic;
171 
        HWRITE_S8         : out std_logic;
172 
        HWDATA_S8         : out std_logic_vector(31 downto 0);
173 
        HREADY_S8         : out std_logic;
174 
        HMASTLOCK_S8      : out std_logic;
175 
        HRDATA_S9         : in std_logic_vector(31 downto 0);
176 
        HREADYOUT_S9      : in std_logic;
177 
        HRESP_S9          : in std_logic;
178 
        HSEL_S9           : out std_logic;
179 
        HADDR_S9          : out std_logic_vector(31 downto 0);
180 
        HSIZE_S9          : out std_logic_vector(2 downto 0);
181 
        HTRANS_S9         : out std_logic;
182 
        HWRITE_S9         : out std_logic;
183 
        HWDATA_S9         : out std_logic_vector(31 downto 0);
184 
        HREADY_S9         : out std_logic;
185 
        HMASTLOCK_S9      : out std_logic;
186 
        HRDATA_S10        : in std_logic_vector(31 downto 0);
187 
        HREADYOUT_S10     : in std_logic;
188 
        HRESP_S10         : in std_logic;
189 
        HSEL_S10          : out std_logic;
190 
        HADDR_S10         : out std_logic_vector(31 downto 0);
191 
        HSIZE_S10         : out std_logic_vector(2 downto 0);
192 
        HTRANS_S10        : out std_logic;
193 
        HWRITE_S10        : out std_logic;
194 
        HWDATA_S10        : out std_logic_vector(31 downto 0);
195 
        HREADY_S10        : out std_logic;
196 
        HMASTLOCK_S10     : out std_logic;
197 
        HRDATA_S11        : in std_logic_vector(31 downto 0);
198 
        HREADYOUT_S11     : in std_logic;
199 
        HRESP_S11         : in std_logic;
200 
        HSEL_S11          : out std_logic;
201 
        HADDR_S11         : out std_logic_vector(31 downto 0);
202 
        HSIZE_S11         : out std_logic_vector(2 downto 0);
203 
        HTRANS_S11        : out std_logic;
204 
        HWRITE_S11        : out std_logic;
205 
        HWDATA_S11        : out std_logic_vector(31 downto 0);
206 
        HREADY_S11        : out std_logic;
207 
        HMASTLOCK_S11     : out std_logic;
208 
        HRDATA_S12        : in std_logic_vector(31 downto 0);
209 
        HREADYOUT_S12     : in std_logic;
210 
        HRESP_S12         : in std_logic;
211 
        HSEL_S12          : out std_logic;
212 
        HADDR_S12         : out std_logic_vector(31 downto 0);
213 
        HSIZE_S12         : out std_logic_vector(2 downto 0);
214 
        HTRANS_S12        : out std_logic;
215 
        HWRITE_S12        : out std_logic;
216 
        HWDATA_S12        : out std_logic_vector(31 downto 0);
217 
        HREADY_S12        : out std_logic;
218 
        HMASTLOCK_S12     : out std_logic;
219 
        HRDATA_S13        : in std_logic_vector(31 downto 0);
220 
        HREADYOUT_S13     : in std_logic;
221 
        HRESP_S13         : in std_logic;
222 
        HSEL_S13          : out std_logic;
223 
        HADDR_S13         : out std_logic_vector(31 downto 0);
224 
        HSIZE_S13         : out std_logic_vector(2 downto 0);
225 
        HTRANS_S13        : out std_logic;
226 
        HWRITE_S13        : out std_logic;
227 
        HWDATA_S13        : out std_logic_vector(31 downto 0);
228 
        HREADY_S13        : out std_logic;
229 
        HMASTLOCK_S13     : out std_logic;
230 
        HRDATA_S14        : in std_logic_vector(31 downto 0);
231 
        HREADYOUT_S14     : in std_logic;
232 
        HRESP_S14         : in std_logic;
233 
        HSEL_S14          : out std_logic;
234 
        HADDR_S14         : out std_logic_vector(31 downto 0);
235 
        HSIZE_S14         : out std_logic_vector(2 downto 0);
236 
        HTRANS_S14        : out std_logic;
237 
        HWRITE_S14        : out std_logic;
238 
        HWDATA_S14        : out std_logic_vector(31 downto 0);
239 
        HREADY_S14        : out std_logic;
240 
        HMASTLOCK_S14     : out std_logic;
241 
        HRDATA_S15        : in std_logic_vector(31 downto 0);
242 
        HREADYOUT_S15     : in std_logic;
243 
        HRESP_S15         : in std_logic;
244 
        HSEL_S15          : out std_logic;
245 
        HADDR_S15         : out std_logic_vector(31 downto 0);
246 
        HSIZE_S15         : out std_logic_vector(2 downto 0);
247 
        HTRANS_S15        : out std_logic;
248 
        HWRITE_S15        : out std_logic;
249 
        HWDATA_S15        : out std_logic_vector(31 downto 0);
250 
        HREADY_S15        : out std_logic;
251 
        HMASTLOCK_S15     : out std_logic;
252 
        HRDATA_S16        : in std_logic_vector(31 downto 0);
253 
        HREADYOUT_S16     : in std_logic;
254 
        HRESP_S16         : in std_logic;
255 
        HSEL_S16          : out std_logic;
256 
        HADDR_S16         : out std_logic_vector(31 downto 0);
257 
        HSIZE_S16         : out std_logic_vector(2 downto 0);
258 
        HTRANS_S16        : out std_logic;
259 
        HWRITE_S16        : out std_logic;
260 
        HWDATA_S16        : out std_logic_vector(31 downto 0);
261 
        HREADY_S16        : out std_logic;
262 
        HMASTLOCK_S16     : out std_logic
263 
    );
264 
end entity COREAHBLITE_MATRIX4X16;
265 
 
266 
architecture COREAHBLITE_MATRIX4X16_arch of COREAHBLITE_MATRIX4X16 is
267 
 
268 
constant M0_AHBSLOTENABLE_slv  : std_logic_vector(16 downto 0):=
269 
        std_logic_vector(to_unsigned(M0_AHBSLOTENABLE,17));
270 
constant M1_AHBSLOTENABLE_slv  : std_logic_vector(16 downto 0):=
271 
        std_logic_vector(to_unsigned(M1_AHBSLOTENABLE,17));
272 
constant M2_AHBSLOTENABLE_slv  : std_logic_vector(16 downto 0):=
273 
        std_logic_vector(to_unsigned(M2_AHBSLOTENABLE,17));
274 
constant M3_AHBSLOTENABLE_slv  : std_logic_vector(16 downto 0):=
275 
        std_logic_vector(to_unsigned(M3_AHBSLOTENABLE,17));
276 
constant SC_slv  : std_logic_vector(15 downto 0):=
277 
    std_logic_vector(to_unsigned(SC,16));
278 
 
279 
    component COREAHBLITE_MASTERSTAGE is
280 
        generic (
281 
            MEMSPACE            : integer range 0 to 6 := 0;
282 
            HADDR_SHG_CFG       : integer range 0 to 1 := 0;
283 
            SC                  : integer range 0 to (2**16)-1 := 0;
284 
            M_AHBSLOTENABLE     : integer range 0 to (2**17)-1 := (2**17)-1;
285 
                        SYNC_RESET          : integer := 0
286 
        );
287 
        port (
288 
            HCLK              : in std_logic;
289 
            HRESETN           : in std_logic;
290 
            HADDR             : in std_logic_vector(31 downto 0);
291 
            HMASTLOCK         : in std_logic;
292 
            HSIZE             : in std_logic_vector(2 downto 0);
293 
            HTRANS            : in std_logic;
294 
            HWRITE            : in std_logic;
295 
            HRESP             : out std_logic;
296 
            HRDATA            : out std_logic_vector(31 downto 0);
297 
            HREADY_M          : out std_logic;
298 
            REMAP             : in std_logic;
299 
            SADDRREADY        : in std_logic_vector(16 downto 0);
300 
            SDATAREADY        : in std_logic_vector(16 downto 0);
301 
            SHRESP            : in std_logic_vector(16 downto 0);
302 
            GATEDHADDR        : out std_logic_vector(31 downto 0);
303 
            GATEDHMASTLOCK    : out std_logic;
304 
            GATEDHSIZE        : out std_logic_vector(2 downto 0);
305 
            GATEDHTRANS       : out std_logic;
306 
            GATEDHWRITE       : out std_logic;
307 
            SADDRSEL          : out std_logic_vector(16 downto 0);
308 
            SDATASEL          : out std_logic_vector(16 downto 0);
309 
            PREVDATASLAVEREADY : out std_logic;
310 
            HRDATA_S0         : in std_logic_vector(31 downto 0);
311 
            HREADYOUT_S0      : in std_logic;
312 
            HRDATA_S1         : in std_logic_vector(31 downto 0);
313 
            HREADYOUT_S1      : in std_logic;
314 
            HRDATA_S2         : in std_logic_vector(31 downto 0);
315 
            HREADYOUT_S2      : in std_logic;
316 
            HRDATA_S3         : in std_logic_vector(31 downto 0);
317 
            HREADYOUT_S3      : in std_logic;
318 
            HRDATA_S4         : in std_logic_vector(31 downto 0);
319 
            HREADYOUT_S4      : in std_logic;
320 
            HRDATA_S5         : in std_logic_vector(31 downto 0);
321 
            HREADYOUT_S5      : in std_logic;
322 
            HRDATA_S6         : in std_logic_vector(31 downto 0);
323 
            HREADYOUT_S6      : in std_logic;
324 
            HRDATA_S7         : in std_logic_vector(31 downto 0);
325 
            HREADYOUT_S7      : in std_logic;
326 
            HRDATA_S8         : in std_logic_vector(31 downto 0);
327 
            HREADYOUT_S8      : in std_logic;
328 
            HRDATA_S9         : in std_logic_vector(31 downto 0);
329 
            HREADYOUT_S9      : in std_logic;
330 
            HRDATA_S10        : in std_logic_vector(31 downto 0);
331 
            HREADYOUT_S10     : in std_logic;
332 
            HRDATA_S11        : in std_logic_vector(31 downto 0);
333 
            HREADYOUT_S11     : in std_logic;
334 
            HRDATA_S12        : in std_logic_vector(31 downto 0);
335 
            HREADYOUT_S12     : in std_logic;
336 
            HRDATA_S13        : in std_logic_vector(31 downto 0);
337 
            HREADYOUT_S13     : in std_logic;
338 
            HRDATA_S14        : in std_logic_vector(31 downto 0);
339 
            HREADYOUT_S14     : in std_logic;
340 
            HRDATA_S15        : in std_logic_vector(31 downto 0);
341 
            HREADYOUT_S15     : in std_logic;
342 
            HRDATA_S16        : in std_logic_vector(31 downto 0);
343 
            HREADYOUT_S16     : in std_logic
344 
        );
345 
    end component;
346 
 
347 
    component COREAHBLITE_SLAVESTAGE is
348 
            generic(SYNC_RESET      : integer := 0);
349 
        port (
350 
            HCLK              : in std_logic;
351 
            HRESETN           : in std_logic;
352 
            HREADYOUT         : in std_logic;
353 
            HRESP             : in std_logic;
354 
            HSEL              : out std_logic;
355 
            HADDR             : out std_logic_vector(31 downto 0);
356 
            HSIZE             : out std_logic_vector(2 downto 0);
357 
            HTRANS            : out std_logic;
358 
            HWRITE            : out std_logic;
359 
            HWDATA            : out std_logic_vector(31 downto 0);
360 
            HREADY_S          : out std_logic;
361 
            HMASTLOCK         : out std_logic;
362 
            MADDRSEL          : in std_logic_vector(3 downto 0);
363 
            MDATASEL          : in std_logic_vector(3 downto 0);
364 
            MPREVDATASLAVEREADY : in std_logic_vector(3 downto 0);
365 
            MADDRREADY        : out std_logic_vector(3 downto 0);
366 
            MDATAREADY        : out std_logic_vector(3 downto 0);
367 
            MHRESP            : out std_logic_vector(3 downto 0);
368 
            M0GATEDHADDR      : in std_logic_vector(31 downto 0);
369 
            M0GATEDHMASTLOCK  : in std_logic;
370 
            M0GATEDHSIZE      : in std_logic_vector(2 downto 0);
371 
            M0GATEDHTRANS     : in std_logic;
372 
            M0GATEDHWRITE     : in std_logic;
373 
            M1GATEDHADDR      : in std_logic_vector(31 downto 0);
374 
            M1GATEDHMASTLOCK  : in std_logic;
375 
            M1GATEDHSIZE      : in std_logic_vector(2 downto 0);
376 
            M1GATEDHTRANS     : in std_logic;
377 
            M1GATEDHWRITE     : in std_logic;
378 
            M2GATEDHADDR      : in std_logic_vector(31 downto 0);
379 
            M2GATEDHMASTLOCK  : in std_logic;
380 
            M2GATEDHSIZE      : in std_logic_vector(2 downto 0);
381 
            M2GATEDHTRANS     : in std_logic;
382 
            M2GATEDHWRITE     : in std_logic;
383 
            M3GATEDHADDR      : in std_logic_vector(31 downto 0);
384 
            M3GATEDHMASTLOCK  : in std_logic;
385 
            M3GATEDHSIZE      : in std_logic_vector(2 downto 0);
386 
            M3GATEDHTRANS     : in std_logic;
387 
            M3GATEDHWRITE     : in std_logic;
388 
            HWDATA_M0         : in std_logic_vector(31 downto 0);
389 
            HWDATA_M1         : in std_logic_vector(31 downto 0);
390 
            HWDATA_M2         : in std_logic_vector(31 downto 0);
391 
            HWDATA_M3         : in std_logic_vector(31 downto 0)
392 
        );
393 
    end component;
394 
 
395 
    signal M0GATEDHADDR            : std_logic_vector(31 downto 0);
396 
    signal M0GATEDHMASTLOCK        : std_logic;
397 
    signal M0GATEDHSIZE            : std_logic_vector(2 downto 0);
398 
    signal M0GATEDHTRANS           : std_logic;
399 
    signal M0GATEDHWRITE           : std_logic;
400 
    signal m0PrevDataSlaveReady    : std_logic;
401 
    signal m0s0AddrSel             : std_logic;
402 
    signal m0s0DataSel             : std_logic;
403 
    signal s0m0AddrReady           : std_logic;
404 
    signal s0m0DataReady           : std_logic;
405 
    signal s0m0HResp               : std_logic;
406 
    signal m0s0AddrSel_int         : std_logic;
407 
    signal m0s0DataSel_int         : std_logic;
408 
    signal s0m0AddrReady_int       : std_logic;
409 
    signal s0m0DataReady_int       : std_logic;
410 
    signal s0m0HResp_int           : std_logic;
411 
    signal m0s1AddrSel             : std_logic;
412 
    signal m0s1DataSel             : std_logic;
413 
    signal s1m0AddrReady           : std_logic;
414 
    signal s1m0DataReady           : std_logic;
415 
    signal s1m0HResp               : std_logic;
416 
    signal m0s1AddrSel_int         : std_logic;
417 
    signal m0s1DataSel_int         : std_logic;
418 
    signal s1m0AddrReady_int       : std_logic;
419 
    signal s1m0DataReady_int       : std_logic;
420 
    signal s1m0HResp_int           : std_logic;
421 
    signal m0s2AddrSel             : std_logic;
422 
    signal m0s2DataSel             : std_logic;
423 
    signal s2m0AddrReady           : std_logic;
424 
    signal s2m0DataReady           : std_logic;
425 
    signal s2m0HResp               : std_logic;
426 
    signal m0s2AddrSel_int         : std_logic;
427 
    signal m0s2DataSel_int         : std_logic;
428 
    signal s2m0AddrReady_int       : std_logic;
429 
    signal s2m0DataReady_int       : std_logic;
430 
    signal s2m0HResp_int           : std_logic;
431 
    signal m0s3AddrSel             : std_logic;
432 
    signal m0s3DataSel             : std_logic;
433 
    signal s3m0AddrReady           : std_logic;
434 
    signal s3m0DataReady           : std_logic;
435 
    signal s3m0HResp               : std_logic;
436 
    signal m0s3AddrSel_int         : std_logic;
437 
    signal m0s3DataSel_int         : std_logic;
438 
    signal s3m0AddrReady_int       : std_logic;
439 
    signal s3m0DataReady_int       : std_logic;
440 
    signal s3m0HResp_int           : std_logic;
441 
    signal m0s4AddrSel             : std_logic;
442 
    signal m0s4DataSel             : std_logic;
443 
    signal s4m0AddrReady           : std_logic;
444 
    signal s4m0DataReady           : std_logic;
445 
    signal s4m0HResp               : std_logic;
446 
    signal m0s4AddrSel_int         : std_logic;
447 
    signal m0s4DataSel_int         : std_logic;
448 
    signal s4m0AddrReady_int       : std_logic;
449 
    signal s4m0DataReady_int       : std_logic;
450 
    signal s4m0HResp_int           : std_logic;
451 
    signal m0s5AddrSel             : std_logic;
452 
    signal m0s5DataSel             : std_logic;
453 
    signal s5m0AddrReady           : std_logic;
454 
    signal s5m0DataReady           : std_logic;
455 
    signal s5m0HResp               : std_logic;
456 
    signal m0s5AddrSel_int         : std_logic;
457 
    signal m0s5DataSel_int         : std_logic;
458 
    signal s5m0AddrReady_int       : std_logic;
459 
    signal s5m0DataReady_int       : std_logic;
460 
    signal s5m0HResp_int           : std_logic;
461 
    signal m0s6AddrSel             : std_logic;
462 
    signal m0s6DataSel             : std_logic;
463 
    signal s6m0AddrReady           : std_logic;
464 
    signal s6m0DataReady           : std_logic;
465 
    signal s6m0HResp               : std_logic;
466 
    signal m0s6AddrSel_int         : std_logic;
467 
    signal m0s6DataSel_int         : std_logic;
468 
    signal s6m0AddrReady_int       : std_logic;
469 
    signal s6m0DataReady_int       : std_logic;
470 
    signal s6m0HResp_int           : std_logic;
471 
    signal m0s7AddrSel             : std_logic;
472 
    signal m0s7DataSel             : std_logic;
473 
    signal s7m0AddrReady           : std_logic;
474 
    signal s7m0DataReady           : std_logic;
475 
    signal s7m0HResp               : std_logic;
476 
    signal m0s7AddrSel_int         : std_logic;
477 
    signal m0s7DataSel_int         : std_logic;
478 
    signal s7m0AddrReady_int       : std_logic;
479 
    signal s7m0DataReady_int       : std_logic;
480 
    signal s7m0HResp_int           : std_logic;
481 
    signal m0s8AddrSel             : std_logic;
482 
    signal m0s8DataSel             : std_logic;
483 
    signal s8m0AddrReady           : std_logic;
484 
    signal s8m0DataReady           : std_logic;
485 
    signal s8m0HResp               : std_logic;
486 
    signal m0s8AddrSel_int         : std_logic;
487 
    signal m0s8DataSel_int         : std_logic;
488 
    signal s8m0AddrReady_int       : std_logic;
489 
    signal s8m0DataReady_int       : std_logic;
490 
    signal s8m0HResp_int           : std_logic;
491 
    signal m0s9AddrSel             : std_logic;
492 
    signal m0s9DataSel             : std_logic;
493 
    signal s9m0AddrReady           : std_logic;
494 
    signal s9m0DataReady           : std_logic;
495 
    signal s9m0HResp               : std_logic;
496 
    signal m0s9AddrSel_int         : std_logic;
497 
    signal m0s9DataSel_int         : std_logic;
498 
    signal s9m0AddrReady_int       : std_logic;
499 
    signal s9m0DataReady_int       : std_logic;
500 
    signal s9m0HResp_int           : std_logic;
501 
    signal m0s10AddrSel            : std_logic;
502 
    signal m0s10DataSel            : std_logic;
503 
    signal s10m0AddrReady          : std_logic;
504 
    signal s10m0DataReady          : std_logic;
505 
    signal s10m0HResp              : std_logic;
506 
    signal m0s10AddrSel_int        : std_logic;
507 
    signal m0s10DataSel_int        : std_logic;
508 
    signal s10m0AddrReady_int      : std_logic;
509 
    signal s10m0DataReady_int      : std_logic;
510 
    signal s10m0HResp_int          : std_logic;
511 
    signal m0s11AddrSel            : std_logic;
512 
    signal m0s11DataSel            : std_logic;
513 
    signal s11m0AddrReady          : std_logic;
514 
    signal s11m0DataReady          : std_logic;
515 
    signal s11m0HResp              : std_logic;
516 
    signal m0s11AddrSel_int        : std_logic;
517 
    signal m0s11DataSel_int        : std_logic;
518 
    signal s11m0AddrReady_int      : std_logic;
519 
    signal s11m0DataReady_int      : std_logic;
520 
    signal s11m0HResp_int          : std_logic;
521 
    signal m0s12AddrSel            : std_logic;
522 
    signal m0s12DataSel            : std_logic;
523 
    signal s12m0AddrReady          : std_logic;
524 
    signal s12m0DataReady          : std_logic;
525 
    signal s12m0HResp              : std_logic;
526 
    signal m0s12AddrSel_int        : std_logic;
527 
    signal m0s12DataSel_int        : std_logic;
528 
    signal s12m0AddrReady_int      : std_logic;
529 
    signal s12m0DataReady_int      : std_logic;
530 
    signal s12m0HResp_int          : std_logic;
531 
    signal m0s13AddrSel            : std_logic;
532 
    signal m0s13DataSel            : std_logic;
533 
    signal s13m0AddrReady          : std_logic;
534 
    signal s13m0DataReady          : std_logic;
535 
    signal s13m0HResp              : std_logic;
536 
    signal m0s13AddrSel_int        : std_logic;
537 
    signal m0s13DataSel_int        : std_logic;
538 
    signal s13m0AddrReady_int      : std_logic;
539 
    signal s13m0DataReady_int      : std_logic;
540 
    signal s13m0HResp_int          : std_logic;
541 
    signal m0s14AddrSel            : std_logic;
542 
    signal m0s14DataSel            : std_logic;
543 
    signal s14m0AddrReady          : std_logic;
544 
    signal s14m0DataReady          : std_logic;
545 
    signal s14m0HResp              : std_logic;
546 
    signal m0s14AddrSel_int        : std_logic;
547 
    signal m0s14DataSel_int        : std_logic;
548 
    signal s14m0AddrReady_int      : std_logic;
549 
    signal s14m0DataReady_int      : std_logic;
550 
    signal s14m0HResp_int          : std_logic;
551 
    signal m0s15AddrSel            : std_logic;
552 
    signal m0s15DataSel            : std_logic;
553 
    signal s15m0AddrReady          : std_logic;
554 
    signal s15m0DataReady          : std_logic;
555 
    signal s15m0HResp              : std_logic;
556 
    signal m0s15AddrSel_int        : std_logic;
557 
    signal m0s15DataSel_int        : std_logic;
558 
    signal s15m0AddrReady_int      : std_logic;
559 
    signal s15m0DataReady_int      : std_logic;
560 
    signal s15m0HResp_int          : std_logic;
561 
    signal m0s16AddrSel            : std_logic;
562 
    signal m0s16DataSel            : std_logic;
563 
    signal s16m0AddrReady          : std_logic;
564 
    signal s16m0DataReady          : std_logic;
565 
    signal s16m0HResp              : std_logic;
566 
    signal m0s16AddrSel_int        : std_logic;
567 
    signal m0s16DataSel_int        : std_logic;
568 
    signal s16m0AddrReady_int      : std_logic;
569 
    signal s16m0DataReady_int      : std_logic;
570 
    signal s16m0HResp_int          : std_logic;
571 
    signal M1GATEDHADDR            : std_logic_vector(31 downto 0);
572 
    signal M1GATEDHMASTLOCK        : std_logic;
573 
    signal M1GATEDHSIZE            : std_logic_vector(2 downto 0);
574 
    signal M1GATEDHTRANS           : std_logic;
575 
    signal M1GATEDHWRITE           : std_logic;
576 
    signal m1PrevDataSlaveReady    : std_logic;
577 
    signal m1s0AddrSel             : std_logic;
578 
    signal m1s0DataSel             : std_logic;
579 
    signal s0m1AddrReady           : std_logic;
580 
    signal s0m1DataReady           : std_logic;
581 
    signal s0m1HResp               : std_logic;
582 
    signal m1s0AddrSel_int         : std_logic;
583 
    signal m1s0DataSel_int         : std_logic;
584 
    signal s0m1AddrReady_int       : std_logic;
585 
    signal s0m1DataReady_int       : std_logic;
586 
    signal s0m1HResp_int           : std_logic;
587 
    signal m1s1AddrSel             : std_logic;
588 
    signal m1s1DataSel             : std_logic;
589 
    signal s1m1AddrReady           : std_logic;
590 
    signal s1m1DataReady           : std_logic;
591 
    signal s1m1HResp               : std_logic;
592 
    signal m1s1AddrSel_int         : std_logic;
593 
    signal m1s1DataSel_int         : std_logic;
594 
    signal s1m1AddrReady_int       : std_logic;
595 
    signal s1m1DataReady_int       : std_logic;
596 
    signal s1m1HResp_int           : std_logic;
597 
    signal m1s2AddrSel             : std_logic;
598 
    signal m1s2DataSel             : std_logic;
599 
    signal s2m1AddrReady           : std_logic;
600 
    signal s2m1DataReady           : std_logic;
601 
    signal s2m1HResp               : std_logic;
602 
    signal m1s2AddrSel_int         : std_logic;
603 
    signal m1s2DataSel_int         : std_logic;
604 
    signal s2m1AddrReady_int       : std_logic;
605 
    signal s2m1DataReady_int       : std_logic;
606 
    signal s2m1HResp_int           : std_logic;
607 
    signal m1s3AddrSel             : std_logic;
608 
    signal m1s3DataSel             : std_logic;
609 
    signal s3m1AddrReady           : std_logic;
610 
    signal s3m1DataReady           : std_logic;
611 
    signal s3m1HResp               : std_logic;
612 
    signal m1s3AddrSel_int         : std_logic;
613 
    signal m1s3DataSel_int         : std_logic;
614 
    signal s3m1AddrReady_int       : std_logic;
615 
    signal s3m1DataReady_int       : std_logic;
616 
    signal s3m1HResp_int           : std_logic;
617 
    signal m1s4AddrSel             : std_logic;
618 
    signal m1s4DataSel             : std_logic;
619 
    signal s4m1AddrReady           : std_logic;
620 
    signal s4m1DataReady           : std_logic;
621 
    signal s4m1HResp               : std_logic;
622 
    signal m1s4AddrSel_int         : std_logic;
623 
    signal m1s4DataSel_int         : std_logic;
624 
    signal s4m1AddrReady_int       : std_logic;
625 
    signal s4m1DataReady_int       : std_logic;
626 
    signal s4m1HResp_int           : std_logic;
627 
    signal m1s5AddrSel             : std_logic;
628 
    signal m1s5DataSel             : std_logic;
629 
    signal s5m1AddrReady           : std_logic;
630 
    signal s5m1DataReady           : std_logic;
631 
    signal s5m1HResp               : std_logic;
632 
    signal m1s5AddrSel_int         : std_logic;
633 
    signal m1s5DataSel_int         : std_logic;
634 
    signal s5m1AddrReady_int       : std_logic;
635 
    signal s5m1DataReady_int       : std_logic;
636 
    signal s5m1HResp_int           : std_logic;
637 
    signal m1s6AddrSel             : std_logic;
638 
    signal m1s6DataSel             : std_logic;
639 
    signal s6m1AddrReady           : std_logic;
640 
    signal s6m1DataReady           : std_logic;
641 
    signal s6m1HResp               : std_logic;
642 
    signal m1s6AddrSel_int         : std_logic;
643 
    signal m1s6DataSel_int         : std_logic;
644 
    signal s6m1AddrReady_int       : std_logic;
645 
    signal s6m1DataReady_int       : std_logic;
646 
    signal s6m1HResp_int           : std_logic;
647 
    signal m1s7AddrSel             : std_logic;
648 
    signal m1s7DataSel             : std_logic;
649 
    signal s7m1AddrReady           : std_logic;
650 
    signal s7m1DataReady           : std_logic;
651 
    signal s7m1HResp               : std_logic;
652 
    signal m1s7AddrSel_int         : std_logic;
653 
    signal m1s7DataSel_int         : std_logic;
654 
    signal s7m1AddrReady_int       : std_logic;
655 
    signal s7m1DataReady_int       : std_logic;
656 
    signal s7m1HResp_int           : std_logic;
657 
    signal m1s8AddrSel             : std_logic;
658 
    signal m1s8DataSel             : std_logic;
659 
    signal s8m1AddrReady           : std_logic;
660 
    signal s8m1DataReady           : std_logic;
661 
    signal s8m1HResp               : std_logic;
662 
    signal m1s8AddrSel_int         : std_logic;
663 
    signal m1s8DataSel_int         : std_logic;
664 
    signal s8m1AddrReady_int       : std_logic;
665 
    signal s8m1DataReady_int       : std_logic;
666 
    signal s8m1HResp_int           : std_logic;
667 
    signal m1s9AddrSel             : std_logic;
668 
    signal m1s9DataSel             : std_logic;
669 
    signal s9m1AddrReady           : std_logic;
670 
    signal s9m1DataReady           : std_logic;
671 
    signal s9m1HResp               : std_logic;
672 
    signal m1s9AddrSel_int         : std_logic;
673 
    signal m1s9DataSel_int         : std_logic;
674 
    signal s9m1AddrReady_int       : std_logic;
675 
    signal s9m1DataReady_int       : std_logic;
676 
    signal s9m1HResp_int           : std_logic;
677 
    signal m1s10AddrSel            : std_logic;
678 
    signal m1s10DataSel            : std_logic;
679 
    signal s10m1AddrReady          : std_logic;
680 
    signal s10m1DataReady          : std_logic;
681 
    signal s10m1HResp              : std_logic;
682 
    signal m1s10AddrSel_int        : std_logic;
683 
    signal m1s10DataSel_int        : std_logic;
684 
    signal s10m1AddrReady_int      : std_logic;
685 
    signal s10m1DataReady_int      : std_logic;
686 
    signal s10m1HResp_int          : std_logic;
687 
    signal m1s11AddrSel            : std_logic;
688 
    signal m1s11DataSel            : std_logic;
689 
    signal s11m1AddrReady          : std_logic;
690 
    signal s11m1DataReady          : std_logic;
691 
    signal s11m1HResp              : std_logic;
692 
    signal m1s11AddrSel_int        : std_logic;
693 
    signal m1s11DataSel_int        : std_logic;
694 
    signal s11m1AddrReady_int      : std_logic;
695 
    signal s11m1DataReady_int      : std_logic;
696 
    signal s11m1HResp_int          : std_logic;
697 
    signal m1s12AddrSel            : std_logic;
698 
    signal m1s12DataSel            : std_logic;
699 
    signal s12m1AddrReady          : std_logic;
700 
    signal s12m1DataReady          : std_logic;
701 
    signal s12m1HResp              : std_logic;
702 
    signal m1s12AddrSel_int        : std_logic;
703 
    signal m1s12DataSel_int        : std_logic;
704 
    signal s12m1AddrReady_int      : std_logic;
705 
    signal s12m1DataReady_int      : std_logic;
706 
    signal s12m1HResp_int          : std_logic;
707 
    signal m1s13AddrSel            : std_logic;
708 
    signal m1s13DataSel            : std_logic;
709 
    signal s13m1AddrReady          : std_logic;
710 
    signal s13m1DataReady          : std_logic;
711 
    signal s13m1HResp              : std_logic;
712 
    signal m1s13AddrSel_int        : std_logic;
713 
    signal m1s13DataSel_int        : std_logic;
714 
    signal s13m1AddrReady_int      : std_logic;
715 
    signal s13m1DataReady_int      : std_logic;
716 
    signal s13m1HResp_int          : std_logic;
717 
    signal m1s14AddrSel            : std_logic;
718 
    signal m1s14DataSel            : std_logic;
719 
    signal s14m1AddrReady          : std_logic;
720 
    signal s14m1DataReady          : std_logic;
721 
    signal s14m1HResp              : std_logic;
722 
    signal m1s14AddrSel_int        : std_logic;
723 
    signal m1s14DataSel_int        : std_logic;
724 
    signal s14m1AddrReady_int      : std_logic;
725 
    signal s14m1DataReady_int      : std_logic;
726 
    signal s14m1HResp_int          : std_logic;
727 
    signal m1s15AddrSel            : std_logic;
728 
    signal m1s15DataSel            : std_logic;
729 
    signal s15m1AddrReady          : std_logic;
730 
    signal s15m1DataReady          : std_logic;
731 
    signal s15m1HResp              : std_logic;
732 
    signal m1s15AddrSel_int        : std_logic;
733 
    signal m1s15DataSel_int        : std_logic;
734 
    signal s15m1AddrReady_int      : std_logic;
735 
    signal s15m1DataReady_int      : std_logic;
736 
    signal s15m1HResp_int          : std_logic;
737 
    signal m1s16AddrSel            : std_logic;
738 
    signal m1s16DataSel            : std_logic;
739 
    signal s16m1AddrReady          : std_logic;
740 
    signal s16m1DataReady          : std_logic;
741 
    signal s16m1HResp              : std_logic;
742 
    signal m1s16AddrSel_int        : std_logic;
743 
    signal m1s16DataSel_int        : std_logic;
744 
    signal s16m1AddrReady_int      : std_logic;
745 
    signal s16m1DataReady_int      : std_logic;
746 
    signal s16m1HResp_int          : std_logic;
747 
    signal M2GATEDHADDR            : std_logic_vector(31 downto 0);
748 
    signal M2GATEDHMASTLOCK        : std_logic;
749 
    signal M2GATEDHSIZE            : std_logic_vector(2 downto 0);
750 
    signal M2GATEDHTRANS           : std_logic;
751 
    signal M2GATEDHWRITE           : std_logic;
752 
    signal m2PrevDataSlaveReady    : std_logic;
753 
    signal m2s0AddrSel             : std_logic;
754 
    signal m2s0DataSel             : std_logic;
755 
    signal s0m2AddrReady           : std_logic;
756 
    signal s0m2DataReady           : std_logic;
757 
    signal s0m2HResp               : std_logic;
758 
    signal m2s0AddrSel_int         : std_logic;
759 
    signal m2s0DataSel_int         : std_logic;
760 
    signal s0m2AddrReady_int       : std_logic;
761 
    signal s0m2DataReady_int       : std_logic;
762 
    signal s0m2HResp_int           : std_logic;
763 
    signal m2s1AddrSel             : std_logic;
764 
    signal m2s1DataSel             : std_logic;
765 
    signal s1m2AddrReady           : std_logic;
766 
    signal s1m2DataReady           : std_logic;
767 
    signal s1m2HResp               : std_logic;
768 
    signal m2s1AddrSel_int         : std_logic;
769 
    signal m2s1DataSel_int         : std_logic;
770 
    signal s1m2AddrReady_int       : std_logic;
771 
    signal s1m2DataReady_int       : std_logic;
772 
    signal s1m2HResp_int           : std_logic;
773 
    signal m2s2AddrSel             : std_logic;
774 
    signal m2s2DataSel             : std_logic;
775 
    signal s2m2AddrReady           : std_logic;
776 
    signal s2m2DataReady           : std_logic;
777 
    signal s2m2HResp               : std_logic;
778 
    signal m2s2AddrSel_int         : std_logic;
779 
    signal m2s2DataSel_int         : std_logic;
780 
    signal s2m2AddrReady_int       : std_logic;
781 
    signal s2m2DataReady_int       : std_logic;
782 
    signal s2m2HResp_int           : std_logic;
783 
    signal m2s3AddrSel             : std_logic;
784 
    signal m2s3DataSel             : std_logic;
785 
    signal s3m2AddrReady           : std_logic;
786 
    signal s3m2DataReady           : std_logic;
787 
    signal s3m2HResp               : std_logic;
788 
    signal m2s3AddrSel_int         : std_logic;
789 
    signal m2s3DataSel_int         : std_logic;
790 
    signal s3m2AddrReady_int       : std_logic;
791 
    signal s3m2DataReady_int       : std_logic;
792 
    signal s3m2HResp_int           : std_logic;
793 
    signal m2s4AddrSel             : std_logic;
794 
    signal m2s4DataSel             : std_logic;
795 
    signal s4m2AddrReady           : std_logic;
796 
    signal s4m2DataReady           : std_logic;
797 
    signal s4m2HResp               : std_logic;
798 
    signal m2s4AddrSel_int         : std_logic;
799 
    signal m2s4DataSel_int         : std_logic;
800 
    signal s4m2AddrReady_int       : std_logic;
801 
    signal s4m2DataReady_int       : std_logic;
802 
    signal s4m2HResp_int           : std_logic;
803 
    signal m2s5AddrSel             : std_logic;
804 
    signal m2s5DataSel             : std_logic;
805 
    signal s5m2AddrReady           : std_logic;
806 
    signal s5m2DataReady           : std_logic;
807 
    signal s5m2HResp               : std_logic;
808 
    signal m2s5AddrSel_int         : std_logic;
809 
    signal m2s5DataSel_int         : std_logic;
810 
    signal s5m2AddrReady_int       : std_logic;
811 
    signal s5m2DataReady_int       : std_logic;
812 
    signal s5m2HResp_int           : std_logic;
813 
    signal m2s6AddrSel             : std_logic;
814 
    signal m2s6DataSel             : std_logic;
815 
    signal s6m2AddrReady           : std_logic;
816 
    signal s6m2DataReady           : std_logic;
817 
    signal s6m2HResp               : std_logic;
818 
    signal m2s6AddrSel_int         : std_logic;
819 
    signal m2s6DataSel_int         : std_logic;
820 
    signal s6m2AddrReady_int       : std_logic;
821 
    signal s6m2DataReady_int       : std_logic;
822 
    signal s6m2HResp_int           : std_logic;
823 
    signal m2s7AddrSel             : std_logic;
824 
    signal m2s7DataSel             : std_logic;
825 
    signal s7m2AddrReady           : std_logic;
826 
    signal s7m2DataReady           : std_logic;
827 
    signal s7m2HResp               : std_logic;
828 
    signal m2s7AddrSel_int         : std_logic;
829 
    signal m2s7DataSel_int         : std_logic;
830 
    signal s7m2AddrReady_int       : std_logic;
831 
    signal s7m2DataReady_int       : std_logic;
832 
    signal s7m2HResp_int           : std_logic;
833 
    signal m2s8AddrSel             : std_logic;
834 
    signal m2s8DataSel             : std_logic;
835 
    signal s8m2AddrReady           : std_logic;
836 
    signal s8m2DataReady           : std_logic;
837 
    signal s8m2HResp               : std_logic;
838 
    signal m2s8AddrSel_int         : std_logic;
839 
    signal m2s8DataSel_int         : std_logic;
840 
    signal s8m2AddrReady_int       : std_logic;
841 
    signal s8m2DataReady_int       : std_logic;
842 
    signal s8m2HResp_int           : std_logic;
843 
    signal m2s9AddrSel             : std_logic;
844 
    signal m2s9DataSel             : std_logic;
845 
    signal s9m2AddrReady           : std_logic;
846 
    signal s9m2DataReady           : std_logic;
847 
    signal s9m2HResp               : std_logic;
848 
    signal m2s9AddrSel_int         : std_logic;
849 
    signal m2s9DataSel_int         : std_logic;
850 
    signal s9m2AddrReady_int       : std_logic;
851 
    signal s9m2DataReady_int       : std_logic;
852 
    signal s9m2HResp_int           : std_logic;
853 
    signal m2s10AddrSel            : std_logic;
854 
    signal m2s10DataSel            : std_logic;
855 
    signal s10m2AddrReady          : std_logic;
856 
    signal s10m2DataReady          : std_logic;
857 
    signal s10m2HResp              : std_logic;
858 
    signal m2s10AddrSel_int        : std_logic;
859 
    signal m2s10DataSel_int        : std_logic;
860 
    signal s10m2AddrReady_int      : std_logic;
861 
    signal s10m2DataReady_int      : std_logic;
862 
    signal s10m2HResp_int          : std_logic;
863 
    signal m2s11AddrSel            : std_logic;
864 
    signal m2s11DataSel            : std_logic;
865 
    signal s11m2AddrReady          : std_logic;
866 
    signal s11m2DataReady          : std_logic;
867 
    signal s11m2HResp              : std_logic;
868 
    signal m2s11AddrSel_int        : std_logic;
869 
    signal m2s11DataSel_int        : std_logic;
870 
    signal s11m2AddrReady_int      : std_logic;
871 
    signal s11m2DataReady_int      : std_logic;
872 
    signal s11m2HResp_int          : std_logic;
873 
    signal m2s12AddrSel            : std_logic;
874 
    signal m2s12DataSel            : std_logic;
875 
    signal s12m2AddrReady          : std_logic;
876 
    signal s12m2DataReady          : std_logic;
877 
    signal s12m2HResp              : std_logic;
878 
    signal m2s12AddrSel_int        : std_logic;
879 
    signal m2s12DataSel_int        : std_logic;
880 
    signal s12m2AddrReady_int      : std_logic;
881 
    signal s12m2DataReady_int      : std_logic;
882 
    signal s12m2HResp_int          : std_logic;
883 
    signal m2s13AddrSel            : std_logic;
884 
    signal m2s13DataSel            : std_logic;
885 
    signal s13m2AddrReady          : std_logic;
886 
    signal s13m2DataReady          : std_logic;
887 
    signal s13m2HResp              : std_logic;
888 
    signal m2s13AddrSel_int        : std_logic;
889 
    signal m2s13DataSel_int        : std_logic;
890 
    signal s13m2AddrReady_int      : std_logic;
891 
    signal s13m2DataReady_int      : std_logic;
892 
    signal s13m2HResp_int          : std_logic;
893 
    signal m2s14AddrSel            : std_logic;
894 
    signal m2s14DataSel            : std_logic;
895 
    signal s14m2AddrReady          : std_logic;
896 
    signal s14m2DataReady          : std_logic;
897 
    signal s14m2HResp              : std_logic;
898 
    signal m2s14AddrSel_int        : std_logic;
899 
    signal m2s14DataSel_int        : std_logic;
900 
    signal s14m2AddrReady_int      : std_logic;
901 
    signal s14m2DataReady_int      : std_logic;
902 
    signal s14m2HResp_int          : std_logic;
903 
    signal m2s15AddrSel            : std_logic;
904 
    signal m2s15DataSel            : std_logic;
905 
    signal s15m2AddrReady          : std_logic;
906 
    signal s15m2DataReady          : std_logic;
907 
    signal s15m2HResp              : std_logic;
908 
    signal m2s15AddrSel_int        : std_logic;
909 
    signal m2s15DataSel_int        : std_logic;
910 
    signal s15m2AddrReady_int      : std_logic;
911 
    signal s15m2DataReady_int      : std_logic;
912 
    signal s15m2HResp_int          : std_logic;
913 
    signal m2s16AddrSel            : std_logic;
914 
    signal m2s16DataSel            : std_logic;
915 
    signal s16m2AddrReady          : std_logic;
916 
    signal s16m2DataReady          : std_logic;
917 
    signal s16m2HResp              : std_logic;
918 
    signal m2s16AddrSel_int        : std_logic;
919 
    signal m2s16DataSel_int        : std_logic;
920 
    signal s16m2AddrReady_int      : std_logic;
921 
    signal s16m2DataReady_int      : std_logic;
922 
    signal s16m2HResp_int          : std_logic;
923 
    signal M3GATEDHADDR            : std_logic_vector(31 downto 0);
924 
    signal M3GATEDHMASTLOCK        : std_logic;
925 
    signal M3GATEDHSIZE            : std_logic_vector(2 downto 0);
926 
    signal M3GATEDHTRANS           : std_logic;
927 
    signal M3GATEDHWRITE           : std_logic;
928 
    signal m3PrevDataSlaveReady    : std_logic;
929 
    signal m3s0AddrSel             : std_logic;
930 
    signal m3s0DataSel             : std_logic;
931 
    signal s0m3AddrReady           : std_logic;
932 
    signal s0m3DataReady           : std_logic;
933 
    signal s0m3HResp               : std_logic;
934 
    signal m3s0AddrSel_int         : std_logic;
935 
    signal m3s0DataSel_int         : std_logic;
936 
    signal s0m3AddrReady_int       : std_logic;
937 
    signal s0m3DataReady_int       : std_logic;
938 
    signal s0m3HResp_int           : std_logic;
939 
    signal m3s1AddrSel             : std_logic;
940 
    signal m3s1DataSel             : std_logic;
941 
    signal s1m3AddrReady           : std_logic;
942 
    signal s1m3DataReady           : std_logic;
943 
    signal s1m3HResp               : std_logic;
944 
    signal m3s1AddrSel_int         : std_logic;
945 
    signal m3s1DataSel_int         : std_logic;
946 
    signal s1m3AddrReady_int       : std_logic;
947 
    signal s1m3DataReady_int       : std_logic;
948 
    signal s1m3HResp_int           : std_logic;
949 
    signal m3s2AddrSel             : std_logic;
950 
    signal m3s2DataSel             : std_logic;
951 
    signal s2m3AddrReady           : std_logic;
952 
    signal s2m3DataReady           : std_logic;
953 
    signal s2m3HResp               : std_logic;
954 
    signal m3s2AddrSel_int         : std_logic;
955 
    signal m3s2DataSel_int         : std_logic;
956 
    signal s2m3AddrReady_int       : std_logic;
957 
    signal s2m3DataReady_int       : std_logic;
958 
    signal s2m3HResp_int           : std_logic;
959 
    signal m3s3AddrSel             : std_logic;
960 
    signal m3s3DataSel             : std_logic;
961 
    signal s3m3AddrReady           : std_logic;
962 
    signal s3m3DataReady           : std_logic;
963 
    signal s3m3HResp               : std_logic;
964 
    signal m3s3AddrSel_int         : std_logic;
965 
    signal m3s3DataSel_int         : std_logic;
966 
    signal s3m3AddrReady_int       : std_logic;
967 
    signal s3m3DataReady_int       : std_logic;
968 
    signal s3m3HResp_int           : std_logic;
969 
    signal m3s4AddrSel             : std_logic;
970 
    signal m3s4DataSel             : std_logic;
971 
    signal s4m3AddrReady           : std_logic;
972 
    signal s4m3DataReady           : std_logic;
973 
    signal s4m3HResp               : std_logic;
974 
    signal m3s4AddrSel_int         : std_logic;
975 
    signal m3s4DataSel_int         : std_logic;
976 
    signal s4m3AddrReady_int       : std_logic;
977 
    signal s4m3DataReady_int       : std_logic;
978 
    signal s4m3HResp_int           : std_logic;
979 
    signal m3s5AddrSel             : std_logic;
980 
    signal m3s5DataSel             : std_logic;
981 
    signal s5m3AddrReady           : std_logic;
982 
    signal s5m3DataReady           : std_logic;
983 
    signal s5m3HResp               : std_logic;
984 
    signal m3s5AddrSel_int         : std_logic;
985 
    signal m3s5DataSel_int         : std_logic;
986 
    signal s5m3AddrReady_int       : std_logic;
987 
    signal s5m3DataReady_int       : std_logic;
988 
    signal s5m3HResp_int           : std_logic;
989 
    signal m3s6AddrSel             : std_logic;
990 
    signal m3s6DataSel             : std_logic;
991 
    signal s6m3AddrReady           : std_logic;
992 
    signal s6m3DataReady           : std_logic;
993 
    signal s6m3HResp               : std_logic;
994 
    signal m3s6AddrSel_int         : std_logic;
995 
    signal m3s6DataSel_int         : std_logic;
996 
    signal s6m3AddrReady_int       : std_logic;
997 
    signal s6m3DataReady_int       : std_logic;
998 
    signal s6m3HResp_int           : std_logic;
999 
    signal m3s7AddrSel             : std_logic;
1000 
    signal m3s7DataSel             : std_logic;
1001 
    signal s7m3AddrReady           : std_logic;
1002 
    signal s7m3DataReady           : std_logic;
1003 
    signal s7m3HResp               : std_logic;
1004 
    signal m3s7AddrSel_int         : std_logic;
1005 
    signal m3s7DataSel_int         : std_logic;
1006 
    signal s7m3AddrReady_int       : std_logic;
1007 
    signal s7m3DataReady_int       : std_logic;
1008 
    signal s7m3HResp_int           : std_logic;
1009 
    signal m3s8AddrSel             : std_logic;
1010 
    signal m3s8DataSel             : std_logic;
1011 
    signal s8m3AddrReady           : std_logic;
1012 
    signal s8m3DataReady           : std_logic;
1013 
    signal s8m3HResp               : std_logic;
1014 
    signal m3s8AddrSel_int         : std_logic;
1015 
    signal m3s8DataSel_int         : std_logic;
1016 
    signal s8m3AddrReady_int       : std_logic;
1017 
    signal s8m3DataReady_int       : std_logic;
1018 
    signal s8m3HResp_int           : std_logic;
1019 
    signal m3s9AddrSel             : std_logic;
1020 
    signal m3s9DataSel             : std_logic;
1021 
    signal s9m3AddrReady           : std_logic;
1022 
    signal s9m3DataReady           : std_logic;
1023 
    signal s9m3HResp               : std_logic;
1024 
    signal m3s9AddrSel_int         : std_logic;
1025 
    signal m3s9DataSel_int         : std_logic;
1026 
    signal s9m3AddrReady_int       : std_logic;
1027 
    signal s9m3DataReady_int       : std_logic;
1028 
    signal s9m3HResp_int           : std_logic;
1029 
    signal m3s10AddrSel            : std_logic;
1030 
    signal m3s10DataSel            : std_logic;
1031 
    signal s10m3AddrReady          : std_logic;
1032 
    signal s10m3DataReady          : std_logic;
1033 
    signal s10m3HResp              : std_logic;
1034 
    signal m3s10AddrSel_int        : std_logic;
1035 
    signal m3s10DataSel_int        : std_logic;
1036 
    signal s10m3AddrReady_int      : std_logic;
1037 
    signal s10m3DataReady_int      : std_logic;
1038 
    signal s10m3HResp_int          : std_logic;
1039 
    signal m3s11AddrSel            : std_logic;
1040 
    signal m3s11DataSel            : std_logic;
1041 
    signal s11m3AddrReady          : std_logic;
1042 
    signal s11m3DataReady          : std_logic;
1043 
    signal s11m3HResp              : std_logic;
1044 
    signal m3s11AddrSel_int        : std_logic;
1045 
    signal m3s11DataSel_int        : std_logic;
1046 
    signal s11m3AddrReady_int      : std_logic;
1047 
    signal s11m3DataReady_int      : std_logic;
1048 
    signal s11m3HResp_int          : std_logic;
1049 
    signal m3s12AddrSel            : std_logic;
1050 
    signal m3s12DataSel            : std_logic;
1051 
    signal s12m3AddrReady          : std_logic;
1052 
    signal s12m3DataReady          : std_logic;
1053 
    signal s12m3HResp              : std_logic;
1054 
    signal m3s12AddrSel_int        : std_logic;
1055 
    signal m3s12DataSel_int        : std_logic;
1056 
    signal s12m3AddrReady_int      : std_logic;
1057 
    signal s12m3DataReady_int      : std_logic;
1058 
    signal s12m3HResp_int          : std_logic;
1059 
    signal m3s13AddrSel            : std_logic;
1060 
    signal m3s13DataSel            : std_logic;
1061 
    signal s13m3AddrReady          : std_logic;
1062 
    signal s13m3DataReady          : std_logic;
1063 
    signal s13m3HResp              : std_logic;
1064 
    signal m3s13AddrSel_int        : std_logic;
1065 
    signal m3s13DataSel_int        : std_logic;
1066 
    signal s13m3AddrReady_int      : std_logic;
1067 
    signal s13m3DataReady_int      : std_logic;
1068 
    signal s13m3HResp_int          : std_logic;
1069 
    signal m3s14AddrSel            : std_logic;
1070 
    signal m3s14DataSel            : std_logic;
1071 
    signal s14m3AddrReady          : std_logic;
1072 
    signal s14m3DataReady          : std_logic;
1073 
    signal s14m3HResp              : std_logic;
1074 
    signal m3s14AddrSel_int        : std_logic;
1075 
    signal m3s14DataSel_int        : std_logic;
1076 
    signal s14m3AddrReady_int      : std_logic;
1077 
    signal s14m3DataReady_int      : std_logic;
1078 
    signal s14m3HResp_int          : std_logic;
1079 
    signal m3s15AddrSel            : std_logic;
1080 
    signal m3s15DataSel            : std_logic;
1081 
    signal s15m3AddrReady          : std_logic;
1082 
    signal s15m3DataReady          : std_logic;
1083 
    signal s15m3HResp              : std_logic;
1084 
    signal m3s15AddrSel_int        : std_logic;
1085 
    signal m3s15DataSel_int        : std_logic;
1086 
    signal s15m3AddrReady_int      : std_logic;
1087 
    signal s15m3DataReady_int      : std_logic;
1088 
    signal s15m3HResp_int          : std_logic;
1089 
    signal m3s16AddrSel            : std_logic;
1090 
    signal m3s16DataSel            : std_logic;
1091 
    signal s16m3AddrReady          : std_logic;
1092 
    signal s16m3DataReady          : std_logic;
1093 
    signal s16m3HResp              : std_logic;
1094 
    signal m3s16AddrSel_int        : std_logic;
1095 
    signal m3s16DataSel_int        : std_logic;
1096 
    signal s16m3AddrReady_int      : std_logic;
1097 
    signal s16m3DataReady_int      : std_logic;
1098 
    signal s16m3HResp_int          : std_logic;
1099 
    signal M0_HRDATA_S0            : std_logic_vector(31 downto 0);
1100 
    signal M0_HRDATA_S1            : std_logic_vector(31 downto 0);
1101 
    signal M0_HRDATA_S2            : std_logic_vector(31 downto 0);
1102 
    signal M0_HRDATA_S3            : std_logic_vector(31 downto 0);
1103 
    signal M0_HRDATA_S4            : std_logic_vector(31 downto 0);
1104 
    signal M0_HRDATA_S5            : std_logic_vector(31 downto 0);
1105 
    signal M0_HRDATA_S6            : std_logic_vector(31 downto 0);
1106 
    signal M0_HRDATA_S7            : std_logic_vector(31 downto 0);
1107 
    signal M0_HRDATA_S8            : std_logic_vector(31 downto 0);
1108 
    signal M0_HRDATA_S9            : std_logic_vector(31 downto 0);
1109 
    signal M0_HRDATA_S10           : std_logic_vector(31 downto 0);
1110 
    signal M0_HRDATA_S11           : std_logic_vector(31 downto 0);
1111 
    signal M0_HRDATA_S12           : std_logic_vector(31 downto 0);
1112 
    signal M0_HRDATA_S13           : std_logic_vector(31 downto 0);
1113 
    signal M0_HRDATA_S14           : std_logic_vector(31 downto 0);
1114 
    signal M0_HRDATA_S15           : std_logic_vector(31 downto 0);
1115 
    signal M0_HRDATA_S16           : std_logic_vector(31 downto 0);
1116 
    signal M1_HRDATA_S0            : std_logic_vector(31 downto 0);
1117 
    signal M1_HRDATA_S1            : std_logic_vector(31 downto 0);
1118 
    signal M1_HRDATA_S2            : std_logic_vector(31 downto 0);
1119 
    signal M1_HRDATA_S3            : std_logic_vector(31 downto 0);
1120 
    signal M1_HRDATA_S4            : std_logic_vector(31 downto 0);
1121 
    signal M1_HRDATA_S5            : std_logic_vector(31 downto 0);
1122 
    signal M1_HRDATA_S6            : std_logic_vector(31 downto 0);
1123 
    signal M1_HRDATA_S7            : std_logic_vector(31 downto 0);
1124 
    signal M1_HRDATA_S8            : std_logic_vector(31 downto 0);
1125 
    signal M1_HRDATA_S9            : std_logic_vector(31 downto 0);
1126 
    signal M1_HRDATA_S10           : std_logic_vector(31 downto 0);
1127 
    signal M1_HRDATA_S11           : std_logic_vector(31 downto 0);
1128 
    signal M1_HRDATA_S12           : std_logic_vector(31 downto 0);
1129 
    signal M1_HRDATA_S13           : std_logic_vector(31 downto 0);
1130 
    signal M1_HRDATA_S14           : std_logic_vector(31 downto 0);
1131 
    signal M1_HRDATA_S15           : std_logic_vector(31 downto 0);
1132 
    signal M1_HRDATA_S16           : std_logic_vector(31 downto 0);
1133 
    signal M2_HRDATA_S0            : std_logic_vector(31 downto 0);
1134 
    signal M2_HRDATA_S1            : std_logic_vector(31 downto 0);
1135 
    signal M2_HRDATA_S2            : std_logic_vector(31 downto 0);
1136 
    signal M2_HRDATA_S3            : std_logic_vector(31 downto 0);
1137 
    signal M2_HRDATA_S4            : std_logic_vector(31 downto 0);
1138 
    signal M2_HRDATA_S5            : std_logic_vector(31 downto 0);
1139 
    signal M2_HRDATA_S6            : std_logic_vector(31 downto 0);
1140 
    signal M2_HRDATA_S7            : std_logic_vector(31 downto 0);
1141 
    signal M2_HRDATA_S8            : std_logic_vector(31 downto 0);
1142 
    signal M2_HRDATA_S9            : std_logic_vector(31 downto 0);
1143 
    signal M2_HRDATA_S10           : std_logic_vector(31 downto 0);
1144 
    signal M2_HRDATA_S11           : std_logic_vector(31 downto 0);
1145 
    signal M2_HRDATA_S12           : std_logic_vector(31 downto 0);
1146 
    signal M2_HRDATA_S13           : std_logic_vector(31 downto 0);
1147 
    signal M2_HRDATA_S14           : std_logic_vector(31 downto 0);
1148 
    signal M2_HRDATA_S15           : std_logic_vector(31 downto 0);
1149 
    signal M2_HRDATA_S16           : std_logic_vector(31 downto 0);
1150 
    signal M3_HRDATA_S0            : std_logic_vector(31 downto 0);
1151 
    signal M3_HRDATA_S1            : std_logic_vector(31 downto 0);
1152 
    signal M3_HRDATA_S2            : std_logic_vector(31 downto 0);
1153 
    signal M3_HRDATA_S3            : std_logic_vector(31 downto 0);
1154 
    signal M3_HRDATA_S4            : std_logic_vector(31 downto 0);
1155 
    signal M3_HRDATA_S5            : std_logic_vector(31 downto 0);
1156 
    signal M3_HRDATA_S6            : std_logic_vector(31 downto 0);
1157 
    signal M3_HRDATA_S7            : std_logic_vector(31 downto 0);
1158 
    signal M3_HRDATA_S8            : std_logic_vector(31 downto 0);
1159 
    signal M3_HRDATA_S9            : std_logic_vector(31 downto 0);
1160 
    signal M3_HRDATA_S10           : std_logic_vector(31 downto 0);
1161 
    signal M3_HRDATA_S11           : std_logic_vector(31 downto 0);
1162 
    signal M3_HRDATA_S12           : std_logic_vector(31 downto 0);
1163 
    signal M3_HRDATA_S13           : std_logic_vector(31 downto 0);
1164 
    signal M3_HRDATA_S14           : std_logic_vector(31 downto 0);
1165 
    signal M3_HRDATA_S15           : std_logic_vector(31 downto 0);
1166 
    signal M3_HRDATA_S16           : std_logic_vector(31 downto 0);
1167 
    signal M0_HREADYOUT_S0         : std_logic;
1168 
    signal M0_HREADYOUT_S1         : std_logic;
1169 
    signal M0_HREADYOUT_S2         : std_logic;
1170 
    signal M0_HREADYOUT_S3         : std_logic;
1171 
    signal M0_HREADYOUT_S4         : std_logic;
1172 
    signal M0_HREADYOUT_S5         : std_logic;
1173 
    signal M0_HREADYOUT_S6         : std_logic;
1174 
    signal M0_HREADYOUT_S7         : std_logic;
1175 
    signal M0_HREADYOUT_S8         : std_logic;
1176 
    signal M0_HREADYOUT_S9         : std_logic;
1177 
    signal M0_HREADYOUT_S10        : std_logic;
1178 
    signal M0_HREADYOUT_S11        : std_logic;
1179 
    signal M0_HREADYOUT_S12        : std_logic;
1180 
    signal M0_HREADYOUT_S13        : std_logic;
1181 
    signal M0_HREADYOUT_S14        : std_logic;
1182 
    signal M0_HREADYOUT_S15        : std_logic;
1183 
    signal M0_HREADYOUT_S16        : std_logic;
1184 
    signal M1_HREADYOUT_S0         : std_logic;
1185 
    signal M1_HREADYOUT_S1         : std_logic;
1186 
    signal M1_HREADYOUT_S2         : std_logic;
1187 
    signal M1_HREADYOUT_S3         : std_logic;
1188 
    signal M1_HREADYOUT_S4         : std_logic;
1189 
    signal M1_HREADYOUT_S5         : std_logic;
1190 
    signal M1_HREADYOUT_S6         : std_logic;
1191 
    signal M1_HREADYOUT_S7         : std_logic;
1192 
    signal M1_HREADYOUT_S8         : std_logic;
1193 
    signal M1_HREADYOUT_S9         : std_logic;
1194 
    signal M1_HREADYOUT_S10        : std_logic;
1195 
    signal M1_HREADYOUT_S11        : std_logic;
1196 
    signal M1_HREADYOUT_S12        : std_logic;
1197 
    signal M1_HREADYOUT_S13        : std_logic;
1198 
    signal M1_HREADYOUT_S14        : std_logic;
1199 
    signal M1_HREADYOUT_S15        : std_logic;
1200 
    signal M1_HREADYOUT_S16        : std_logic;
1201 
    signal M2_HREADYOUT_S0         : std_logic;
1202 
    signal M2_HREADYOUT_S1         : std_logic;
1203 
    signal M2_HREADYOUT_S2         : std_logic;
1204 
    signal M2_HREADYOUT_S3         : std_logic;
1205 
    signal M2_HREADYOUT_S4         : std_logic;
1206 
    signal M2_HREADYOUT_S5         : std_logic;
1207 
    signal M2_HREADYOUT_S6         : std_logic;
1208 
    signal M2_HREADYOUT_S7         : std_logic;
1209 
    signal M2_HREADYOUT_S8         : std_logic;
1210 
    signal M2_HREADYOUT_S9         : std_logic;
1211 
    signal M2_HREADYOUT_S10        : std_logic;
1212 
    signal M2_HREADYOUT_S11        : std_logic;
1213 
    signal M2_HREADYOUT_S12        : std_logic;
1214 
    signal M2_HREADYOUT_S13        : std_logic;
1215 
    signal M2_HREADYOUT_S14        : std_logic;
1216 
    signal M2_HREADYOUT_S15        : std_logic;
1217 
    signal M2_HREADYOUT_S16        : std_logic;
1218 
    signal M3_HREADYOUT_S0         : std_logic;
1219 
    signal M3_HREADYOUT_S1         : std_logic;
1220 
    signal M3_HREADYOUT_S2         : std_logic;
1221 
    signal M3_HREADYOUT_S3         : std_logic;
1222 
    signal M3_HREADYOUT_S4         : std_logic;
1223 
    signal M3_HREADYOUT_S5         : std_logic;
1224 
    signal M3_HREADYOUT_S6         : std_logic;
1225 
    signal M3_HREADYOUT_S7         : std_logic;
1226 
    signal M3_HREADYOUT_S8         : std_logic;
1227 
    signal M3_HREADYOUT_S9         : std_logic;
1228 
    signal M3_HREADYOUT_S10        : std_logic;
1229 
    signal M3_HREADYOUT_S11        : std_logic;
1230 
    signal M3_HREADYOUT_S12        : std_logic;
1231 
    signal M3_HREADYOUT_S13        : std_logic;
1232 
    signal M3_HREADYOUT_S14        : std_logic;
1233 
    signal M3_HREADYOUT_S15        : std_logic;
1234 
    signal M3_HREADYOUT_S16        : std_logic;
1235 
    signal INT_HREADYOUT_S0        : std_logic;
1236 
    signal INT_HREADYOUT_S1        : std_logic;
1237 
    signal INT_HREADYOUT_S2        : std_logic;
1238 
    signal INT_HREADYOUT_S3        : std_logic;
1239 
    signal INT_HREADYOUT_S4        : std_logic;
1240 
    signal INT_HREADYOUT_S5        : std_logic;
1241 
    signal INT_HREADYOUT_S6        : std_logic;
1242 
    signal INT_HREADYOUT_S7        : std_logic;
1243 
    signal INT_HREADYOUT_S8        : std_logic;
1244 
    signal INT_HREADYOUT_S9        : std_logic;
1245 
    signal INT_HREADYOUT_S10       : std_logic;
1246 
    signal INT_HREADYOUT_S11       : std_logic;
1247 
    signal INT_HREADYOUT_S12       : std_logic;
1248 
    signal INT_HREADYOUT_S13       : std_logic;
1249 
    signal INT_HREADYOUT_S14       : std_logic;
1250 
    signal INT_HREADYOUT_S15       : std_logic;
1251 
    signal INT_HREADYOUT_S16       : std_logic;
1252 
    signal INT_HRESP_S0            : std_logic;
1253 
    signal INT_HRESP_S1            : std_logic;
1254 
    signal INT_HRESP_S2            : std_logic;
1255 
    signal INT_HRESP_S3            : std_logic;
1256 
    signal INT_HRESP_S4            : std_logic;
1257 
    signal INT_HRESP_S5            : std_logic;
1258 
    signal INT_HRESP_S6            : std_logic;
1259 
    signal INT_HRESP_S7            : std_logic;
1260 
    signal INT_HRESP_S8            : std_logic;
1261 
    signal INT_HRESP_S9            : std_logic;
1262 
    signal INT_HRESP_S10           : std_logic;
1263 
    signal INT_HRESP_S11           : std_logic;
1264 
    signal INT_HRESP_S12           : std_logic;
1265 
    signal INT_HRESP_S13           : std_logic;
1266 
    signal INT_HRESP_S14           : std_logic;
1267 
    signal INT_HRESP_S15           : std_logic;
1268 
    signal INT_HRESP_S16           : std_logic;
1269 
    signal HWDATA_M0S0             : std_logic_vector(31 downto 0);
1270 
    signal HWDATA_M0S1             : std_logic_vector(31 downto 0);
1271 
    signal HWDATA_M0S2             : std_logic_vector(31 downto 0);
1272 
    signal HWDATA_M0S3             : std_logic_vector(31 downto 0);
1273 
    signal HWDATA_M0S4             : std_logic_vector(31 downto 0);
1274 
    signal HWDATA_M0S5             : std_logic_vector(31 downto 0);
1275 
    signal HWDATA_M0S6             : std_logic_vector(31 downto 0);
1276 
    signal HWDATA_M0S7             : std_logic_vector(31 downto 0);
1277 
    signal HWDATA_M0S8             : std_logic_vector(31 downto 0);
1278 
    signal HWDATA_M0S9             : std_logic_vector(31 downto 0);
1279 
    signal HWDATA_M0S10            : std_logic_vector(31 downto 0);
1280 
    signal HWDATA_M0S11            : std_logic_vector(31 downto 0);
1281 
    signal HWDATA_M0S12            : std_logic_vector(31 downto 0);
1282 
    signal HWDATA_M0S13            : std_logic_vector(31 downto 0);
1283 
    signal HWDATA_M0S14            : std_logic_vector(31 downto 0);
1284 
    signal HWDATA_M0S15            : std_logic_vector(31 downto 0);
1285 
    signal HWDATA_M0S16            : std_logic_vector(31 downto 0);
1286 
    signal HWDATA_M1S0             : std_logic_vector(31 downto 0);
1287 
    signal HWDATA_M1S1             : std_logic_vector(31 downto 0);
1288 
    signal HWDATA_M1S2             : std_logic_vector(31 downto 0);
1289 
    signal HWDATA_M1S3             : std_logic_vector(31 downto 0);
1290 
    signal HWDATA_M1S4             : std_logic_vector(31 downto 0);
1291 
    signal HWDATA_M1S5             : std_logic_vector(31 downto 0);
1292 
    signal HWDATA_M1S6             : std_logic_vector(31 downto 0);
1293 
    signal HWDATA_M1S7             : std_logic_vector(31 downto 0);
1294 
    signal HWDATA_M1S8             : std_logic_vector(31 downto 0);
1295 
    signal HWDATA_M1S9             : std_logic_vector(31 downto 0);
1296 
    signal HWDATA_M1S10            : std_logic_vector(31 downto 0);
1297 
    signal HWDATA_M1S11            : std_logic_vector(31 downto 0);
1298 
    signal HWDATA_M1S12            : std_logic_vector(31 downto 0);
1299 
    signal HWDATA_M1S13            : std_logic_vector(31 downto 0);
1300 
    signal HWDATA_M1S14            : std_logic_vector(31 downto 0);
1301 
    signal HWDATA_M1S15            : std_logic_vector(31 downto 0);
1302 
    signal HWDATA_M1S16            : std_logic_vector(31 downto 0);
1303 
    signal HWDATA_M2S0             : std_logic_vector(31 downto 0);
1304 
    signal HWDATA_M2S1             : std_logic_vector(31 downto 0);
1305 
    signal HWDATA_M2S2             : std_logic_vector(31 downto 0);
1306 
    signal HWDATA_M2S3             : std_logic_vector(31 downto 0);
1307 
    signal HWDATA_M2S4             : std_logic_vector(31 downto 0);
1308 
    signal HWDATA_M2S5             : std_logic_vector(31 downto 0);
1309 
    signal HWDATA_M2S6             : std_logic_vector(31 downto 0);
1310 
    signal HWDATA_M2S7             : std_logic_vector(31 downto 0);
1311 
    signal HWDATA_M2S8             : std_logic_vector(31 downto 0);
1312 
    signal HWDATA_M2S9             : std_logic_vector(31 downto 0);
1313 
    signal HWDATA_M2S10            : std_logic_vector(31 downto 0);
1314 
    signal HWDATA_M2S11            : std_logic_vector(31 downto 0);
1315 
    signal HWDATA_M2S12            : std_logic_vector(31 downto 0);
1316 
    signal HWDATA_M2S13            : std_logic_vector(31 downto 0);
1317 
    signal HWDATA_M2S14            : std_logic_vector(31 downto 0);
1318 
    signal HWDATA_M2S15            : std_logic_vector(31 downto 0);
1319 
    signal HWDATA_M2S16            : std_logic_vector(31 downto 0);
1320 
    signal HWDATA_M3S0             : std_logic_vector(31 downto 0);
1321 
    signal HWDATA_M3S1             : std_logic_vector(31 downto 0);
1322 
    signal HWDATA_M3S2             : std_logic_vector(31 downto 0);
1323 
    signal HWDATA_M3S3             : std_logic_vector(31 downto 0);
1324 
    signal HWDATA_M3S4             : std_logic_vector(31 downto 0);
1325 
    signal HWDATA_M3S5             : std_logic_vector(31 downto 0);
1326 
    signal HWDATA_M3S6             : std_logic_vector(31 downto 0);
1327 
    signal HWDATA_M3S7             : std_logic_vector(31 downto 0);
1328 
    signal HWDATA_M3S8             : std_logic_vector(31 downto 0);
1329 
    signal HWDATA_M3S9             : std_logic_vector(31 downto 0);
1330 
    signal HWDATA_M3S10            : std_logic_vector(31 downto 0);
1331 
    signal HWDATA_M3S11            : std_logic_vector(31 downto 0);
1332 
    signal HWDATA_M3S12            : std_logic_vector(31 downto 0);
1333 
    signal HWDATA_M3S13            : std_logic_vector(31 downto 0);
1334 
    signal HWDATA_M3S14            : std_logic_vector(31 downto 0);
1335 
    signal HWDATA_M3S15            : std_logic_vector(31 downto 0);
1336 
    signal HWDATA_M3S16            : std_logic_vector(31 downto 0);
1337 
    signal m0s0GatedHADDR          : std_logic_vector(31 downto 0);
1338 
    signal m0s1GatedHADDR          : std_logic_vector(31 downto 0);
1339 
    signal m0s2GatedHADDR          : std_logic_vector(31 downto 0);
1340 
    signal m0s3GatedHADDR          : std_logic_vector(31 downto 0);
1341 
    signal m0s4GatedHADDR          : std_logic_vector(31 downto 0);
1342 
    signal m0s5GatedHADDR          : std_logic_vector(31 downto 0);
1343 
    signal m0s6GatedHADDR          : std_logic_vector(31 downto 0);
1344 
    signal m0s7GatedHADDR          : std_logic_vector(31 downto 0);
1345 
    signal m0s8GatedHADDR          : std_logic_vector(31 downto 0);
1346 
    signal m0s9GatedHADDR          : std_logic_vector(31 downto 0);
1347 
    signal m0s10GatedHADDR         : std_logic_vector(31 downto 0);
1348 
    signal m0s11GatedHADDR         : std_logic_vector(31 downto 0);
1349 
    signal m0s12GatedHADDR         : std_logic_vector(31 downto 0);
1350 
    signal m0s13GatedHADDR         : std_logic_vector(31 downto 0);
1351 
    signal m0s14GatedHADDR         : std_logic_vector(31 downto 0);
1352 
    signal m0s15GatedHADDR         : std_logic_vector(31 downto 0);
1353 
    signal m0s16GatedHADDR         : std_logic_vector(31 downto 0);
1354 
    signal m1s0GatedHADDR          : std_logic_vector(31 downto 0);
1355 
    signal m1s1GatedHADDR          : std_logic_vector(31 downto 0);
1356 
    signal m1s2GatedHADDR          : std_logic_vector(31 downto 0);
1357 
    signal m1s3GatedHADDR          : std_logic_vector(31 downto 0);
1358 
    signal m1s4GatedHADDR          : std_logic_vector(31 downto 0);
1359 
    signal m1s5GatedHADDR          : std_logic_vector(31 downto 0);
1360 
    signal m1s6GatedHADDR          : std_logic_vector(31 downto 0);
1361 
    signal m1s7GatedHADDR          : std_logic_vector(31 downto 0);
1362 
    signal m1s8GatedHADDR          : std_logic_vector(31 downto 0);
1363 
    signal m1s9GatedHADDR          : std_logic_vector(31 downto 0);
1364 
    signal m1s10GatedHADDR         : std_logic_vector(31 downto 0);
1365 
    signal m1s11GatedHADDR         : std_logic_vector(31 downto 0);
1366 
    signal m1s12GatedHADDR         : std_logic_vector(31 downto 0);
1367 
    signal m1s13GatedHADDR         : std_logic_vector(31 downto 0);
1368 
    signal m1s14GatedHADDR         : std_logic_vector(31 downto 0);
1369 
    signal m1s15GatedHADDR         : std_logic_vector(31 downto 0);
1370 
    signal m1s16GatedHADDR         : std_logic_vector(31 downto 0);
1371 
    signal m0s0GatedHSIZE          : std_logic_vector(2 downto 0);
1372 
    signal m0s1GatedHSIZE          : std_logic_vector(2 downto 0);
1373 
    signal m0s2GatedHSIZE          : std_logic_vector(2 downto 0);
1374 
    signal m0s3GatedHSIZE          : std_logic_vector(2 downto 0);
1375 
    signal m0s4GatedHSIZE          : std_logic_vector(2 downto 0);
1376 
    signal m0s5GatedHSIZE          : std_logic_vector(2 downto 0);
1377 
    signal m0s6GatedHSIZE          : std_logic_vector(2 downto 0);
1378 
    signal m0s7GatedHSIZE          : std_logic_vector(2 downto 0);
1379 
    signal m0s8GatedHSIZE          : std_logic_vector(2 downto 0);
1380 
    signal m0s9GatedHSIZE          : std_logic_vector(2 downto 0);
1381 
    signal m0s10GatedHSIZE         : std_logic_vector(2 downto 0);
1382 
    signal m0s11GatedHSIZE         : std_logic_vector(2 downto 0);
1383 
    signal m0s12GatedHSIZE         : std_logic_vector(2 downto 0);
1384 
    signal m0s13GatedHSIZE         : std_logic_vector(2 downto 0);
1385 
    signal m0s14GatedHSIZE         : std_logic_vector(2 downto 0);
1386 
    signal m0s15GatedHSIZE         : std_logic_vector(2 downto 0);
1387 
    signal m0s16GatedHSIZE         : std_logic_vector(2 downto 0);
1388 
    signal m1s0GatedHSIZE          : std_logic_vector(2 downto 0);
1389 
    signal m1s1GatedHSIZE          : std_logic_vector(2 downto 0);
1390 
    signal m1s2GatedHSIZE          : std_logic_vector(2 downto 0);
1391 
    signal m1s3GatedHSIZE          : std_logic_vector(2 downto 0);
1392 
    signal m1s4GatedHSIZE          : std_logic_vector(2 downto 0);
1393 
    signal m1s5GatedHSIZE          : std_logic_vector(2 downto 0);
1394 
    signal m1s6GatedHSIZE          : std_logic_vector(2 downto 0);
1395 
    signal m1s7GatedHSIZE          : std_logic_vector(2 downto 0);
1396 
    signal m1s8GatedHSIZE          : std_logic_vector(2 downto 0);
1397 
    signal m1s9GatedHSIZE          : std_logic_vector(2 downto 0);
1398 
    signal m1s10GatedHSIZE         : std_logic_vector(2 downto 0);
1399 
    signal m1s11GatedHSIZE         : std_logic_vector(2 downto 0);
1400 
    signal m1s12GatedHSIZE         : std_logic_vector(2 downto 0);
1401 
    signal m1s13GatedHSIZE         : std_logic_vector(2 downto 0);
1402 
    signal m1s14GatedHSIZE         : std_logic_vector(2 downto 0);
1403 
    signal m1s15GatedHSIZE         : std_logic_vector(2 downto 0);
1404 
    signal m1s16GatedHSIZE         : std_logic_vector(2 downto 0);
1405 
    signal m0s0GatedHMASTLOCK      : std_logic;
1406 
    signal m0s1GatedHMASTLOCK      : std_logic;
1407 
    signal m0s2GatedHMASTLOCK      : std_logic;
1408 
    signal m0s3GatedHMASTLOCK      : std_logic;
1409 
    signal m0s4GatedHMASTLOCK      : std_logic;
1410 
    signal m0s5GatedHMASTLOCK      : std_logic;
1411 
    signal m0s6GatedHMASTLOCK      : std_logic;
1412 
    signal m0s7GatedHMASTLOCK      : std_logic;
1413 
    signal m0s8GatedHMASTLOCK      : std_logic;
1414 
    signal m0s9GatedHMASTLOCK      : std_logic;
1415 
    signal m0s10GatedHMASTLOCK     : std_logic;
1416 
    signal m0s11GatedHMASTLOCK     : std_logic;
1417 
    signal m0s12GatedHMASTLOCK     : std_logic;
1418 
    signal m0s13GatedHMASTLOCK     : std_logic;
1419 
    signal m0s14GatedHMASTLOCK     : std_logic;
1420 
    signal m0s15GatedHMASTLOCK     : std_logic;
1421 
    signal m0s16GatedHMASTLOCK     : std_logic;
1422 
    signal m1s0GatedHMASTLOCK      : std_logic;
1423 
    signal m1s1GatedHMASTLOCK      : std_logic;
1424 
    signal m1s2GatedHMASTLOCK      : std_logic;
1425 
    signal m1s3GatedHMASTLOCK      : std_logic;
1426 
    signal m1s4GatedHMASTLOCK      : std_logic;
1427 
    signal m1s5GatedHMASTLOCK      : std_logic;
1428 
    signal m1s6GatedHMASTLOCK      : std_logic;
1429 
    signal m1s7GatedHMASTLOCK      : std_logic;
1430 
    signal m1s8GatedHMASTLOCK      : std_logic;
1431 
    signal m1s9GatedHMASTLOCK      : std_logic;
1432 
    signal m1s10GatedHMASTLOCK     : std_logic;
1433 
    signal m1s11GatedHMASTLOCK     : std_logic;
1434 
    signal m1s12GatedHMASTLOCK     : std_logic;
1435 
    signal m1s13GatedHMASTLOCK     : std_logic;
1436 
    signal m1s14GatedHMASTLOCK     : std_logic;
1437 
    signal m1s15GatedHMASTLOCK     : std_logic;
1438 
    signal m1s16GatedHMASTLOCK     : std_logic;
1439 
    signal m0s0GatedHTRANS         : std_logic;
1440 
    signal m0s1GatedHTRANS         : std_logic;
1441 
    signal m0s2GatedHTRANS         : std_logic;
1442 
    signal m0s3GatedHTRANS         : std_logic;
1443 
    signal m0s4GatedHTRANS         : std_logic;
1444 
    signal m0s5GatedHTRANS         : std_logic;
1445 
    signal m0s6GatedHTRANS         : std_logic;
1446 
    signal m0s7GatedHTRANS         : std_logic;
1447 
    signal m0s8GatedHTRANS         : std_logic;
1448 
    signal m0s9GatedHTRANS         : std_logic;
1449 
    signal m0s10GatedHTRANS        : std_logic;
1450 
    signal m0s11GatedHTRANS        : std_logic;
1451 
    signal m0s12GatedHTRANS        : std_logic;
1452 
    signal m0s13GatedHTRANS        : std_logic;
1453 
    signal m0s14GatedHTRANS        : std_logic;
1454 
    signal m0s15GatedHTRANS        : std_logic;
1455 
    signal m0s16GatedHTRANS        : std_logic;
1456 
    signal m1s0GatedHTRANS         : std_logic;
1457 
    signal m1s1GatedHTRANS         : std_logic;
1458 
    signal m1s2GatedHTRANS         : std_logic;
1459 
    signal m1s3GatedHTRANS         : std_logic;
1460 
    signal m1s4GatedHTRANS         : std_logic;
1461 
    signal m1s5GatedHTRANS         : std_logic;
1462 
    signal m1s6GatedHTRANS         : std_logic;
1463 
    signal m1s7GatedHTRANS         : std_logic;
1464 
    signal m1s8GatedHTRANS         : std_logic;
1465 
    signal m1s9GatedHTRANS         : std_logic;
1466 
    signal m1s10GatedHTRANS        : std_logic;
1467 
    signal m1s11GatedHTRANS        : std_logic;
1468 
    signal m1s12GatedHTRANS        : std_logic;
1469 
    signal m1s13GatedHTRANS        : std_logic;
1470 
    signal m1s14GatedHTRANS        : std_logic;
1471 
    signal m1s15GatedHTRANS        : std_logic;
1472 
    signal m1s16GatedHTRANS        : std_logic;
1473 
    signal m0s0GatedHWRITE         : std_logic;
1474 
    signal m0s1GatedHWRITE         : std_logic;
1475 
    signal m0s2GatedHWRITE         : std_logic;
1476 
    signal m0s3GatedHWRITE         : std_logic;
1477 
    signal m0s4GatedHWRITE         : std_logic;
1478 
    signal m0s5GatedHWRITE         : std_logic;
1479 
    signal m0s6GatedHWRITE         : std_logic;
1480 
    signal m0s7GatedHWRITE         : std_logic;
1481 
    signal m0s8GatedHWRITE         : std_logic;
1482 
    signal m0s9GatedHWRITE         : std_logic;
1483 
    signal m0s10GatedHWRITE        : std_logic;
1484 
    signal m0s11GatedHWRITE        : std_logic;
1485 
    signal m0s12GatedHWRITE        : std_logic;
1486 
    signal m0s13GatedHWRITE        : std_logic;
1487 
    signal m0s14GatedHWRITE        : std_logic;
1488 
    signal m0s15GatedHWRITE        : std_logic;
1489 
    signal m0s16GatedHWRITE        : std_logic;
1490 
    signal m1s0GatedHWRITE         : std_logic;
1491 
    signal m1s1GatedHWRITE         : std_logic;
1492 
    signal m1s2GatedHWRITE         : std_logic;
1493 
    signal m1s3GatedHWRITE         : std_logic;
1494 
    signal m1s4GatedHWRITE         : std_logic;
1495 
    signal m1s5GatedHWRITE         : std_logic;
1496 
    signal m1s6GatedHWRITE         : std_logic;
1497 
    signal m1s7GatedHWRITE         : std_logic;
1498 
    signal m1s8GatedHWRITE         : std_logic;
1499 
    signal m1s9GatedHWRITE         : std_logic;
1500 
    signal m1s10GatedHWRITE        : std_logic;
1501 
    signal m1s11GatedHWRITE        : std_logic;
1502 
    signal m1s12GatedHWRITE        : std_logic;
1503 
    signal m1s13GatedHWRITE        : std_logic;
1504 
    signal m1s14GatedHWRITE        : std_logic;
1505 
    signal m1s15GatedHWRITE        : std_logic;
1506 
    signal m1s16GatedHWRITE        : std_logic;
1507 
    signal m0s0PrevDataSlaveReady  : std_logic;
1508 
    signal m0s1PrevDataSlaveReady  : std_logic;
1509 
    signal m0s2PrevDataSlaveReady  : std_logic;
1510 
    signal m0s3PrevDataSlaveReady  : std_logic;
1511 
    signal m0s4PrevDataSlaveReady  : std_logic;
1512 
    signal m0s5PrevDataSlaveReady  : std_logic;
1513 
    signal m0s6PrevDataSlaveReady  : std_logic;
1514 
    signal m0s7PrevDataSlaveReady  : std_logic;
1515 
    signal m0s8PrevDataSlaveReady  : std_logic;
1516 
    signal m0s9PrevDataSlaveReady  : std_logic;
1517 
    signal m0s10PrevDataSlaveReady : std_logic;
1518 
    signal m0s11PrevDataSlaveReady : std_logic;
1519 
    signal m0s12PrevDataSlaveReady : std_logic;
1520 
    signal m0s13PrevDataSlaveReady : std_logic;
1521 
    signal m0s14PrevDataSlaveReady : std_logic;
1522 
    signal m0s15PrevDataSlaveReady : std_logic;
1523 
    signal m0s16PrevDataSlaveReady : std_logic;
1524 
    signal m1s0PrevDataSlaveReady  : std_logic;
1525 
    signal m1s1PrevDataSlaveReady  : std_logic;
1526 
    signal m1s2PrevDataSlaveReady  : std_logic;
1527 
    signal m1s3PrevDataSlaveReady  : std_logic;
1528 
    signal m1s4PrevDataSlaveReady  : std_logic;
1529 
    signal m1s5PrevDataSlaveReady  : std_logic;
1530 
    signal m1s6PrevDataSlaveReady  : std_logic;
1531 
    signal m1s7PrevDataSlaveReady  : std_logic;
1532 
    signal m1s8PrevDataSlaveReady  : std_logic;
1533 
    signal m1s9PrevDataSlaveReady  : std_logic;
1534 
    signal m1s10PrevDataSlaveReady : std_logic;
1535 
    signal m1s11PrevDataSlaveReady : std_logic;
1536 
    signal m1s12PrevDataSlaveReady : std_logic;
1537 
    signal m1s13PrevDataSlaveReady : std_logic;
1538 
    signal m1s14PrevDataSlaveReady : std_logic;
1539 
    signal m1s15PrevDataSlaveReady : std_logic;
1540 
    signal m1s16PrevDataSlaveReady : std_logic;
1541 
    signal m2s0GatedHADDR          : std_logic_vector(31 downto 0);
1542 
    signal m2s1GatedHADDR          : std_logic_vector(31 downto 0);
1543 
    signal m2s2GatedHADDR          : std_logic_vector(31 downto 0);
1544 
    signal m2s3GatedHADDR          : std_logic_vector(31 downto 0);
1545 
    signal m2s4GatedHADDR          : std_logic_vector(31 downto 0);
1546 
    signal m2s5GatedHADDR          : std_logic_vector(31 downto 0);
1547 
    signal m2s6GatedHADDR          : std_logic_vector(31 downto 0);
1548 
    signal m2s7GatedHADDR          : std_logic_vector(31 downto 0);
1549 
    signal m2s8GatedHADDR          : std_logic_vector(31 downto 0);
1550 
    signal m2s9GatedHADDR          : std_logic_vector(31 downto 0);
1551 
    signal m2s10GatedHADDR         : std_logic_vector(31 downto 0);
1552 
    signal m2s11GatedHADDR         : std_logic_vector(31 downto 0);
1553 
    signal m2s12GatedHADDR         : std_logic_vector(31 downto 0);
1554 
    signal m2s13GatedHADDR         : std_logic_vector(31 downto 0);
1555 
    signal m2s14GatedHADDR         : std_logic_vector(31 downto 0);
1556 
    signal m2s15GatedHADDR         : std_logic_vector(31 downto 0);
1557 
    signal m2s16GatedHADDR         : std_logic_vector(31 downto 0);
1558 
    signal m3s0GatedHADDR          : std_logic_vector(31 downto 0);
1559 
    signal m3s1GatedHADDR          : std_logic_vector(31 downto 0);
1560 
    signal m3s2GatedHADDR          : std_logic_vector(31 downto 0);
1561 
    signal m3s3GatedHADDR          : std_logic_vector(31 downto 0);
1562 
    signal m3s4GatedHADDR          : std_logic_vector(31 downto 0);
1563 
    signal m3s5GatedHADDR          : std_logic_vector(31 downto 0);
1564 
    signal m3s6GatedHADDR          : std_logic_vector(31 downto 0);
1565 
    signal m3s7GatedHADDR          : std_logic_vector(31 downto 0);
1566 
    signal m3s8GatedHADDR          : std_logic_vector(31 downto 0);
1567 
    signal m3s9GatedHADDR          : std_logic_vector(31 downto 0);
1568 
    signal m3s10GatedHADDR         : std_logic_vector(31 downto 0);
1569 
    signal m3s11GatedHADDR         : std_logic_vector(31 downto 0);
1570 
    signal m3s12GatedHADDR         : std_logic_vector(31 downto 0);
1571 
    signal m3s13GatedHADDR         : std_logic_vector(31 downto 0);
1572 
    signal m3s14GatedHADDR         : std_logic_vector(31 downto 0);
1573 
    signal m3s15GatedHADDR         : std_logic_vector(31 downto 0);
1574 
    signal m3s16GatedHADDR         : std_logic_vector(31 downto 0);
1575 
    signal m2s0GatedHSIZE          : std_logic_vector(2 downto 0);
1576 
    signal m2s1GatedHSIZE          : std_logic_vector(2 downto 0);
1577 
    signal m2s2GatedHSIZE          : std_logic_vector(2 downto 0);
1578 
    signal m2s3GatedHSIZE          : std_logic_vector(2 downto 0);
1579 
    signal m2s4GatedHSIZE          : std_logic_vector(2 downto 0);
1580 
    signal m2s5GatedHSIZE          : std_logic_vector(2 downto 0);
1581 
    signal m2s6GatedHSIZE          : std_logic_vector(2 downto 0);
1582 
    signal m2s7GatedHSIZE          : std_logic_vector(2 downto 0);
1583 
    signal m2s8GatedHSIZE          : std_logic_vector(2 downto 0);
1584 
    signal m2s9GatedHSIZE          : std_logic_vector(2 downto 0);
1585 
    signal m2s10GatedHSIZE         : std_logic_vector(2 downto 0);
1586 
    signal m2s11GatedHSIZE         : std_logic_vector(2 downto 0);
1587 
    signal m2s12GatedHSIZE         : std_logic_vector(2 downto 0);
1588 
    signal m2s13GatedHSIZE         : std_logic_vector(2 downto 0);
1589 
    signal m2s14GatedHSIZE         : std_logic_vector(2 downto 0);
1590 
    signal m2s15GatedHSIZE         : std_logic_vector(2 downto 0);
1591 
    signal m2s16GatedHSIZE         : std_logic_vector(2 downto 0);
1592 
    signal m3s0GatedHSIZE          : std_logic_vector(2 downto 0);
1593 
    signal m3s1GatedHSIZE          : std_logic_vector(2 downto 0);
1594 
    signal m3s2GatedHSIZE          : std_logic_vector(2 downto 0);
1595 
    signal m3s3GatedHSIZE          : std_logic_vector(2 downto 0);
1596 
    signal m3s4GatedHSIZE          : std_logic_vector(2 downto 0);
1597 
    signal m3s5GatedHSIZE          : std_logic_vector(2 downto 0);
1598 
    signal m3s6GatedHSIZE          : std_logic_vector(2 downto 0);
1599 
    signal m3s7GatedHSIZE          : std_logic_vector(2 downto 0);
1600 
    signal m3s8GatedHSIZE          : std_logic_vector(2 downto 0);
1601 
    signal m3s9GatedHSIZE          : std_logic_vector(2 downto 0);
1602 
    signal m3s10GatedHSIZE         : std_logic_vector(2 downto 0);
1603 
    signal m3s11GatedHSIZE         : std_logic_vector(2 downto 0);
1604 
    signal m3s12GatedHSIZE         : std_logic_vector(2 downto 0);
1605 
    signal m3s13GatedHSIZE         : std_logic_vector(2 downto 0);
1606 
    signal m3s14GatedHSIZE         : std_logic_vector(2 downto 0);
1607 
    signal m3s15GatedHSIZE         : std_logic_vector(2 downto 0);
1608 
    signal m3s16GatedHSIZE         : std_logic_vector(2 downto 0);
1609 
    signal m2s0GatedHMASTLOCK      : std_logic;
1610 
    signal m2s1GatedHMASTLOCK      : std_logic;
1611 
    signal m2s2GatedHMASTLOCK      : std_logic;
1612 
    signal m2s3GatedHMASTLOCK      : std_logic;
1613 
    signal m2s4GatedHMASTLOCK      : std_logic;
1614 
    signal m2s5GatedHMASTLOCK      : std_logic;
1615 
    signal m2s6GatedHMASTLOCK      : std_logic;
1616 
    signal m2s7GatedHMASTLOCK      : std_logic;
1617 
    signal m2s8GatedHMASTLOCK      : std_logic;
1618 
    signal m2s9GatedHMASTLOCK      : std_logic;
1619 
    signal m2s10GatedHMASTLOCK     : std_logic;
1620 
    signal m2s11GatedHMASTLOCK     : std_logic;
1621 
    signal m2s12GatedHMASTLOCK     : std_logic;
1622 
    signal m2s13GatedHMASTLOCK     : std_logic;
1623 
    signal m2s14GatedHMASTLOCK     : std_logic;
1624 
    signal m2s15GatedHMASTLOCK     : std_logic;
1625 
    signal m2s16GatedHMASTLOCK     : std_logic;
1626 
    signal m3s0GatedHMASTLOCK      : std_logic;
1627 
    signal m3s1GatedHMASTLOCK      : std_logic;
1628 
    signal m3s2GatedHMASTLOCK      : std_logic;
1629 
    signal m3s3GatedHMASTLOCK      : std_logic;
1630 
    signal m3s4GatedHMASTLOCK      : std_logic;
1631 
    signal m3s5GatedHMASTLOCK      : std_logic;
1632 
    signal m3s6GatedHMASTLOCK      : std_logic;
1633 
    signal m3s7GatedHMASTLOCK      : std_logic;
1634 
    signal m3s8GatedHMASTLOCK      : std_logic;
1635 
    signal m3s9GatedHMASTLOCK      : std_logic;
1636 
    signal m3s10GatedHMASTLOCK     : std_logic;
1637 
    signal m3s11GatedHMASTLOCK     : std_logic;
1638 
    signal m3s12GatedHMASTLOCK     : std_logic;
1639 
    signal m3s13GatedHMASTLOCK     : std_logic;
1640 
    signal m3s14GatedHMASTLOCK     : std_logic;
1641 
    signal m3s15GatedHMASTLOCK     : std_logic;
1642 
    signal m3s16GatedHMASTLOCK     : std_logic;
1643 
    signal m2s0GatedHTRANS         : std_logic;
1644 
    signal m2s1GatedHTRANS         : std_logic;
1645 
    signal m2s2GatedHTRANS         : std_logic;
1646 
    signal m2s3GatedHTRANS         : std_logic;
1647 
    signal m2s4GatedHTRANS         : std_logic;
1648 
    signal m2s5GatedHTRANS         : std_logic;
1649 
    signal m2s6GatedHTRANS         : std_logic;
1650 
    signal m2s7GatedHTRANS         : std_logic;
1651 
    signal m2s8GatedHTRANS         : std_logic;
1652 
    signal m2s9GatedHTRANS         : std_logic;
1653 
    signal m2s10GatedHTRANS        : std_logic;
1654 
    signal m2s11GatedHTRANS        : std_logic;
1655 
    signal m2s12GatedHTRANS        : std_logic;
1656 
    signal m2s13GatedHTRANS        : std_logic;
1657 
    signal m2s14GatedHTRANS        : std_logic;
1658 
    signal m2s15GatedHTRANS        : std_logic;
1659 
    signal m2s16GatedHTRANS        : std_logic;
1660 
    signal m3s0GatedHTRANS         : std_logic;
1661 
    signal m3s1GatedHTRANS         : std_logic;
1662 
    signal m3s2GatedHTRANS         : std_logic;
1663 
    signal m3s3GatedHTRANS         : std_logic;
1664 
    signal m3s4GatedHTRANS         : std_logic;
1665 
    signal m3s5GatedHTRANS         : std_logic;
1666 
    signal m3s6GatedHTRANS         : std_logic;
1667 
    signal m3s7GatedHTRANS         : std_logic;
1668 
    signal m3s8GatedHTRANS         : std_logic;
1669 
    signal m3s9GatedHTRANS         : std_logic;
1670 
    signal m3s10GatedHTRANS        : std_logic;
1671 
    signal m3s11GatedHTRANS        : std_logic;
1672 
    signal m3s12GatedHTRANS        : std_logic;
1673 
    signal m3s13GatedHTRANS        : std_logic;
1674 
    signal m3s14GatedHTRANS        : std_logic;
1675 
    signal m3s15GatedHTRANS        : std_logic;
1676 
    signal m3s16GatedHTRANS        : std_logic;
1677 
    signal m2s0GatedHWRITE         : std_logic;
1678 
    signal m2s1GatedHWRITE         : std_logic;
1679 
    signal m2s2GatedHWRITE         : std_logic;
1680 
    signal m2s3GatedHWRITE         : std_logic;
1681 
    signal m2s4GatedHWRITE         : std_logic;
1682 
    signal m2s5GatedHWRITE         : std_logic;
1683 
    signal m2s6GatedHWRITE         : std_logic;
1684 
    signal m2s7GatedHWRITE         : std_logic;
1685 
    signal m2s8GatedHWRITE         : std_logic;
1686 
    signal m2s9GatedHWRITE         : std_logic;
1687 
    signal m2s10GatedHWRITE        : std_logic;
1688 
    signal m2s11GatedHWRITE        : std_logic;
1689 
    signal m2s12GatedHWRITE        : std_logic;
1690 
    signal m2s13GatedHWRITE        : std_logic;
1691 
    signal m2s14GatedHWRITE        : std_logic;
1692 
    signal m2s15GatedHWRITE        : std_logic;
1693 
    signal m2s16GatedHWRITE        : std_logic;
1694 
    signal m3s0GatedHWRITE         : std_logic;
1695 
    signal m3s1GatedHWRITE         : std_logic;
1696 
    signal m3s2GatedHWRITE         : std_logic;
1697 
    signal m3s3GatedHWRITE         : std_logic;
1698 
    signal m3s4GatedHWRITE         : std_logic;
1699 
    signal m3s5GatedHWRITE         : std_logic;
1700 
    signal m3s6GatedHWRITE         : std_logic;
1701 
    signal m3s7GatedHWRITE         : std_logic;
1702 
    signal m3s8GatedHWRITE         : std_logic;
1703 
    signal m3s9GatedHWRITE         : std_logic;
1704 
    signal m3s10GatedHWRITE        : std_logic;
1705 
    signal m3s11GatedHWRITE        : std_logic;
1706 
    signal m3s12GatedHWRITE        : std_logic;
1707 
    signal m3s13GatedHWRITE        : std_logic;
1708 
    signal m3s14GatedHWRITE        : std_logic;
1709 
    signal m3s15GatedHWRITE        : std_logic;
1710 
    signal m3s16GatedHWRITE        : std_logic;
1711 
    signal m2s0PrevDataSlaveReady  : std_logic;
1712 
    signal m2s1PrevDataSlaveReady  : std_logic;
1713 
    signal m2s2PrevDataSlaveReady  : std_logic;
1714 
    signal m2s3PrevDataSlaveReady  : std_logic;
1715 
    signal m2s4PrevDataSlaveReady  : std_logic;
1716 
    signal m2s5PrevDataSlaveReady  : std_logic;
1717 
    signal m2s6PrevDataSlaveReady  : std_logic;
1718 
    signal m2s7PrevDataSlaveReady  : std_logic;
1719 
    signal m2s8PrevDataSlaveReady  : std_logic;
1720 
    signal m2s9PrevDataSlaveReady  : std_logic;
1721 
    signal m2s10PrevDataSlaveReady : std_logic;
1722 
    signal m2s11PrevDataSlaveReady : std_logic;
1723 
    signal m2s12PrevDataSlaveReady : std_logic;
1724 
    signal m2s13PrevDataSlaveReady : std_logic;
1725 
    signal m2s14PrevDataSlaveReady : std_logic;
1726 
    signal m2s15PrevDataSlaveReady : std_logic;
1727 
    signal m2s16PrevDataSlaveReady : std_logic;
1728 
    signal m3s0PrevDataSlaveReady  : std_logic;
1729 
    signal m3s1PrevDataSlaveReady  : std_logic;
1730 
    signal m3s2PrevDataSlaveReady  : std_logic;
1731 
    signal m3s3PrevDataSlaveReady  : std_logic;
1732 
    signal m3s4PrevDataSlaveReady  : std_logic;
1733 
    signal m3s5PrevDataSlaveReady  : std_logic;
1734 
    signal m3s6PrevDataSlaveReady  : std_logic;
1735 
    signal m3s7PrevDataSlaveReady  : std_logic;
1736 
    signal m3s8PrevDataSlaveReady  : std_logic;
1737 
    signal m3s9PrevDataSlaveReady  : std_logic;
1738 
    signal m3s10PrevDataSlaveReady : std_logic;
1739 
    signal m3s11PrevDataSlaveReady : std_logic;
1740 
    signal m3s12PrevDataSlaveReady : std_logic;
1741 
    signal m3s13PrevDataSlaveReady : std_logic;
1742 
    signal m3s14PrevDataSlaveReady : std_logic;
1743 
    signal m3s15PrevDataSlaveReady : std_logic;
1744 
    signal m3s16PrevDataSlaveReady : std_logic;
1745 
    signal HREADY_M0_pre           : std_logic;
1746 
    signal HREADY_M1_pre           : std_logic;
1747 
    signal HREADY_M2_pre           : std_logic;
1748 
    signal HREADY_M3_pre           : std_logic;
1749 
 
1750 
    -- X-HDL generated signals
1751 
 
1752 
    signal xhdl1218 : std_logic_vector(16 downto 0);
1753 
    signal xhdl1219 : std_logic_vector(16 downto 0);
1754 
    signal xhdl1220 : std_logic_vector(16 downto 0);
1755 
    signal xhdl1221 : std_logic_vector(16 downto 0);
1756 
    signal xhdl1222 : std_logic_vector(16 downto 0);
1757 
    signal xhdl1223 : std_logic_vector(16 downto 0);
1758 
    signal xhdl1224 : std_logic_vector(16 downto 0);
1759 
    signal xhdl1225 : std_logic_vector(16 downto 0);
1760 
    signal xhdl1226 : std_logic_vector(16 downto 0);
1761 
    signal xhdl1227 : std_logic_vector(16 downto 0);
1762 
 
1763 
    signal hdl1218  : std_logic_vector(16 downto 0);
1764 
    signal hdl1219  : std_logic_vector(16 downto 0);
1765 
    signal hdl1220  : std_logic_vector(16 downto 0);
1766 
    signal hdl1221  : std_logic_vector(16 downto 0);
1767 
    signal hdl1222  : std_logic_vector(16 downto 0);
1768 
    signal hdl1223  : std_logic_vector(16 downto 0);
1769 
    signal hdl1224  : std_logic_vector(16 downto 0);
1770 
    signal hdl1225  : std_logic_vector(16 downto 0);
1771 
    signal hdl1226  : std_logic_vector(16 downto 0);
1772 
    signal hdl1227  : std_logic_vector(16 downto 0);
1773 
 
1774 
    signal xhdl1228 : std_logic_vector(3 downto 0);
1775 
    signal xhdl1229 : std_logic_vector(3 downto 0);
1776 
    signal xhdl1230 : std_logic_vector(3 downto 0);
1777 
    signal xhdl1231 : std_logic_vector(3 downto 0);
1778 
    signal xhdl1232 : std_logic_vector(3 downto 0);
1779 
    signal xhdl1233 : std_logic_vector(3 downto 0);
1780 
    signal xhdl1234 : std_logic_vector(3 downto 0);
1781 
    signal xhdl1235 : std_logic_vector(3 downto 0);
1782 
    signal xhdl1236 : std_logic_vector(3 downto 0);
1783 
    signal xhdl1237 : std_logic_vector(3 downto 0);
1784 
    signal xhdl1238 : std_logic_vector(3 downto 0);
1785 
    signal xhdl1239 : std_logic_vector(3 downto 0);
1786 
    signal xhdl1240 : std_logic_vector(3 downto 0);
1787 
    signal xhdl1241 : std_logic_vector(3 downto 0);
1788 
    signal xhdl1242 : std_logic_vector(3 downto 0);
1789 
    signal xhdl1243 : std_logic_vector(3 downto 0);
1790 
    signal xhdl1244 : std_logic_vector(3 downto 0);
1791 
    signal xhdl1245 : std_logic_vector(3 downto 0);
1792 
    signal xhdl1246 : std_logic_vector(3 downto 0);
1793 
    signal xhdl1247 : std_logic_vector(3 downto 0);
1794 
    signal xhdl1248 : std_logic_vector(3 downto 0);
1795 
    signal xhdl1249 : std_logic_vector(3 downto 0);
1796 
    signal xhdl1250 : std_logic_vector(3 downto 0);
1797 
    signal xhdl1251 : std_logic_vector(3 downto 0);
1798 
    signal xhdl1252 : std_logic_vector(3 downto 0);
1799 
    signal xhdl1253 : std_logic_vector(3 downto 0);
1800 
    signal xhdl1254 : std_logic_vector(3 downto 0);
1801 
    signal xhdl1255 : std_logic_vector(3 downto 0);
1802 
    signal xhdl1256 : std_logic_vector(3 downto 0);
1803 
    signal xhdl1257 : std_logic_vector(3 downto 0);
1804 
    signal xhdl1258 : std_logic_vector(3 downto 0);
1805 
    signal xhdl1259 : std_logic_vector(3 downto 0);
1806 
    signal xhdl1260 : std_logic_vector(3 downto 0);
1807 
    signal xhdl1261 : std_logic_vector(3 downto 0);
1808 
    signal xhdl1262 : std_logic_vector(3 downto 0);
1809 
    signal xhdl1263 : std_logic_vector(3 downto 0);
1810 
    signal xhdl1264 : std_logic_vector(3 downto 0);
1811 
    signal xhdl1265 : std_logic_vector(3 downto 0);
1812 
    signal xhdl1266 : std_logic_vector(3 downto 0);
1813 
    signal xhdl1267 : std_logic_vector(3 downto 0);
1814 
    signal xhdl1268 : std_logic_vector(3 downto 0);
1815 
    signal xhdl1269 : std_logic_vector(3 downto 0);
1816 
    signal xhdl1270 : std_logic_vector(3 downto 0);
1817 
    signal xhdl1271 : std_logic_vector(3 downto 0);
1818 
    signal xhdl1272 : std_logic_vector(3 downto 0);
1819 
    signal xhdl1273 : std_logic_vector(3 downto 0);
1820 
    signal xhdl1274 : std_logic_vector(3 downto 0);
1821 
    signal xhdl1275 : std_logic_vector(3 downto 0);
1822 
    signal xhdl1276 : std_logic_vector(3 downto 0);
1823 
    signal xhdl1277 : std_logic_vector(3 downto 0);
1824 
    signal xhdl1278 : std_logic_vector(3 downto 0);
1825 
    signal xhdl1279 : std_logic_vector(3 downto 0);
1826 
    signal xhdl1280 : std_logic_vector(3 downto 0);
1827 
    signal xhdl1281 : std_logic_vector(3 downto 0);
1828 
    signal xhdl1282 : std_logic_vector(3 downto 0);
1829 
    signal xhdl1283 : std_logic_vector(3 downto 0);
1830 
    signal xhdl1284 : std_logic_vector(3 downto 0);
1831 
    signal xhdl1285 : std_logic_vector(3 downto 0);
1832 
    signal xhdl1286 : std_logic_vector(3 downto 0);
1833 
    signal xhdl1287 : std_logic_vector(3 downto 0);
1834 
    signal xhdl1288 : std_logic_vector(3 downto 0);
1835 
    signal xhdl1289 : std_logic_vector(3 downto 0);
1836 
    signal xhdl1290 : std_logic_vector(3 downto 0);
1837 
    signal xhdl1291 : std_logic_vector(3 downto 0);
1838 
    signal xhdl1292 : std_logic_vector(3 downto 0);
1839 
    signal xhdl1293 : std_logic_vector(3 downto 0);
1840 
    signal xhdl1294 : std_logic_vector(3 downto 0);
1841 
    signal xhdl1295 : std_logic_vector(3 downto 0);
1842 
    signal xhdl1296 : std_logic_vector(3 downto 0);
1843 
    signal xhdl1297 : std_logic_vector(3 downto 0);
1844 
    signal xhdl1298 : std_logic_vector(3 downto 0);
1845 
    signal xhdl1299 : std_logic_vector(3 downto 0);
1846 
    signal xhdl1300 : std_logic_vector(3 downto 0);
1847 
    signal xhdl1301 : std_logic_vector(3 downto 0);
1848 
    signal xhdl1302 : std_logic_vector(3 downto 0);
1849 
    signal xhdl1303 : std_logic_vector(3 downto 0);
1850 
    signal xhdl1304 : std_logic_vector(3 downto 0);
1851 
    signal xhdl1305 : std_logic_vector(3 downto 0);
1852 
    signal xhdl1306 : std_logic_vector(3 downto 0);
1853 
    signal xhdl1307 : std_logic_vector(3 downto 0);
1854 
    signal xhdl1308 : std_logic_vector(3 downto 0);
1855 
    signal xhdl1309 : std_logic_vector(3 downto 0);
1856 
    signal xhdl1310 : std_logic_vector(3 downto 0);
1857 
    signal xhdl1311 : std_logic_vector(3 downto 0);
1858 
    signal xhdl1312 : std_logic_vector(3 downto 0);
1859 
    signal xhdl1313 : std_logic_vector(3 downto 0);
1860 
    signal xhdl1314 : std_logic_vector(3 downto 0);
1861 
    signal xhdl1315 : std_logic_vector(3 downto 0);
1862 
    signal xhdl1316 : std_logic_vector(3 downto 0);
1863 
    signal xhdl1317 : std_logic_vector(3 downto 0);
1864 
    signal xhdl1318 : std_logic_vector(3 downto 0);
1865 
    signal xhdl1319 : std_logic_vector(3 downto 0);
1866 
    signal xhdl1320 : std_logic_vector(3 downto 0);
1867 
    signal xhdl1321 : std_logic_vector(3 downto 0);
1868 
    signal xhdl1322 : std_logic_vector(3 downto 0);
1869 
    signal xhdl1323 : std_logic_vector(3 downto 0);
1870 
    signal xhdl1324 : std_logic_vector(3 downto 0);
1871 
    signal xhdl1325 : std_logic_vector(3 downto 0);
1872 
    signal xhdl1326 : std_logic_vector(3 downto 0);
1873 
    signal xhdl1327 : std_logic_vector(3 downto 0);
1874 
    signal xhdl1328 : std_logic_vector(3 downto 0);
1875 
    signal xhdl1329 : std_logic_vector(3 downto 0);
1876 
    --signal xhdl1330 : std_logic_vector(1 downto 0);
1877 
    --signal xhdl1331 : std_logic_vector(1 downto 0);
1878 
    --signal xhdl1332 : std_logic_vector(1 downto 0);
1879 
    --signal xhdl1333 : std_logic_vector(1 downto 0);
1880 
    --signal xhdl1334 : std_logic_vector(1 downto 0);
1881 
    --signal xhdl1335 : std_logic_vector(1 downto 0);
1882 
 
1883 
    -- Declare intermediate signals for referenced outputs
1884 
    signal HRESP_M0_xhdl55         : std_logic;
1885 
    signal HRDATA_M0_xhdl34        : std_logic_vector(31 downto 0);
1886 
    signal HREADY_M0_xhdl36        : std_logic;
1887 
    signal HRESP_M1_xhdl56         : std_logic;
1888 
    signal HRDATA_M1_xhdl35        : std_logic_vector(31 downto 0);
1889 
    signal HREADY_M1_xhdl37        : std_logic;
1890 
    signal HRESP_M2_xhdl55         : std_logic;
1891 
    signal HRDATA_M2_xhdl34        : std_logic_vector(31 downto 0);
1892 
    signal HREADY_M2_xhdl36        : std_logic;
1893 
    signal HRESP_M3_xhdl56         : std_logic;
1894 
    signal HRDATA_M3_xhdl35        : std_logic_vector(31 downto 0);
1895 
    signal HREADY_M3_xhdl37        : std_logic;
1896 
    signal HSEL_S0_xhdl57          : std_logic;
1897 
    signal HADDR_S0_xhdl0          : std_logic_vector(31 downto 0);
1898 
    signal HSIZE_S0_xhdl74         : std_logic_vector(2 downto 0);
1899 
    signal HTRANS_S0_xhdl91        : std_logic;
1900 
    signal HWRITE_S0_xhdl125       : std_logic;
1901 
    signal HWDATA_S0_xhdl108       : std_logic_vector(31 downto 0);
1902 
    signal HREADY_S0_xhdl38        : std_logic;
1903 
    signal HMASTLOCK_S0_xhdl17     : std_logic;
1904 
    signal HSEL_S1_xhdl58          : std_logic;
1905 
    signal HADDR_S1_xhdl1          : std_logic_vector(31 downto 0);
1906 
    signal HSIZE_S1_xhdl75         : std_logic_vector(2 downto 0);
1907 
    signal HTRANS_S1_xhdl92        : std_logic;
1908 
    signal HWRITE_S1_xhdl126       : std_logic;
1909 
    signal HWDATA_S1_xhdl109       : std_logic_vector(31 downto 0);
1910 
    signal HREADY_S1_xhdl39        : std_logic;
1911 
    signal HMASTLOCK_S1_xhdl18     : std_logic;
1912 
    signal HSEL_S2_xhdl65          : std_logic;
1913 
    signal HADDR_S2_xhdl8          : std_logic_vector(31 downto 0);
1914 
    signal HSIZE_S2_xhdl82         : std_logic_vector(2 downto 0);
1915 
    signal HTRANS_S2_xhdl99        : std_logic;
1916 
    signal HWRITE_S2_xhdl133       : std_logic;
1917 
    signal HWDATA_S2_xhdl116       : std_logic_vector(31 downto 0);
1918 
    signal HREADY_S2_xhdl46        : std_logic;
1919 
    signal HMASTLOCK_S2_xhdl25     : std_logic;
1920 
    signal HSEL_S3_xhdl66          : std_logic;
1921 
    signal HADDR_S3_xhdl9          : std_logic_vector(31 downto 0);
1922 
    signal HSIZE_S3_xhdl83         : std_logic_vector(2 downto 0);
1923 
    signal HTRANS_S3_xhdl100       : std_logic;
1924 
    signal HWRITE_S3_xhdl134       : std_logic;
1925 
    signal HWDATA_S3_xhdl117       : std_logic_vector(31 downto 0);
1926 
    signal HREADY_S3_xhdl47        : std_logic;
1927 
    signal HMASTLOCK_S3_xhdl26     : std_logic;
1928 
    signal HSEL_S4_xhdl67          : std_logic;
1929 
    signal HADDR_S4_xhdl10         : std_logic_vector(31 downto 0);
1930 
    signal HSIZE_S4_xhdl84         : std_logic_vector(2 downto 0);
1931 
    signal HTRANS_S4_xhdl101       : std_logic;
1932 
    signal HWRITE_S4_xhdl135       : std_logic;
1933 
    signal HWDATA_S4_xhdl118       : std_logic_vector(31 downto 0);
1934 
    signal HREADY_S4_xhdl48        : std_logic;
1935 
    signal HMASTLOCK_S4_xhdl27     : std_logic;
1936 
    signal HSEL_S5_xhdl68          : std_logic;
1937 
    signal HADDR_S5_xhdl11         : std_logic_vector(31 downto 0);
1938 
    signal HSIZE_S5_xhdl85         : std_logic_vector(2 downto 0);
1939 
    signal HTRANS_S5_xhdl102       : std_logic;
1940 
    signal HWRITE_S5_xhdl136       : std_logic;
1941 
    signal HWDATA_S5_xhdl119       : std_logic_vector(31 downto 0);
1942 
    signal HREADY_S5_xhdl49        : std_logic;
1943 
    signal HMASTLOCK_S5_xhdl28     : std_logic;
1944 
    signal HSEL_S6_xhdl69          : std_logic;
1945 
    signal HADDR_S6_xhdl12         : std_logic_vector(31 downto 0);
1946 
    signal HSIZE_S6_xhdl86         : std_logic_vector(2 downto 0);
1947 
    signal HTRANS_S6_xhdl103       : std_logic;
1948 
    signal HWRITE_S6_xhdl137       : std_logic;
1949 
    signal HWDATA_S6_xhdl120       : std_logic_vector(31 downto 0);
1950 
    signal HREADY_S6_xhdl50        : std_logic;
1951 
    signal HMASTLOCK_S6_xhdl29     : std_logic;
1952 
    signal HSEL_S7_xhdl70          : std_logic;
1953 
    signal HADDR_S7_xhdl13         : std_logic_vector(31 downto 0);
1954 
    signal HSIZE_S7_xhdl87         : std_logic_vector(2 downto 0);
1955 
    signal HTRANS_S7_xhdl104       : std_logic;
1956 
    signal HWRITE_S7_xhdl138       : std_logic;
1957 
    signal HWDATA_S7_xhdl121       : std_logic_vector(31 downto 0);
1958 
    signal HREADY_S7_xhdl51        : std_logic;
1959 
    signal HMASTLOCK_S7_xhdl30     : std_logic;
1960 
    signal HSEL_S8_xhdl71          : std_logic;
1961 
    signal HADDR_S8_xhdl14         : std_logic_vector(31 downto 0);
1962 
    signal HSIZE_S8_xhdl88         : std_logic_vector(2 downto 0);
1963 
    signal HTRANS_S8_xhdl105       : std_logic;
1964 
    signal HWRITE_S8_xhdl139       : std_logic;
1965 
    signal HWDATA_S8_xhdl122       : std_logic_vector(31 downto 0);
1966 
    signal HREADY_S8_xhdl52        : std_logic;
1967 
    signal HMASTLOCK_S8_xhdl31     : std_logic;
1968 
    signal HSEL_S9_xhdl72          : std_logic;
1969 
    signal HADDR_S9_xhdl15         : std_logic_vector(31 downto 0);
1970 
    signal HSIZE_S9_xhdl89         : std_logic_vector(2 downto 0);
1971 
    signal HTRANS_S9_xhdl106       : std_logic;
1972 
    signal HWRITE_S9_xhdl140       : std_logic;
1973 
    signal HWDATA_S9_xhdl123       : std_logic_vector(31 downto 0);
1974 
    signal HREADY_S9_xhdl53        : std_logic;
1975 
    signal HMASTLOCK_S9_xhdl32     : std_logic;
1976 
    signal HSEL_S10_xhdl59         : std_logic;
1977 
    signal HADDR_S10_xhdl2         : std_logic_vector(31 downto 0);
1978 
    signal HSIZE_S10_xhdl76        : std_logic_vector(2 downto 0);
1979 
    signal HTRANS_S10_xhdl93       : std_logic;
1980 
    signal HWRITE_S10_xhdl127      : std_logic;
1981 
    signal HWDATA_S10_xhdl110      : std_logic_vector(31 downto 0);
1982 
    signal HREADY_S10_xhdl40       : std_logic;
1983 
    signal HMASTLOCK_S10_xhdl19    : std_logic;
1984 
    signal HSEL_S11_xhdl60         : std_logic;
1985 
    signal HADDR_S11_xhdl3         : std_logic_vector(31 downto 0);
1986 
    signal HSIZE_S11_xhdl77        : std_logic_vector(2 downto 0);
1987 
    signal HTRANS_S11_xhdl94       : std_logic;
1988 
    signal HWRITE_S11_xhdl128      : std_logic;
1989 
    signal HWDATA_S11_xhdl111      : std_logic_vector(31 downto 0);
1990 
    signal HREADY_S11_xhdl41       : std_logic;
1991 
    signal HMASTLOCK_S11_xhdl20    : std_logic;
1992 
    signal HSEL_S12_xhdl61         : std_logic;
1993 
    signal HADDR_S12_xhdl4         : std_logic_vector(31 downto 0);
1994 
    signal HSIZE_S12_xhdl78        : std_logic_vector(2 downto 0);
1995 
    signal HTRANS_S12_xhdl95       : std_logic;
1996 
    signal HWRITE_S12_xhdl129      : std_logic;
1997 
    signal HWDATA_S12_xhdl112      : std_logic_vector(31 downto 0);
1998 
    signal HREADY_S12_xhdl42       : std_logic;
1999 
    signal HMASTLOCK_S12_xhdl21    : std_logic;
2000 
    signal HSEL_S13_xhdl62         : std_logic;
2001 
    signal HADDR_S13_xhdl5         : std_logic_vector(31 downto 0);
2002 
    signal HSIZE_S13_xhdl79        : std_logic_vector(2 downto 0);
2003 
    signal HTRANS_S13_xhdl96       : std_logic;
2004 
    signal HWRITE_S13_xhdl130      : std_logic;
2005 
    signal HWDATA_S13_xhdl113      : std_logic_vector(31 downto 0);
2006 
    signal HREADY_S13_xhdl43       : std_logic;
2007 
    signal HMASTLOCK_S13_xhdl22    : std_logic;
2008 
    signal HSEL_S14_xhdl63         : std_logic;
2009 
    signal HADDR_S14_xhdl6         : std_logic_vector(31 downto 0);
2010 
    signal HSIZE_S14_xhdl80        : std_logic_vector(2 downto 0);
2011 
    signal HTRANS_S14_xhdl97       : std_logic;
2012 
    signal HWRITE_S14_xhdl131      : std_logic;
2013 
    signal HWDATA_S14_xhdl114      : std_logic_vector(31 downto 0);
2014 
    signal HREADY_S14_xhdl44       : std_logic;
2015 
    signal HMASTLOCK_S14_xhdl23    : std_logic;
2016 
    signal HSEL_S15_xhdl64         : std_logic;
2017 
    signal HADDR_S15_xhdl7         : std_logic_vector(31 downto 0);
2018 
    signal HSIZE_S15_xhdl81        : std_logic_vector(2 downto 0);
2019 
    signal HTRANS_S15_xhdl98       : std_logic;
2020 
    signal HWRITE_S15_xhdl132      : std_logic;
2021 
    signal HWDATA_S15_xhdl115      : std_logic_vector(31 downto 0);
2022 
    signal HREADY_S15_xhdl45       : std_logic;
2023 
    signal HMASTLOCK_S15_xhdl24    : std_logic;
2024 
    signal HSEL_S16_xhdl73         : std_logic;
2025 
    signal HADDR_S16_xhdl16        : std_logic_vector(31 downto 0);
2026 
    signal HSIZE_S16_xhdl90        : std_logic_vector(2 downto 0);
2027 
    signal HTRANS_S16_xhdl107      : std_logic;
2028 
    signal HWRITE_S16_xhdl141      : std_logic;
2029 
    signal HWDATA_S16_xhdl124      : std_logic_vector(31 downto 0);
2030 
    signal HREADY_S16_xhdl54       : std_logic;
2031 
    signal HMASTLOCK_S16_xhdl33    : std_logic;
2032 
begin
2033 
    -- Drive referenced outputs
2034 
    HRESP_M0 <= HRESP_M0_xhdl55;
2035 
    HRDATA_M0 <= HRDATA_M0_xhdl34;
2036 
    HREADY_M0 <= HREADY_M0_xhdl36;
2037 
    HRESP_M1 <= HRESP_M1_xhdl56;
2038 
    HRDATA_M1 <= HRDATA_M1_xhdl35;
2039 
    HREADY_M1 <= HREADY_M1_xhdl37;
2040 
    HRESP_M2 <= HRESP_M2_xhdl55;
2041 
    HRDATA_M2 <= HRDATA_M2_xhdl34;
2042 
    HREADY_M2 <= HREADY_M2_xhdl36;
2043 
    HRESP_M3 <= HRESP_M3_xhdl56;
2044 
    HRDATA_M3 <= HRDATA_M3_xhdl35;
2045 
    HREADY_M3 <= HREADY_M3_xhdl37;
2046 
    HSEL_S0 <= HSEL_S0_xhdl57;
2047 
    HADDR_S0 <= HADDR_S0_xhdl0;
2048 
    HSIZE_S0 <= HSIZE_S0_xhdl74;
2049 
    HTRANS_S0 <= HTRANS_S0_xhdl91;
2050 
    HWRITE_S0 <= HWRITE_S0_xhdl125;
2051 
    HWDATA_S0 <= HWDATA_S0_xhdl108;
2052 
    HREADY_S0 <= HREADY_S0_xhdl38;
2053 
    HMASTLOCK_S0 <= HMASTLOCK_S0_xhdl17;
2054 
    HSEL_S1 <= HSEL_S1_xhdl58;
2055 
    HADDR_S1 <= HADDR_S1_xhdl1;
2056 
    HSIZE_S1 <= HSIZE_S1_xhdl75;
2057 
    HTRANS_S1 <= HTRANS_S1_xhdl92;
2058 
    HWRITE_S1 <= HWRITE_S1_xhdl126;
2059 
    HWDATA_S1 <= HWDATA_S1_xhdl109;
2060 
    HREADY_S1 <= HREADY_S1_xhdl39;
2061 
    HMASTLOCK_S1 <= HMASTLOCK_S1_xhdl18;
2062 
    HSEL_S2 <= HSEL_S2_xhdl65;
2063 
    HADDR_S2 <= HADDR_S2_xhdl8;
2064 
    HSIZE_S2 <= HSIZE_S2_xhdl82;
2065 
    HTRANS_S2 <= HTRANS_S2_xhdl99;
2066 
    HWRITE_S2 <= HWRITE_S2_xhdl133;
2067 
    HWDATA_S2 <= HWDATA_S2_xhdl116;
2068 
    HREADY_S2 <= HREADY_S2_xhdl46;
2069 
    HMASTLOCK_S2 <= HMASTLOCK_S2_xhdl25;
2070 
    HSEL_S3 <= HSEL_S3_xhdl66;
2071 
    HADDR_S3 <= HADDR_S3_xhdl9;
2072 
    HSIZE_S3 <= HSIZE_S3_xhdl83;
2073 
    HTRANS_S3 <= HTRANS_S3_xhdl100;
2074 
    HWRITE_S3 <= HWRITE_S3_xhdl134;
2075 
    HWDATA_S3 <= HWDATA_S3_xhdl117;
2076 
    HREADY_S3 <= HREADY_S3_xhdl47;
2077 
    HMASTLOCK_S3 <= HMASTLOCK_S3_xhdl26;
2078 
    HSEL_S4 <= HSEL_S4_xhdl67;
2079 
    HADDR_S4 <= HADDR_S4_xhdl10;
2080 
    HSIZE_S4 <= HSIZE_S4_xhdl84;
2081 
    HTRANS_S4 <= HTRANS_S4_xhdl101;
2082 
    HWRITE_S4 <= HWRITE_S4_xhdl135;
2083 
    HWDATA_S4 <= HWDATA_S4_xhdl118;
2084 
    HREADY_S4 <= HREADY_S4_xhdl48;
2085 
    HMASTLOCK_S4 <= HMASTLOCK_S4_xhdl27;
2086 
    HSEL_S5 <= HSEL_S5_xhdl68;
2087 
    HADDR_S5 <= HADDR_S5_xhdl11;
2088 
    HSIZE_S5 <= HSIZE_S5_xhdl85;
2089 
    HTRANS_S5 <= HTRANS_S5_xhdl102;
2090 
    HWRITE_S5 <= HWRITE_S5_xhdl136;
2091 
    HWDATA_S5 <= HWDATA_S5_xhdl119;
2092 
    HREADY_S5 <= HREADY_S5_xhdl49;
2093 
    HMASTLOCK_S5 <= HMASTLOCK_S5_xhdl28;
2094 
    HSEL_S6 <= HSEL_S6_xhdl69;
2095 
    HADDR_S6 <= HADDR_S6_xhdl12;
2096 
    HSIZE_S6 <= HSIZE_S6_xhdl86;
2097 
    HTRANS_S6 <= HTRANS_S6_xhdl103;
2098 
    HWRITE_S6 <= HWRITE_S6_xhdl137;
2099 
    HWDATA_S6 <= HWDATA_S6_xhdl120;
2100 
    HREADY_S6 <= HREADY_S6_xhdl50;
2101 
    HMASTLOCK_S6 <= HMASTLOCK_S6_xhdl29;
2102 
    HSEL_S7 <= HSEL_S7_xhdl70;
2103 
    HADDR_S7 <= HADDR_S7_xhdl13;
2104 
    HSIZE_S7 <= HSIZE_S7_xhdl87;
2105 
    HTRANS_S7 <= HTRANS_S7_xhdl104;
2106 
    HWRITE_S7 <= HWRITE_S7_xhdl138;
2107 
    HWDATA_S7 <= HWDATA_S7_xhdl121;
2108 
    HREADY_S7 <= HREADY_S7_xhdl51;
2109 
    HMASTLOCK_S7 <= HMASTLOCK_S7_xhdl30;
2110 
    HSEL_S8 <= HSEL_S8_xhdl71;
2111 
    HADDR_S8 <= HADDR_S8_xhdl14;
2112 
    HSIZE_S8 <= HSIZE_S8_xhdl88;
2113 
    HTRANS_S8 <= HTRANS_S8_xhdl105;
2114 
    HWRITE_S8 <= HWRITE_S8_xhdl139;
2115 
    HWDATA_S8 <= HWDATA_S8_xhdl122;
2116 
    HREADY_S8 <= HREADY_S8_xhdl52;
2117 
    HMASTLOCK_S8 <= HMASTLOCK_S8_xhdl31;
2118 
    HSEL_S9 <= HSEL_S9_xhdl72;
2119 
    HADDR_S9 <= HADDR_S9_xhdl15;
2120 
    HSIZE_S9 <= HSIZE_S9_xhdl89;
2121 
    HTRANS_S9 <= HTRANS_S9_xhdl106;
2122 
    HWRITE_S9 <= HWRITE_S9_xhdl140;
2123 
    HWDATA_S9 <= HWDATA_S9_xhdl123;
2124 
    HREADY_S9 <= HREADY_S9_xhdl53;
2125 
    HMASTLOCK_S9 <= HMASTLOCK_S9_xhdl32;
2126 
    HSEL_S10 <= HSEL_S10_xhdl59;
2127 
    HADDR_S10 <= HADDR_S10_xhdl2;
2128 
    HSIZE_S10 <= HSIZE_S10_xhdl76;
2129 
    HTRANS_S10 <= HTRANS_S10_xhdl93;
2130 
    HWRITE_S10 <= HWRITE_S10_xhdl127;
2131 
    HWDATA_S10 <= HWDATA_S10_xhdl110;
2132 
    HREADY_S10 <= HREADY_S10_xhdl40;
2133 
    HMASTLOCK_S10 <= HMASTLOCK_S10_xhdl19;
2134 
    HSEL_S11 <= HSEL_S11_xhdl60;
2135 
    HADDR_S11 <= HADDR_S11_xhdl3;
2136 
    HSIZE_S11 <= HSIZE_S11_xhdl77;
2137 
    HTRANS_S11 <= HTRANS_S11_xhdl94;
2138 
    HWRITE_S11 <= HWRITE_S11_xhdl128;
2139 
    HWDATA_S11 <= HWDATA_S11_xhdl111;
2140 
    HREADY_S11 <= HREADY_S11_xhdl41;
2141 
    HMASTLOCK_S11 <= HMASTLOCK_S11_xhdl20;
2142 
    HSEL_S12 <= HSEL_S12_xhdl61;
2143 
    HADDR_S12 <= HADDR_S12_xhdl4;
2144 
    HSIZE_S12 <= HSIZE_S12_xhdl78;
2145 
    HTRANS_S12 <= HTRANS_S12_xhdl95;
2146 
    HWRITE_S12 <= HWRITE_S12_xhdl129;
2147 
    HWDATA_S12 <= HWDATA_S12_xhdl112;
2148 
    HREADY_S12 <= HREADY_S12_xhdl42;
2149 
    HMASTLOCK_S12 <= HMASTLOCK_S12_xhdl21;
2150 
    HSEL_S13 <= HSEL_S13_xhdl62;
2151 
    HADDR_S13 <= HADDR_S13_xhdl5;
2152 
    HSIZE_S13 <= HSIZE_S13_xhdl79;
2153 
    HTRANS_S13 <= HTRANS_S13_xhdl96;
2154 
    HWRITE_S13 <= HWRITE_S13_xhdl130;
2155 
    HWDATA_S13 <= HWDATA_S13_xhdl113;
2156 
    HREADY_S13 <= HREADY_S13_xhdl43;
2157 
    HMASTLOCK_S13 <= HMASTLOCK_S13_xhdl22;
2158 
    HSEL_S14 <= HSEL_S14_xhdl63;
2159 
    HADDR_S14 <= HADDR_S14_xhdl6;
2160 
    HSIZE_S14 <= HSIZE_S14_xhdl80;
2161 
    HTRANS_S14 <= HTRANS_S14_xhdl97;
2162 
    HWRITE_S14 <= HWRITE_S14_xhdl131;
2163 
    HWDATA_S14 <= HWDATA_S14_xhdl114;
2164 
    HREADY_S14 <= HREADY_S14_xhdl44;
2165 
    HMASTLOCK_S14 <= HMASTLOCK_S14_xhdl23;
2166 
    HSEL_S15 <= HSEL_S15_xhdl64;
2167 
    HADDR_S15 <= HADDR_S15_xhdl7;
2168 
    HSIZE_S15 <= HSIZE_S15_xhdl81;
2169 
    HTRANS_S15 <= HTRANS_S15_xhdl98;
2170 
    HWRITE_S15 <= HWRITE_S15_xhdl132;
2171 
    HWDATA_S15 <= HWDATA_S15_xhdl115;
2172 
    HREADY_S15 <= HREADY_S15_xhdl45;
2173 
    HMASTLOCK_S15 <= HMASTLOCK_S15_xhdl24;
2174 
    HSEL_S16 <= HSEL_S16_xhdl73;
2175 
    HADDR_S16 <= HADDR_S16_xhdl16;
2176 
    HSIZE_S16 <= HSIZE_S16_xhdl90;
2177 
    HTRANS_S16 <= HTRANS_S16_xhdl107;
2178 
    HWRITE_S16 <= HWRITE_S16_xhdl141;
2179 
    HWDATA_S16 <= HWDATA_S16_xhdl124;
2180 
    HREADY_S16 <= HREADY_S16_xhdl54;
2181 
    HMASTLOCK_S16 <= HMASTLOCK_S16_xhdl33;
2182 
    xhdl146  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m0AddrReady_int  <= s0m0AddrReady;  end generate;
2183 
    xhdl147  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m0AddrReady_int  <= '1';            end generate;
2184 
    xhdl148  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m0AddrReady_int  <= s1m0AddrReady;  end generate;
2185 
    xhdl149  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m0AddrReady_int  <= '1';            end generate;
2186 
    xhdl150  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m0AddrReady_int  <= s2m0AddrReady;  end generate;
2187 
    xhdl151  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m0AddrReady_int  <= '1';            end generate;
2188 
    xhdl152  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m0AddrReady_int  <= s3m0AddrReady;  end generate;
2189 
    xhdl153  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m0AddrReady_int  <= '1';            end generate;
2190 
    xhdl154  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m0AddrReady_int  <= s4m0AddrReady;  end generate;
2191 
    xhdl155  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m0AddrReady_int  <= '1';            end generate;
2192 
    xhdl156  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m0AddrReady_int  <= s5m0AddrReady;  end generate;
2193 
    xhdl157  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m0AddrReady_int  <= '1';            end generate;
2194 
    xhdl158  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m0AddrReady_int  <= s6m0AddrReady;  end generate;
2195 
    xhdl159  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m0AddrReady_int  <= '1';            end generate;
2196 
    xhdl160  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m0AddrReady_int  <= s7m0AddrReady;  end generate;
2197 
    xhdl161  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m0AddrReady_int  <= '1';            end generate;
2198 
    xhdl162  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m0AddrReady_int  <= s8m0AddrReady;  end generate;
2199 
    xhdl163  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m0AddrReady_int  <= '1';            end generate;
2200 
    xhdl164  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m0AddrReady_int  <= s9m0AddrReady;  end generate;
2201 
    xhdl165  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m0AddrReady_int  <= '1';            end generate;
2202 
    xhdl166  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate s10m0AddrReady_int <= s10m0AddrReady; end generate;
2203 
    xhdl167  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate s10m0AddrReady_int <= '1';            end generate;
2204 
    xhdl168  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate s11m0AddrReady_int <= s11m0AddrReady; end generate;
2205 
    xhdl169  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate s11m0AddrReady_int <= '1';            end generate;
2206 
    xhdl170  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate s12m0AddrReady_int <= s12m0AddrReady; end generate;
2207 
    xhdl171  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate s12m0AddrReady_int <= '1';            end generate;
2208 
    xhdl172  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate s13m0AddrReady_int <= s13m0AddrReady; end generate;
2209 
    xhdl173  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate s13m0AddrReady_int <= '1';            end generate;
2210 
    xhdl174  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate s14m0AddrReady_int <= s14m0AddrReady; end generate;
2211 
    xhdl175  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate s14m0AddrReady_int <= '1';            end generate;
2212 
    xhdl176  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate s15m0AddrReady_int <= s15m0AddrReady; end generate;
2213 
    xhdl177  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate s15m0AddrReady_int <= '1';            end generate;
2214 
    xhdl178  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate s16m0AddrReady_int <= s16m0AddrReady; end generate;
2215 
    xhdl179  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate s16m0AddrReady_int <= '1';            end generate;
2216 
    xhdl182  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m1AddrReady_int  <= s0m1AddrReady;  end generate;
2217 
    xhdl183  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m1AddrReady_int  <= '1';            end generate;
2218 
    xhdl184  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m1AddrReady_int  <= s1m1AddrReady;  end generate;
2219 
    xhdl185  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m1AddrReady_int  <= '1';            end generate;
2220 
    xhdl186  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m1AddrReady_int  <= s2m1AddrReady;  end generate;
2221 
    xhdl187  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m1AddrReady_int  <= '1';            end generate;
2222 
    xhdl188  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m1AddrReady_int  <= s3m1AddrReady;  end generate;
2223 
    xhdl189  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m1AddrReady_int  <= '1';            end generate;
2224 
    xhdl190  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m1AddrReady_int  <= s4m1AddrReady;  end generate;
2225 
    xhdl191  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m1AddrReady_int  <= '1';            end generate;
2226 
    xhdl192  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m1AddrReady_int  <= s5m1AddrReady;  end generate;
2227 
    xhdl193  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m1AddrReady_int  <= '1';            end generate;
2228 
    xhdl194  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m1AddrReady_int  <= s6m1AddrReady;  end generate;
2229 
    xhdl195  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m1AddrReady_int  <= '1';            end generate;
2230 
    xhdl196  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m1AddrReady_int  <= s7m1AddrReady;  end generate;
2231 
    xhdl197  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m1AddrReady_int  <= '1';            end generate;
2232 
    xhdl198  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m1AddrReady_int  <= s8m1AddrReady;  end generate;
2233 
    xhdl199  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m1AddrReady_int  <= '1';            end generate;
2234 
    xhdl200  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m1AddrReady_int  <= s9m1AddrReady;  end generate;
2235 
    xhdl201  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m1AddrReady_int  <= '1';            end generate;
2236 
    xhdl202  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate s10m1AddrReady_int <= s10m1AddrReady; end generate;
2237 
    xhdl203  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate s10m1AddrReady_int <= '1';            end generate;
2238 
    xhdl204  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate s11m1AddrReady_int <= s11m1AddrReady; end generate;
2239 
    xhdl205  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate s11m1AddrReady_int <= '1';            end generate;
2240 
    xhdl206  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate s12m1AddrReady_int <= s12m1AddrReady; end generate;
2241 
    xhdl207  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate s12m1AddrReady_int <= '1';            end generate;
2242 
    xhdl208  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate s13m1AddrReady_int <= s13m1AddrReady; end generate;
2243 
    xhdl209  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate s13m1AddrReady_int <= '1';            end generate;
2244 
    xhdl210  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate s14m1AddrReady_int <= s14m1AddrReady; end generate;
2245 
    xhdl211  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate s14m1AddrReady_int <= '1';            end generate;
2246 
    xhdl212  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate s15m1AddrReady_int <= s15m1AddrReady; end generate;
2247 
    xhdl213  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate s15m1AddrReady_int <= '1';            end generate;
2248 
    xhdl214  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate s16m1AddrReady_int <= s16m1AddrReady; end generate;
2249 
    xhdl215  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate s16m1AddrReady_int <= '1';            end generate;
2250 
    xhdl218  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m0DataReady_int  <= s0m0DataReady;  end generate;
2251 
    xhdl219  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m0DataReady_int  <= '1';            end generate;
2252 
    xhdl220  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m0DataReady_int  <= s1m0DataReady;  end generate;
2253 
    xhdl221  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m0DataReady_int  <= '1';            end generate;
2254 
    xhdl222  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m0DataReady_int  <= s2m0DataReady;  end generate;
2255 
    xhdl223  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m0DataReady_int  <= '1';            end generate;
2256 
    xhdl224  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m0DataReady_int  <= s3m0DataReady;  end generate;
2257 
    xhdl225  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m0DataReady_int  <= '1';            end generate;
2258 
    xhdl226  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m0DataReady_int  <= s4m0DataReady;  end generate;
2259 
    xhdl227  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m0DataReady_int  <= '1';            end generate;
2260 
    xhdl228  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m0DataReady_int  <= s5m0DataReady;  end generate;
2261 
    xhdl229  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m0DataReady_int  <= '1';            end generate;
2262 
    xhdl230  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m0DataReady_int  <= s6m0DataReady;  end generate;
2263 
    xhdl231  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m0DataReady_int  <= '1';            end generate;
2264 
    xhdl232  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m0DataReady_int  <= s7m0DataReady;  end generate;
2265 
    xhdl233  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m0DataReady_int  <= '1';            end generate;
2266 
    xhdl234  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m0DataReady_int  <= s8m0DataReady;  end generate;
2267 
    xhdl235  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m0DataReady_int  <= '1';            end generate;
2268 
    xhdl236  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m0DataReady_int  <= s9m0DataReady;  end generate;
2269 
    xhdl237  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m0DataReady_int  <= '1';            end generate;
2270 
    xhdl238  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate s10m0DataReady_int <= s10m0DataReady; end generate;
2271 
    xhdl239  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate s10m0DataReady_int <= '1';            end generate;
2272 
    xhdl240  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate s11m0DataReady_int <= s11m0DataReady; end generate;
2273 
    xhdl241  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate s11m0DataReady_int <= '1';            end generate;
2274 
    xhdl242  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate s12m0DataReady_int <= s12m0DataReady; end generate;
2275 
    xhdl243  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate s12m0DataReady_int <= '1';            end generate;
2276 
    xhdl244  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate s13m0DataReady_int <= s13m0DataReady; end generate;
2277 
    xhdl245  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate s13m0DataReady_int <= '1';            end generate;
2278 
    xhdl246  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate s14m0DataReady_int <= s14m0DataReady; end generate;
2279 
    xhdl247  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate s14m0DataReady_int <= '1';            end generate;
2280 
    xhdl248  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate s15m0DataReady_int <= s15m0DataReady; end generate;
2281 
    xhdl249  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate s15m0DataReady_int <= '1';            end generate;
2282 
    xhdl250  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate s16m0DataReady_int <= s16m0DataReady; end generate;
2283 
    xhdl251  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate s16m0DataReady_int <= '1';            end generate;
2284 
    xhdl254  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m1DataReady_int  <= s0m1DataReady;  end generate;
2285 
    xhdl255  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m1DataReady_int  <= '1';            end generate;
2286 
    xhdl256  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m1DataReady_int  <= s1m1DataReady;  end generate;
2287 
    xhdl257  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m1DataReady_int  <= '1';            end generate;
2288 
    xhdl258  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m1DataReady_int  <= s2m1DataReady;  end generate;
2289 
    xhdl259  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m1DataReady_int  <= '1';            end generate;
2290 
    xhdl260  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m1DataReady_int  <= s3m1DataReady;  end generate;
2291 
    xhdl261  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m1DataReady_int  <= '1';            end generate;
2292 
    xhdl262  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m1DataReady_int  <= s4m1DataReady;  end generate;
2293 
    xhdl263  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m1DataReady_int  <= '1';            end generate;
2294 
    xhdl264  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m1DataReady_int  <= s5m1DataReady;  end generate;
2295 
    xhdl265  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m1DataReady_int  <= '1';            end generate;
2296 
    xhdl266  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m1DataReady_int  <= s6m1DataReady;  end generate;
2297 
    xhdl267  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m1DataReady_int  <= '1';            end generate;
2298 
    xhdl268  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m1DataReady_int  <= s7m1DataReady;  end generate;
2299 
    xhdl269  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m1DataReady_int  <= '1';            end generate;
2300 
    xhdl270  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m1DataReady_int  <= s8m1DataReady;  end generate;
2301 
    xhdl271  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m1DataReady_int  <= '1';            end generate;
2302 
    xhdl272  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m1DataReady_int  <= s9m1DataReady;  end generate;
2303 
    xhdl273  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m1DataReady_int  <= '1';            end generate;
2304 
    xhdl274  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate s10m1DataReady_int <= s10m1DataReady; end generate;
2305 
    xhdl275  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate s10m1DataReady_int <= '1';            end generate;
2306 
    xhdl276  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate s11m1DataReady_int <= s11m1DataReady; end generate;
2307 
    xhdl277  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate s11m1DataReady_int <= '1';            end generate;
2308 
    xhdl278  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate s12m1DataReady_int <= s12m1DataReady; end generate;
2309 
    xhdl279  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate s12m1DataReady_int <= '1';            end generate;
2310 
    xhdl280  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate s13m1DataReady_int <= s13m1DataReady; end generate;
2311 
    xhdl281  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate s13m1DataReady_int <= '1';            end generate;
2312 
    xhdl282  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate s14m1DataReady_int <= s14m1DataReady; end generate;
2313 
    xhdl283  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate s14m1DataReady_int <= '1';            end generate;
2314 
    xhdl284  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate s15m1DataReady_int <= s15m1DataReady; end generate;
2315 
    xhdl285  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate s15m1DataReady_int <= '1';            end generate;
2316 
    xhdl286  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate s16m1DataReady_int <= s16m1DataReady; end generate;
2317 
    xhdl287  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate s16m1DataReady_int <= '1';            end generate;
2318 
    xhdl290  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m0HResp_int  <= s0m0HResp;  end generate;
2319 
    xhdl291  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m0HResp_int  <= '0';        end generate;
2320 
    xhdl292  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m0HResp_int  <= s1m0HResp;  end generate;
2321 
    xhdl293  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m0HResp_int  <= '0';        end generate;
2322 
    xhdl294  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m0HResp_int  <= s2m0HResp;  end generate;
2323 
    xhdl295  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m0HResp_int  <= '0';        end generate;
2324 
    xhdl296  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m0HResp_int  <= s3m0HResp;  end generate;
2325 
    xhdl297  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m0HResp_int  <= '0';        end generate;
2326 
    xhdl298  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m0HResp_int  <= s4m0HResp;  end generate;
2327 
    xhdl299  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m0HResp_int  <= '0';        end generate;
2328 
    xhdl300  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m0HResp_int  <= s5m0HResp;  end generate;
2329 
    xhdl301  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m0HResp_int  <= '0';        end generate;
2330 
    xhdl302  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m0HResp_int  <= s6m0HResp;  end generate;
2331 
    xhdl303  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m0HResp_int  <= '0';        end generate;
2332 
    xhdl304  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m0HResp_int  <= s7m0HResp;  end generate;
2333 
    xhdl305  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m0HResp_int  <= '0';        end generate;
2334 
    xhdl306  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m0HResp_int  <= s8m0HResp;  end generate;
2335 
    xhdl307  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m0HResp_int  <= '0';        end generate;
2336 
    xhdl308  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m0HResp_int  <= s9m0HResp;  end generate;
2337 
    xhdl309  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m0HResp_int  <= '0';        end generate;
2338 
    xhdl310  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate s10m0HResp_int <= s10m0HResp; end generate;
2339 
    xhdl311  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate s10m0HResp_int <= '0';        end generate;
2340 
    xhdl312  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate s11m0HResp_int <= s11m0HResp; end generate;
2341 
    xhdl313  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate s11m0HResp_int <= '0';        end generate;
2342 
    xhdl314  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate s12m0HResp_int <= s12m0HResp; end generate;
2343 
    xhdl315  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate s12m0HResp_int <= '0';        end generate;
2344 
    xhdl316  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate s13m0HResp_int <= s13m0HResp; end generate;
2345 
    xhdl317  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate s13m0HResp_int <= '0';        end generate;
2346 
    xhdl318  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate s14m0HResp_int <= s14m0HResp; end generate;
2347 
    xhdl319  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate s14m0HResp_int <= '0';        end generate;
2348 
    xhdl320  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate s15m0HResp_int <= s15m0HResp; end generate;
2349 
    xhdl321  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate s15m0HResp_int <= '0';        end generate;
2350 
    xhdl322  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate s16m0HResp_int <= s16m0HResp; end generate;
2351 
    xhdl323  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate s16m0HResp_int <= '0';        end generate;
2352 
    xhdl326  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m1HResp_int  <= s0m1HResp;  end generate;
2353 
    xhdl327  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m1HResp_int  <= '0';        end generate;
2354 
    xhdl328  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m1HResp_int  <= s1m1HResp;  end generate;
2355 
    xhdl329  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m1HResp_int  <= '0';        end generate;
2356 
    xhdl330  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m1HResp_int  <= s2m1HResp;  end generate;
2357 
    xhdl331  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m1HResp_int  <= '0';        end generate;
2358 
    xhdl332  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m1HResp_int  <= s3m1HResp;  end generate;
2359 
    xhdl333  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m1HResp_int  <= '0';        end generate;
2360 
    xhdl334  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m1HResp_int  <= s4m1HResp;  end generate;
2361 
    xhdl335  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m1HResp_int  <= '0';        end generate;
2362 
    xhdl336  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m1HResp_int  <= s5m1HResp;  end generate;
2363 
    xhdl337  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m1HResp_int  <= '0';        end generate;
2364 
    xhdl338  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m1HResp_int  <= s6m1HResp;  end generate;
2365 
    xhdl339  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m1HResp_int  <= '0';        end generate;
2366 
    xhdl340  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m1HResp_int  <= s7m1HResp;  end generate;
2367 
    xhdl341  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m1HResp_int  <= '0';        end generate;
2368 
    xhdl342  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m1HResp_int  <= s8m1HResp;  end generate;
2369 
    xhdl343  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m1HResp_int  <= '0';        end generate;
2370 
    xhdl344  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m1HResp_int  <= s9m1HResp;  end generate;
2371 
    xhdl345  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m1HResp_int  <= '0';        end generate;
2372 
    xhdl346  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate s10m1HResp_int <= s10m1HResp; end generate;
2373 
    xhdl347  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate s10m1HResp_int <= '0';        end generate;
2374 
    xhdl348  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate s11m1HResp_int <= s11m1HResp; end generate;
2375 
    xhdl349  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate s11m1HResp_int <= '0';        end generate;
2376 
    xhdl350  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate s12m1HResp_int <= s12m1HResp; end generate;
2377 
    xhdl351  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate s12m1HResp_int <= '0';        end generate;
2378 
    xhdl352  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate s13m1HResp_int <= s13m1HResp; end generate;
2379 
    xhdl353  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate s13m1HResp_int <= '0';        end generate;
2380 
    xhdl354  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate s14m1HResp_int <= s14m1HResp; end generate;
2381 
    xhdl355  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate s14m1HResp_int <= '0';        end generate;
2382 
    xhdl356  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate s15m1HResp_int <= s15m1HResp; end generate;
2383 
    xhdl357  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate s15m1HResp_int <= '0';        end generate;
2384 
    xhdl358  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate s16m1HResp_int <= s16m1HResp; end generate;
2385 
    xhdl359  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate s16m1HResp_int <= '0';        end generate;
2386 
    xhdl362  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0AddrSel_int  <= m0s0AddrSel;  end generate;
2387 
    xhdl363  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0AddrSel_int  <= '0';          end generate;
2388 
    xhdl364  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1AddrSel_int  <= m0s1AddrSel;  end generate;
2389 
    xhdl365  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1AddrSel_int  <= '0';          end generate;
2390 
    xhdl366  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2AddrSel_int  <= m0s2AddrSel;  end generate;
2391 
    xhdl367  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2AddrSel_int  <= '0';          end generate;
2392 
    xhdl368  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3AddrSel_int  <= m0s3AddrSel;  end generate;
2393 
    xhdl369  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3AddrSel_int  <= '0';          end generate;
2394 
    xhdl370  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4AddrSel_int  <= m0s4AddrSel;  end generate;
2395 
    xhdl371  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4AddrSel_int  <= '0';          end generate;
2396 
    xhdl372  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5AddrSel_int  <= m0s5AddrSel;  end generate;
2397 
    xhdl373  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5AddrSel_int  <= '0';          end generate;
2398 
    xhdl374  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6AddrSel_int  <= m0s6AddrSel;  end generate;
2399 
    xhdl375  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6AddrSel_int  <= '0';          end generate;
2400 
    xhdl376  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7AddrSel_int  <= m0s7AddrSel;  end generate;
2401 
    xhdl377  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7AddrSel_int  <= '0';          end generate;
2402 
    xhdl378  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8AddrSel_int  <= m0s8AddrSel;  end generate;
2403 
    xhdl379  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8AddrSel_int  <= '0';          end generate;
2404 
    xhdl380  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9AddrSel_int  <= m0s9AddrSel;  end generate;
2405 
    xhdl381  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9AddrSel_int  <= '0';          end generate;
2406 
    xhdl382  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10AddrSel_int <= m0s10AddrSel; end generate;
2407 
    xhdl383  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10AddrSel_int <= '0';          end generate;
2408 
    xhdl384  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11AddrSel_int <= m0s11AddrSel; end generate;
2409 
    xhdl385  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11AddrSel_int <= '0';          end generate;
2410 
    xhdl386  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12AddrSel_int <= m0s12AddrSel; end generate;
2411 
    xhdl387  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12AddrSel_int <= '0';          end generate;
2412 
    xhdl388  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13AddrSel_int <= m0s13AddrSel; end generate;
2413 
    xhdl389  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13AddrSel_int <= '0';          end generate;
2414 
    xhdl390  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14AddrSel_int <= m0s14AddrSel; end generate;
2415 
    xhdl391  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14AddrSel_int <= '0';          end generate;
2416 
    xhdl392  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15AddrSel_int <= m0s15AddrSel; end generate;
2417 
    xhdl393  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15AddrSel_int <= '0';          end generate;
2418 
    xhdl394  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16AddrSel_int <= m0s16AddrSel; end generate;
2419 
    xhdl395  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16AddrSel_int <= '0';          end generate;
2420 
    xhdl398  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0AddrSel_int  <= m1s0AddrSel;  end generate;
2421 
    xhdl399  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0AddrSel_int  <= '0';          end generate;
2422 
    xhdl400  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1AddrSel_int  <= m1s1AddrSel;  end generate;
2423 
    xhdl401  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1AddrSel_int  <= '0';          end generate;
2424 
    xhdl402  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2AddrSel_int  <= m1s2AddrSel;  end generate;
2425 
    xhdl403  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2AddrSel_int  <= '0';          end generate;
2426 
    xhdl404  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3AddrSel_int  <= m1s3AddrSel;  end generate;
2427 
    xhdl405  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3AddrSel_int  <= '0';          end generate;
2428 
    xhdl406  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4AddrSel_int  <= m1s4AddrSel;  end generate;
2429 
    xhdl407  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4AddrSel_int  <= '0';          end generate;
2430 
    xhdl408  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5AddrSel_int  <= m1s5AddrSel;  end generate;
2431 
    xhdl409  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5AddrSel_int  <= '0';          end generate;
2432 
    xhdl410  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6AddrSel_int  <= m1s6AddrSel;  end generate;
2433 
    xhdl411  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6AddrSel_int  <= '0';          end generate;
2434 
    xhdl412  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7AddrSel_int  <= m1s7AddrSel;  end generate;
2435 
    xhdl413  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7AddrSel_int  <= '0';          end generate;
2436 
    xhdl414  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8AddrSel_int  <= m1s8AddrSel;  end generate;
2437 
    xhdl415  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8AddrSel_int  <= '0';          end generate;
2438 
    xhdl416  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9AddrSel_int  <= m1s9AddrSel;  end generate;
2439 
    xhdl417  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9AddrSel_int  <= '0';          end generate;
2440 
    xhdl418  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10AddrSel_int <= m1s10AddrSel; end generate;
2441 
    xhdl419  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10AddrSel_int <= '0';          end generate;
2442 
    xhdl420  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11AddrSel_int <= m1s11AddrSel; end generate;
2443 
    xhdl421  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11AddrSel_int <= '0';          end generate;
2444 
    xhdl422  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12AddrSel_int <= m1s12AddrSel; end generate;
2445 
    xhdl423  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12AddrSel_int <= '0';          end generate;
2446 
    xhdl424  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13AddrSel_int <= m1s13AddrSel; end generate;
2447 
    xhdl425  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13AddrSel_int <= '0';          end generate;
2448 
    xhdl426  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14AddrSel_int <= m1s14AddrSel; end generate;
2449 
    xhdl427  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14AddrSel_int <= '0';          end generate;
2450 
    xhdl428  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15AddrSel_int <= m1s15AddrSel; end generate;
2451 
    xhdl429  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15AddrSel_int <= '0';          end generate;
2452 
    xhdl430  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16AddrSel_int <= m1s16AddrSel; end generate;
2453 
    xhdl431  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16AddrSel_int <= '0';          end generate;
2454 
    xhdl434  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0DataSel_int  <= m0s0DataSel;  end generate;
2455 
    xhdl435  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0DataSel_int  <= '0';          end generate;
2456 
    xhdl436  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1DataSel_int  <= m0s1DataSel;  end generate;
2457 
    xhdl437  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1DataSel_int  <= '0';          end generate;
2458 
    xhdl438  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2DataSel_int  <= m0s2DataSel;  end generate;
2459 
    xhdl439  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2DataSel_int  <= '0';          end generate;
2460 
    xhdl440  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3DataSel_int  <= m0s3DataSel;  end generate;
2461 
    xhdl441  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3DataSel_int  <= '0';          end generate;
2462 
    xhdl442  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4DataSel_int  <= m0s4DataSel;  end generate;
2463 
    xhdl443  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4DataSel_int  <= '0';          end generate;
2464 
    xhdl444  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5DataSel_int  <= m0s5DataSel;  end generate;
2465 
    xhdl445  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5DataSel_int  <= '0';          end generate;
2466 
    xhdl446  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6DataSel_int  <= m0s6DataSel;  end generate;
2467 
    xhdl447  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6DataSel_int  <= '0';          end generate;
2468 
    xhdl448  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7DataSel_int  <= m0s7DataSel;  end generate;
2469 
    xhdl449  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7DataSel_int  <= '0';          end generate;
2470 
    xhdl450  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8DataSel_int  <= m0s8DataSel;  end generate;
2471 
    xhdl451  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8DataSel_int  <= '0';          end generate;
2472 
    xhdl452  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9DataSel_int  <= m0s9DataSel;  end generate;
2473 
    xhdl453  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9DataSel_int  <= '0';          end generate;
2474 
    xhdl454  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10DataSel_int <= m0s10DataSel; end generate;
2475 
    xhdl455  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10DataSel_int <= '0';          end generate;
2476 
    xhdl456  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11DataSel_int <= m0s11DataSel; end generate;
2477 
    xhdl457  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11DataSel_int <= '0';          end generate;
2478 
    xhdl458  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12DataSel_int <= m0s12DataSel; end generate;
2479 
    xhdl459  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12DataSel_int <= '0';          end generate;
2480 
    xhdl460  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13DataSel_int <= m0s13DataSel; end generate;
2481 
    xhdl461  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13DataSel_int <= '0';          end generate;
2482 
    xhdl462  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14DataSel_int <= m0s14DataSel; end generate;
2483 
    xhdl463  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14DataSel_int <= '0';          end generate;
2484 
    xhdl464  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15DataSel_int <= m0s15DataSel; end generate;
2485 
    xhdl465  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15DataSel_int <= '0';          end generate;
2486 
    xhdl466  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16DataSel_int <= m0s16DataSel; end generate;
2487 
    xhdl467  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16DataSel_int <= '0';          end generate;
2488 
    xhdl470  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0DataSel_int  <= m1s0DataSel;  end generate;
2489 
    xhdl471  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0DataSel_int  <= '0';          end generate;
2490 
    xhdl472  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1DataSel_int  <= m1s1DataSel;  end generate;
2491 
    xhdl473  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1DataSel_int  <= '0';          end generate;
2492 
    xhdl474  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2DataSel_int  <= m1s2DataSel;  end generate;
2493 
    xhdl475  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2DataSel_int  <= '0';          end generate;
2494 
    xhdl476  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3DataSel_int  <= m1s3DataSel;  end generate;
2495 
    xhdl477  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3DataSel_int  <= '0';          end generate;
2496 
    xhdl478  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4DataSel_int  <= m1s4DataSel;  end generate;
2497 
    xhdl479  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4DataSel_int  <= '0';          end generate;
2498 
    xhdl480  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5DataSel_int  <= m1s5DataSel;  end generate;
2499 
    xhdl481  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5DataSel_int  <= '0';          end generate;
2500 
    xhdl482  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6DataSel_int  <= m1s6DataSel;  end generate;
2501 
    xhdl483  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6DataSel_int  <= '0';          end generate;
2502 
    xhdl484  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7DataSel_int  <= m1s7DataSel;  end generate;
2503 
    xhdl485  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7DataSel_int  <= '0';          end generate;
2504 
    xhdl486  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8DataSel_int  <= m1s8DataSel;  end generate;
2505 
    xhdl487  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8DataSel_int  <= '0';          end generate;
2506 
    xhdl488  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9DataSel_int  <= m1s9DataSel;  end generate;
2507 
    xhdl489  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9DataSel_int  <= '0';          end generate;
2508 
    xhdl490  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10DataSel_int <= m1s10DataSel; end generate;
2509 
    xhdl491  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10DataSel_int <= '0';          end generate;
2510 
    xhdl492  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11DataSel_int <= m1s11DataSel; end generate;
2511 
    xhdl493  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11DataSel_int <= '0';          end generate;
2512 
    xhdl494  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12DataSel_int <= m1s12DataSel; end generate;
2513 
    xhdl495  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12DataSel_int <= '0';          end generate;
2514 
    xhdl496  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13DataSel_int <= m1s13DataSel; end generate;
2515 
    xhdl497  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13DataSel_int <= '0';          end generate;
2516 
    xhdl498  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14DataSel_int <= m1s14DataSel; end generate;
2517 
    xhdl499  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14DataSel_int <= '0';          end generate;
2518 
    xhdl500  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15DataSel_int <= m1s15DataSel; end generate;
2519 
    xhdl501  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15DataSel_int <= '0';          end generate;
2520 
    xhdl502  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16DataSel_int <= m1s16DataSel; end generate;
2521 
    xhdl503  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16DataSel_int <= '0';          end generate;
2522 
    xhdl506  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0GatedHADDR  <= M0GATEDHADDR;                       end generate;
2523 
    xhdl507  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2524 
    xhdl508  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1GatedHADDR  <= M0GATEDHADDR;                       end generate;
2525 
    xhdl509  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2526 
    xhdl510  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2GatedHADDR  <= M0GATEDHADDR;                       end generate;
2527 
    xhdl511  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2528 
    xhdl512  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3GatedHADDR  <= M0GATEDHADDR;                       end generate;
2529 
    xhdl513  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2530 
    xhdl514  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4GatedHADDR  <= M0GATEDHADDR;                       end generate;
2531 
    xhdl515  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2532 
    xhdl516  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5GatedHADDR  <= M0GATEDHADDR;                       end generate;
2533 
    xhdl517  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2534 
    xhdl518  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6GatedHADDR  <= M0GATEDHADDR;                       end generate;
2535 
    xhdl519  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2536 
    xhdl520  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7GatedHADDR  <= M0GATEDHADDR;                       end generate;
2537 
    xhdl521  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2538 
    xhdl522  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8GatedHADDR  <= M0GATEDHADDR;                       end generate;
2539 
    xhdl523  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2540 
    xhdl524  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9GatedHADDR  <= M0GATEDHADDR;                       end generate;
2541 
    xhdl525  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2542 
    xhdl526  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10GatedHADDR <= M0GATEDHADDR;                       end generate;
2543 
    xhdl527  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10GatedHADDR <= "00000000000000000000000000000000"; end generate;
2544 
    xhdl528  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11GatedHADDR <= M0GATEDHADDR;                       end generate;
2545 
    xhdl529  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11GatedHADDR <= "00000000000000000000000000000000"; end generate;
2546 
    xhdl530  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12GatedHADDR <= M0GATEDHADDR;                       end generate;
2547 
    xhdl531  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12GatedHADDR <= "00000000000000000000000000000000"; end generate;
2548 
    xhdl532  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13GatedHADDR <= M0GATEDHADDR;                       end generate;
2549 
    xhdl533  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13GatedHADDR <= "00000000000000000000000000000000"; end generate;
2550 
    xhdl534  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14GatedHADDR <= M0GATEDHADDR;                       end generate;
2551 
    xhdl535  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14GatedHADDR <= "00000000000000000000000000000000"; end generate;
2552 
    xhdl536  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15GatedHADDR <= M0GATEDHADDR;                       end generate;
2553 
    xhdl537  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15GatedHADDR <= "00000000000000000000000000000000"; end generate;
2554 
    xhdl538  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16GatedHADDR <= M0GATEDHADDR;                       end generate;
2555 
    xhdl539  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16GatedHADDR <= "00000000000000000000000000000000"; end generate;
2556 
    xhdl542  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0GatedHADDR  <= M1GATEDHADDR;                       end generate;
2557 
    xhdl543  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2558 
    xhdl544  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1GatedHADDR  <= M1GATEDHADDR;                       end generate;
2559 
    xhdl545  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2560 
    xhdl546  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2GatedHADDR  <= M1GATEDHADDR;                       end generate;
2561 
    xhdl547  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2562 
    xhdl548  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3GatedHADDR  <= M1GATEDHADDR;                       end generate;
2563 
    xhdl549  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2564 
    xhdl550  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4GatedHADDR  <= M1GATEDHADDR;                       end generate;
2565 
    xhdl551  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2566 
    xhdl552  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5GatedHADDR  <= M1GATEDHADDR;                       end generate;
2567 
    xhdl553  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2568 
    xhdl554  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6GatedHADDR  <= M1GATEDHADDR;                       end generate;
2569 
    xhdl555  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2570 
    xhdl556  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7GatedHADDR  <= M1GATEDHADDR;                       end generate;
2571 
    xhdl557  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2572 
    xhdl558  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8GatedHADDR  <= M1GATEDHADDR;                       end generate;
2573 
    xhdl559  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2574 
    xhdl560  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9GatedHADDR  <= M1GATEDHADDR;                       end generate;
2575 
    xhdl561  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9GatedHADDR  <= "00000000000000000000000000000000"; end generate;
2576 
    xhdl562  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10GatedHADDR <= M1GATEDHADDR;                       end generate;
2577 
    xhdl563  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10GatedHADDR <= "00000000000000000000000000000000"; end generate;
2578 
    xhdl564  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11GatedHADDR <= M1GATEDHADDR;                       end generate;
2579 
    xhdl565  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11GatedHADDR <= "00000000000000000000000000000000"; end generate;
2580 
    xhdl566  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12GatedHADDR <= M1GATEDHADDR;                       end generate;
2581 
    xhdl567  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12GatedHADDR <= "00000000000000000000000000000000"; end generate;
2582 
    xhdl568  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13GatedHADDR <= M1GATEDHADDR;                       end generate;
2583 
    xhdl569  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13GatedHADDR <= "00000000000000000000000000000000"; end generate;
2584 
    xhdl570  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14GatedHADDR <= M1GATEDHADDR;                       end generate;
2585 
    xhdl571  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14GatedHADDR <= "00000000000000000000000000000000"; end generate;
2586 
    xhdl572  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15GatedHADDR <= M1GATEDHADDR;                       end generate;
2587 
    xhdl573  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15GatedHADDR <= "00000000000000000000000000000000"; end generate;
2588 
    xhdl574  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16GatedHADDR <= M1GATEDHADDR;                       end generate;
2589 
    xhdl575  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16GatedHADDR <= "00000000000000000000000000000000"; end generate;
2590 
    xhdl578  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2591 
    xhdl579  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0GatedHMASTLOCK  <= '0';              end generate;
2592 
    xhdl580  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2593 
    xhdl581  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1GatedHMASTLOCK  <= '0';              end generate;
2594 
    xhdl582  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2595 
    xhdl583  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2GatedHMASTLOCK  <= '0';              end generate;
2596 
    xhdl584  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2597 
    xhdl585  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3GatedHMASTLOCK  <= '0';              end generate;
2598 
    xhdl586  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2599 
    xhdl587  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4GatedHMASTLOCK  <= '0';              end generate;
2600 
    xhdl588  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2601 
    xhdl589  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5GatedHMASTLOCK  <= '0';              end generate;
2602 
    xhdl590  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2603 
    xhdl591  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6GatedHMASTLOCK  <= '0';              end generate;
2604 
    xhdl592  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2605 
    xhdl593  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7GatedHMASTLOCK  <= '0';              end generate;
2606 
    xhdl594  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2607 
    xhdl595  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8GatedHMASTLOCK  <= '0';              end generate;
2608 
    xhdl596  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9GatedHMASTLOCK  <= M0GATEDHMASTLOCK; end generate;
2609 
    xhdl597  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9GatedHMASTLOCK  <= '0';              end generate;
2610 
    xhdl598  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2611 
    xhdl599  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10GatedHMASTLOCK <= '0';              end generate;
2612 
    xhdl600  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2613 
    xhdl601  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11GatedHMASTLOCK <= '0';              end generate;
2614 
    xhdl602  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2615 
    xhdl603  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12GatedHMASTLOCK <= '0';              end generate;
2616 
    xhdl604  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2617 
    xhdl605  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13GatedHMASTLOCK <= '0';              end generate;
2618 
    xhdl606  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2619 
    xhdl607  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14GatedHMASTLOCK <= '0';              end generate;
2620 
    xhdl608  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2621 
    xhdl609  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15GatedHMASTLOCK <= '0';              end generate;
2622 
    xhdl610  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16GatedHMASTLOCK <= M0GATEDHMASTLOCK; end generate;
2623 
    xhdl611  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16GatedHMASTLOCK <= '0';              end generate;
2624 
    xhdl614  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2625 
    xhdl615  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0GatedHMASTLOCK  <= '0';              end generate;
2626 
    xhdl616  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2627 
    xhdl617  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1GatedHMASTLOCK  <= '0';              end generate;
2628 
    xhdl618  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2629 
    xhdl619  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2GatedHMASTLOCK  <= '0';              end generate;
2630 
    xhdl620  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2631 
    xhdl621  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3GatedHMASTLOCK  <= '0';              end generate;
2632 
    xhdl622  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2633 
    xhdl623  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4GatedHMASTLOCK  <= '0';              end generate;
2634 
    xhdl624  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2635 
    xhdl625  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5GatedHMASTLOCK  <= '0';              end generate;
2636 
    xhdl626  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2637 
    xhdl627  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6GatedHMASTLOCK  <= '0';              end generate;
2638 
    xhdl628  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2639 
    xhdl629  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7GatedHMASTLOCK  <= '0';              end generate;
2640 
    xhdl630  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2641 
    xhdl631  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8GatedHMASTLOCK  <= '0';              end generate;
2642 
    xhdl632  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9GatedHMASTLOCK  <= M1GATEDHMASTLOCK; end generate;
2643 
    xhdl633  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9GatedHMASTLOCK  <= '0';              end generate;
2644 
    xhdl634  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2645 
    xhdl635  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10GatedHMASTLOCK <= '0';              end generate;
2646 
    xhdl636  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2647 
    xhdl637  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11GatedHMASTLOCK <= '0';              end generate;
2648 
    xhdl638  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2649 
    xhdl639  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12GatedHMASTLOCK <= '0';              end generate;
2650 
    xhdl640  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2651 
    xhdl641  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13GatedHMASTLOCK <= '0';              end generate;
2652 
    xhdl642  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2653 
    xhdl643  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14GatedHMASTLOCK <= '0';              end generate;
2654 
    xhdl644  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2655 
    xhdl645  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15GatedHMASTLOCK <= '0';              end generate;
2656 
    xhdl646  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16GatedHMASTLOCK <= M1GATEDHMASTLOCK; end generate;
2657 
    xhdl647  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16GatedHMASTLOCK <= '0';              end generate;
2658 
    xhdl650  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0GatedHSIZE  <= M0GATEDHSIZE; end generate;
2659 
    xhdl651  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0GatedHSIZE  <= "000";        end generate;
2660 
    xhdl652  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1GatedHSIZE  <= M0GATEDHSIZE; end generate;
2661 
    xhdl653  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1GatedHSIZE  <= "000";        end generate;
2662 
    xhdl654  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2GatedHSIZE  <= M0GATEDHSIZE; end generate;
2663 
    xhdl655  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2GatedHSIZE  <= "000";        end generate;
2664 
    xhdl656  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3GatedHSIZE  <= M0GATEDHSIZE; end generate;
2665 
    xhdl657  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3GatedHSIZE  <= "000";        end generate;
2666 
    xhdl658  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4GatedHSIZE  <= M0GATEDHSIZE; end generate;
2667 
    xhdl659  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4GatedHSIZE  <= "000";        end generate;
2668 
    xhdl660  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5GatedHSIZE  <= M0GATEDHSIZE; end generate;
2669 
    xhdl661  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5GatedHSIZE  <= "000";        end generate;
2670 
    xhdl662  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6GatedHSIZE  <= M0GATEDHSIZE; end generate;
2671 
    xhdl663  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6GatedHSIZE  <= "000";        end generate;
2672 
    xhdl664  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7GatedHSIZE  <= M0GATEDHSIZE; end generate;
2673 
    xhdl665  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7GatedHSIZE  <= "000";        end generate;
2674 
    xhdl666  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8GatedHSIZE  <= M0GATEDHSIZE; end generate;
2675 
    xhdl667  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8GatedHSIZE  <= "000";        end generate;
2676 
    xhdl668  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9GatedHSIZE  <= M0GATEDHSIZE; end generate;
2677 
    xhdl669  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9GatedHSIZE  <= "000";        end generate;
2678 
    xhdl670  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10GatedHSIZE <= M0GATEDHSIZE; end generate;
2679 
    xhdl671  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10GatedHSIZE <= "000";        end generate;
2680 
    xhdl672  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11GatedHSIZE <= M0GATEDHSIZE; end generate;
2681 
    xhdl673  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11GatedHSIZE <= "000";        end generate;
2682 
    xhdl674  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12GatedHSIZE <= M0GATEDHSIZE; end generate;
2683 
    xhdl675  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12GatedHSIZE <= "000";        end generate;
2684 
    xhdl676  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13GatedHSIZE <= M0GATEDHSIZE; end generate;
2685 
    xhdl677  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13GatedHSIZE <= "000";        end generate;
2686 
    xhdl678  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14GatedHSIZE <= M0GATEDHSIZE; end generate;
2687 
    xhdl679  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14GatedHSIZE <= "000";        end generate;
2688 
    xhdl680  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15GatedHSIZE <= M0GATEDHSIZE; end generate;
2689 
    xhdl681  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15GatedHSIZE <= "000";        end generate;
2690 
    xhdl682  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16GatedHSIZE <= M0GATEDHSIZE; end generate;
2691 
    xhdl683  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16GatedHSIZE <= "000";        end generate;
2692 
    xhdl686  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0GatedHSIZE  <= M1GATEDHSIZE; end generate;
2693 
    xhdl687  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0GatedHSIZE  <= "000";        end generate;
2694 
    xhdl688  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1GatedHSIZE  <= M1GATEDHSIZE; end generate;
2695 
    xhdl689  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1GatedHSIZE  <= "000";        end generate;
2696 
    xhdl690  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2GatedHSIZE  <= M1GATEDHSIZE; end generate;
2697 
    xhdl691  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2GatedHSIZE  <= "000";        end generate;
2698 
    xhdl692  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3GatedHSIZE  <= M1GATEDHSIZE; end generate;
2699 
    xhdl693  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3GatedHSIZE  <= "000";        end generate;
2700 
    xhdl694  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4GatedHSIZE  <= M1GATEDHSIZE; end generate;
2701 
    xhdl695  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4GatedHSIZE  <= "000";        end generate;
2702 
    xhdl696  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5GatedHSIZE  <= M1GATEDHSIZE; end generate;
2703 
    xhdl697  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5GatedHSIZE  <= "000";        end generate;
2704 
    xhdl698  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6GatedHSIZE  <= M1GATEDHSIZE; end generate;
2705 
    xhdl699  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6GatedHSIZE  <= "000";        end generate;
2706 
    xhdl700  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7GatedHSIZE  <= M1GATEDHSIZE; end generate;
2707 
    xhdl701  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7GatedHSIZE  <= "000";        end generate;
2708 
    xhdl702  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8GatedHSIZE  <= M1GATEDHSIZE; end generate;
2709 
    xhdl703  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8GatedHSIZE  <= "000";        end generate;
2710 
    xhdl704  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9GatedHSIZE  <= M1GATEDHSIZE; end generate;
2711 
    xhdl705  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9GatedHSIZE  <= "000";        end generate;
2712 
    xhdl706  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10GatedHSIZE <= M1GATEDHSIZE; end generate;
2713 
    xhdl707  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10GatedHSIZE <= "000";        end generate;
2714 
    xhdl708  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11GatedHSIZE <= M1GATEDHSIZE; end generate;
2715 
    xhdl709  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11GatedHSIZE <= "000";        end generate;
2716 
    xhdl710  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12GatedHSIZE <= M1GATEDHSIZE; end generate;
2717 
    xhdl711  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12GatedHSIZE <= "000";        end generate;
2718 
    xhdl712  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13GatedHSIZE <= M1GATEDHSIZE; end generate;
2719 
    xhdl713  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13GatedHSIZE <= "000";        end generate;
2720 
    xhdl714  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14GatedHSIZE <= M1GATEDHSIZE; end generate;
2721 
    xhdl715  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14GatedHSIZE <= "000";        end generate;
2722 
    xhdl716  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15GatedHSIZE <= M1GATEDHSIZE; end generate;
2723 
    xhdl717  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15GatedHSIZE <= "000";        end generate;
2724 
    xhdl718  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16GatedHSIZE <= M1GATEDHSIZE; end generate;
2725 
    xhdl719  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16GatedHSIZE <= "000";        end generate;
2726 
    xhdl722  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0GatedHTRANS  <= M0GATEDHTRANS; end generate;
2727 
    xhdl723  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0GatedHTRANS  <= '0';           end generate;
2728 
    xhdl724  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1GatedHTRANS  <= M0GATEDHTRANS; end generate;
2729 
    xhdl725  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1GatedHTRANS  <= '0';           end generate;
2730 
    xhdl726  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2GatedHTRANS  <= M0GATEDHTRANS; end generate;
2731 
    xhdl727  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2GatedHTRANS  <= '0';           end generate;
2732 
    xhdl728  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3GatedHTRANS  <= M0GATEDHTRANS; end generate;
2733 
    xhdl729  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3GatedHTRANS  <= '0';           end generate;
2734 
    xhdl730  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4GatedHTRANS  <= M0GATEDHTRANS; end generate;
2735 
    xhdl731  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4GatedHTRANS  <= '0';           end generate;
2736 
    xhdl732  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5GatedHTRANS  <= M0GATEDHTRANS; end generate;
2737 
    xhdl733  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5GatedHTRANS  <= '0';           end generate;
2738 
    xhdl734  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6GatedHTRANS  <= M0GATEDHTRANS; end generate;
2739 
    xhdl735  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6GatedHTRANS  <= '0';           end generate;
2740 
    xhdl736  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7GatedHTRANS  <= M0GATEDHTRANS; end generate;
2741 
    xhdl737  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7GatedHTRANS  <= '0';           end generate;
2742 
    xhdl738  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8GatedHTRANS  <= M0GATEDHTRANS; end generate;
2743 
    xhdl739  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8GatedHTRANS  <= '0';           end generate;
2744 
    xhdl740  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9GatedHTRANS  <= M0GATEDHTRANS; end generate;
2745 
    xhdl741  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9GatedHTRANS  <= '0';           end generate;
2746 
    xhdl742  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10GatedHTRANS <= M0GATEDHTRANS; end generate;
2747 
    xhdl743  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10GatedHTRANS <= '0';           end generate;
2748 
    xhdl744  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11GatedHTRANS <= M0GATEDHTRANS; end generate;
2749 
    xhdl745  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11GatedHTRANS <= '0';           end generate;
2750 
    xhdl746  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12GatedHTRANS <= M0GATEDHTRANS; end generate;
2751 
    xhdl747  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12GatedHTRANS <= '0';           end generate;
2752 
    xhdl748  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13GatedHTRANS <= M0GATEDHTRANS; end generate;
2753 
    xhdl749  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13GatedHTRANS <= '0';           end generate;
2754 
    xhdl750  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14GatedHTRANS <= M0GATEDHTRANS; end generate;
2755 
    xhdl751  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14GatedHTRANS <= '0';           end generate;
2756 
    xhdl752  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15GatedHTRANS <= M0GATEDHTRANS; end generate;
2757 
    xhdl753  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15GatedHTRANS <= '0';           end generate;
2758 
    xhdl754  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16GatedHTRANS <= M0GATEDHTRANS; end generate;
2759 
    xhdl755  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16GatedHTRANS <= '0';           end generate;
2760 
    xhdl758  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0GatedHTRANS  <= M1GATEDHTRANS; end generate;
2761 
    xhdl759  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0GatedHTRANS  <= '0';           end generate;
2762 
    xhdl760  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1GatedHTRANS  <= M1GATEDHTRANS; end generate;
2763 
    xhdl761  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1GatedHTRANS  <= '0';           end generate;
2764 
    xhdl762  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2GatedHTRANS  <= M1GATEDHTRANS; end generate;
2765 
    xhdl763  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2GatedHTRANS  <= '0';           end generate;
2766 
    xhdl764  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3GatedHTRANS  <= M1GATEDHTRANS; end generate;
2767 
    xhdl765  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3GatedHTRANS  <= '0';           end generate;
2768 
    xhdl766  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4GatedHTRANS  <= M1GATEDHTRANS; end generate;
2769 
    xhdl767  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4GatedHTRANS  <= '0';           end generate;
2770 
    xhdl768  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5GatedHTRANS  <= M1GATEDHTRANS; end generate;
2771 
    xhdl769  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5GatedHTRANS  <= '0';           end generate;
2772 
    xhdl770  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6GatedHTRANS  <= M1GATEDHTRANS; end generate;
2773 
    xhdl771  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6GatedHTRANS  <= '0';           end generate;
2774 
    xhdl772  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7GatedHTRANS  <= M1GATEDHTRANS; end generate;
2775 
    xhdl773  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7GatedHTRANS  <= '0';           end generate;
2776 
    xhdl774  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8GatedHTRANS  <= M1GATEDHTRANS; end generate;
2777 
    xhdl775  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8GatedHTRANS  <= '0';           end generate;
2778 
    xhdl776  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9GatedHTRANS  <= M1GATEDHTRANS; end generate;
2779 
    xhdl777  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9GatedHTRANS  <= '0';           end generate;
2780 
    xhdl778  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10GatedHTRANS <= M1GATEDHTRANS; end generate;
2781 
    xhdl779  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10GatedHTRANS <= '0';           end generate;
2782 
    xhdl780  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11GatedHTRANS <= M1GATEDHTRANS; end generate;
2783 
    xhdl781  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11GatedHTRANS <= '0';           end generate;
2784 
    xhdl782  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12GatedHTRANS <= M1GATEDHTRANS; end generate;
2785 
    xhdl783  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12GatedHTRANS <= '0';           end generate;
2786 
    xhdl784  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13GatedHTRANS <= M1GATEDHTRANS; end generate;
2787 
    xhdl785  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13GatedHTRANS <= '0';           end generate;
2788 
    xhdl786  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14GatedHTRANS <= M1GATEDHTRANS; end generate;
2789 
    xhdl787  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14GatedHTRANS <= '0';           end generate;
2790 
    xhdl788  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15GatedHTRANS <= M1GATEDHTRANS; end generate;
2791 
    xhdl789  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15GatedHTRANS <= '0';           end generate;
2792 
    xhdl790  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16GatedHTRANS <= M1GATEDHTRANS; end generate;
2793 
    xhdl791  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16GatedHTRANS <= '0';           end generate;
2794 
    xhdl794  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0GatedHWRITE  <= M0GATEDHWRITE; end generate;
2795 
    xhdl795  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0GatedHWRITE  <= '0';           end generate;
2796 
    xhdl796  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1GatedHWRITE  <= M0GATEDHWRITE; end generate;
2797 
    xhdl797  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1GatedHWRITE  <= '0';           end generate;
2798 
    xhdl798  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2GatedHWRITE  <= M0GATEDHWRITE; end generate;
2799 
    xhdl799  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2GatedHWRITE  <= '0';           end generate;
2800 
    xhdl800  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3GatedHWRITE  <= M0GATEDHWRITE; end generate;
2801 
    xhdl801  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3GatedHWRITE  <= '0';           end generate;
2802 
    xhdl802  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4GatedHWRITE  <= M0GATEDHWRITE; end generate;
2803 
    xhdl803  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4GatedHWRITE  <= '0';           end generate;
2804 
    xhdl804  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5GatedHWRITE  <= M0GATEDHWRITE; end generate;
2805 
    xhdl805  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5GatedHWRITE  <= '0';           end generate;
2806 
    xhdl806  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6GatedHWRITE  <= M0GATEDHWRITE; end generate;
2807 
    xhdl807  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6GatedHWRITE  <= '0';           end generate;
2808 
    xhdl808  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7GatedHWRITE  <= M0GATEDHWRITE; end generate;
2809 
    xhdl809  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7GatedHWRITE  <= '0';           end generate;
2810 
    xhdl810  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8GatedHWRITE  <= M0GATEDHWRITE; end generate;
2811 
    xhdl811  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8GatedHWRITE  <= '0';           end generate;
2812 
    xhdl812  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9GatedHWRITE  <= M0GATEDHWRITE; end generate;
2813 
    xhdl813  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9GatedHWRITE  <= '0';           end generate;
2814 
    xhdl814  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10GatedHWRITE <= M0GATEDHWRITE; end generate;
2815 
    xhdl815  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10GatedHWRITE <= '0';           end generate;
2816 
    xhdl816  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11GatedHWRITE <= M0GATEDHWRITE; end generate;
2817 
    xhdl817  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11GatedHWRITE <= '0';           end generate;
2818 
    xhdl818  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12GatedHWRITE <= M0GATEDHWRITE; end generate;
2819 
    xhdl819  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12GatedHWRITE <= '0';           end generate;
2820 
    xhdl820  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13GatedHWRITE <= M0GATEDHWRITE; end generate;
2821 
    xhdl821  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13GatedHWRITE <= '0';           end generate;
2822 
    xhdl822  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14GatedHWRITE <= M0GATEDHWRITE; end generate;
2823 
    xhdl823  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14GatedHWRITE <= '0';           end generate;
2824 
    xhdl824  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15GatedHWRITE <= M0GATEDHWRITE; end generate;
2825 
    xhdl825  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15GatedHWRITE <= '0';           end generate;
2826 
    xhdl826  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16GatedHWRITE <= M0GATEDHWRITE; end generate;
2827 
    xhdl827  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16GatedHWRITE <= '0';           end generate;
2828 
    xhdl830  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0GatedHWRITE  <= M1GATEDHWRITE; end generate;
2829 
    xhdl831  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0GatedHWRITE  <= '0';           end generate;
2830 
    xhdl832  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1GatedHWRITE  <= M1GATEDHWRITE; end generate;
2831 
    xhdl833  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1GatedHWRITE  <= '0';           end generate;
2832 
    xhdl834  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2GatedHWRITE  <= M1GATEDHWRITE; end generate;
2833 
    xhdl835  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2GatedHWRITE  <= '0';           end generate;
2834 
    xhdl836  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3GatedHWRITE  <= M1GATEDHWRITE; end generate;
2835 
    xhdl837  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3GatedHWRITE  <= '0';           end generate;
2836 
    xhdl838  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4GatedHWRITE  <= M1GATEDHWRITE; end generate;
2837 
    xhdl839  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4GatedHWRITE  <= '0';           end generate;
2838 
    xhdl840  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5GatedHWRITE  <= M1GATEDHWRITE; end generate;
2839 
    xhdl841  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5GatedHWRITE  <= '0';           end generate;
2840 
    xhdl842  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6GatedHWRITE  <= M1GATEDHWRITE; end generate;
2841 
    xhdl843  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6GatedHWRITE  <= '0';           end generate;
2842 
    xhdl844  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7GatedHWRITE  <= M1GATEDHWRITE; end generate;
2843 
    xhdl845  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7GatedHWRITE  <= '0';           end generate;
2844 
    xhdl846  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8GatedHWRITE  <= M1GATEDHWRITE; end generate;
2845 
    xhdl847  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8GatedHWRITE  <= '0';           end generate;
2846 
    xhdl848  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9GatedHWRITE  <= M1GATEDHWRITE; end generate;
2847 
    xhdl849  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9GatedHWRITE  <= '0';           end generate;
2848 
    xhdl850  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10GatedHWRITE <= M1GATEDHWRITE; end generate;
2849 
    xhdl851  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10GatedHWRITE <= '0';           end generate;
2850 
    xhdl852  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11GatedHWRITE <= M1GATEDHWRITE; end generate;
2851 
    xhdl853  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11GatedHWRITE <= '0';           end generate;
2852 
    xhdl854  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12GatedHWRITE <= M1GATEDHWRITE; end generate;
2853 
    xhdl855  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12GatedHWRITE <= '0';           end generate;
2854 
    xhdl856  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13GatedHWRITE <= M1GATEDHWRITE; end generate;
2855 
    xhdl857  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13GatedHWRITE <= '0';           end generate;
2856 
    xhdl858  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14GatedHWRITE <= M1GATEDHWRITE; end generate;
2857 
    xhdl859  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14GatedHWRITE <= '0';           end generate;
2858 
    xhdl860  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15GatedHWRITE <= M1GATEDHWRITE; end generate;
2859 
    xhdl861  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15GatedHWRITE <= '0';           end generate;
2860 
    xhdl862  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16GatedHWRITE <= M1GATEDHWRITE; end generate;
2861 
    xhdl863  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16GatedHWRITE <= '0';           end generate;
2862 
    xhdl866  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate m0s0PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2863 
    xhdl867  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate m0s0PrevDataSlaveReady  <= '1';                  end generate;
2864 
    xhdl868  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate m0s1PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2865 
    xhdl869  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate m0s1PrevDataSlaveReady  <= '1';                  end generate;
2866 
    xhdl870  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate m0s2PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2867 
    xhdl871  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate m0s2PrevDataSlaveReady  <= '1';                  end generate;
2868 
    xhdl872  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate m0s3PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2869 
    xhdl873  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate m0s3PrevDataSlaveReady  <= '1';                  end generate;
2870 
    xhdl874  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate m0s4PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2871 
    xhdl875  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate m0s4PrevDataSlaveReady  <= '1';                  end generate;
2872 
    xhdl876  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate m0s5PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2873 
    xhdl877  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate m0s5PrevDataSlaveReady  <= '1';                  end generate;
2874 
    xhdl878  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate m0s6PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2875 
    xhdl879  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate m0s6PrevDataSlaveReady  <= '1';                  end generate;
2876 
    xhdl880  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate m0s7PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2877 
    xhdl881  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate m0s7PrevDataSlaveReady  <= '1';                  end generate;
2878 
    xhdl882  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate m0s8PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2879 
    xhdl883  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate m0s8PrevDataSlaveReady  <= '1';                  end generate;
2880 
    xhdl884  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate m0s9PrevDataSlaveReady  <= m0PrevDataSlaveReady; end generate;
2881 
    xhdl885  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate m0s9PrevDataSlaveReady  <= '1';                  end generate;
2882 
    xhdl886  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate m0s10PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2883 
    xhdl887  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate m0s10PrevDataSlaveReady <= '1';                  end generate;
2884 
    xhdl888  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate m0s11PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2885 
    xhdl889  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate m0s11PrevDataSlaveReady <= '1';                  end generate;
2886 
    xhdl890  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate m0s12PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2887 
    xhdl891  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate m0s12PrevDataSlaveReady <= '1';                  end generate;
2888 
    xhdl892  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate m0s13PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2889 
    xhdl893  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate m0s13PrevDataSlaveReady <= '1';                  end generate;
2890 
    xhdl894  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate m0s14PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2891 
    xhdl895  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate m0s14PrevDataSlaveReady <= '1';                  end generate;
2892 
    xhdl896  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate m0s15PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2893 
    xhdl897  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate m0s15PrevDataSlaveReady <= '1';                  end generate;
2894 
    xhdl898  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate m0s16PrevDataSlaveReady <= m0PrevDataSlaveReady; end generate;
2895 
    xhdl899  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate m0s16PrevDataSlaveReady <= '1';                  end generate;
2896 
    xhdl902  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate m1s0PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2897 
    xhdl903  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate m1s0PrevDataSlaveReady  <= '1';                  end generate;
2898 
    xhdl904  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate m1s1PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2899 
    xhdl905  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate m1s1PrevDataSlaveReady  <= '1';                  end generate;
2900 
    xhdl906  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate m1s2PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2901 
    xhdl907  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate m1s2PrevDataSlaveReady  <= '1';                  end generate;
2902 
    xhdl908  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate m1s3PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2903 
    xhdl909  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate m1s3PrevDataSlaveReady  <= '1';                  end generate;
2904 
    xhdl910  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate m1s4PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2905 
    xhdl911  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate m1s4PrevDataSlaveReady  <= '1';                  end generate;
2906 
    xhdl912  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate m1s5PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2907 
    xhdl913  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate m1s5PrevDataSlaveReady  <= '1';                  end generate;
2908 
    xhdl914  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate m1s6PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2909 
    xhdl915  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate m1s6PrevDataSlaveReady  <= '1';                  end generate;
2910 
    xhdl916  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate m1s7PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2911 
    xhdl917  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate m1s7PrevDataSlaveReady  <= '1';                  end generate;
2912 
    xhdl918  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate m1s8PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2913 
    xhdl919  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate m1s8PrevDataSlaveReady  <= '1';                  end generate;
2914 
    xhdl920  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate m1s9PrevDataSlaveReady  <= m1PrevDataSlaveReady; end generate;
2915 
    xhdl921  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate m1s9PrevDataSlaveReady  <= '1';                  end generate;
2916 
    xhdl922  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate m1s10PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2917 
    xhdl923  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate m1s10PrevDataSlaveReady <= '1';                  end generate;
2918 
    xhdl924  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate m1s11PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2919 
    xhdl925  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate m1s11PrevDataSlaveReady <= '1';                  end generate;
2920 
    xhdl926  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate m1s12PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2921 
    xhdl927  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate m1s12PrevDataSlaveReady <= '1';                  end generate;
2922 
    xhdl928  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate m1s13PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2923 
    xhdl929  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate m1s13PrevDataSlaveReady <= '1';                  end generate;
2924 
    xhdl930  : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate m1s14PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2925 
    xhdl931  : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate m1s14PrevDataSlaveReady <= '1';                  end generate;
2926 
    xhdl932  : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate m1s15PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2927 
    xhdl933  : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate m1s15PrevDataSlaveReady <= '1';                  end generate;
2928 
    xhdl934  : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate m1s16PrevDataSlaveReady <= m1PrevDataSlaveReady; end generate;
2929 
    xhdl935  : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate m1s16PrevDataSlaveReady <= '1';                  end generate;
2930 
    xhdl938  : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate M0_HRDATA_S0  <= HRDATA_S0;                           end generate;
2931 
    xhdl939  : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate M0_HRDATA_S0  <= "00000000000000000000000000000000";  end generate;
2932 
    xhdl940  : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate M0_HRDATA_S1  <= HRDATA_S1;                           end generate;
2933 
    xhdl941  : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate M0_HRDATA_S1  <= "00000000000000000000000000000000";  end generate;
2934 
    xhdl942  : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate M0_HRDATA_S2  <= HRDATA_S2;                           end generate;
2935 
    xhdl943  : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate M0_HRDATA_S2  <= "00000000000000000000000000000000";  end generate;
2936 
    xhdl944  : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate M0_HRDATA_S3  <= HRDATA_S3;                           end generate;
2937 
    xhdl945  : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate M0_HRDATA_S3  <= "00000000000000000000000000000000";  end generate;
2938 
    xhdl946  : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate M0_HRDATA_S4  <= HRDATA_S4;                           end generate;
2939 
    xhdl947  : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate M0_HRDATA_S4  <= "00000000000000000000000000000000";  end generate;
2940 
    xhdl948  : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate M0_HRDATA_S5  <= HRDATA_S5;                           end generate;
2941 
    xhdl949  : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate M0_HRDATA_S5  <= "00000000000000000000000000000000";  end generate;
2942 
    xhdl950  : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate M0_HRDATA_S6  <= HRDATA_S6;                           end generate;
2943 
    xhdl951  : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate M0_HRDATA_S6  <= "00000000000000000000000000000000";  end generate;
2944 
    xhdl952  : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate M0_HRDATA_S7  <= HRDATA_S7;                           end generate;
2945 
    xhdl953  : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate M0_HRDATA_S7  <= "00000000000000000000000000000000";  end generate;
2946 
    xhdl954  : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate M0_HRDATA_S8  <= HRDATA_S8;                           end generate;
2947 
    xhdl955  : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate M0_HRDATA_S8  <= "00000000000000000000000000000000";  end generate;
2948 
    xhdl956  : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate M0_HRDATA_S9  <= HRDATA_S9;                           end generate;
2949 
    xhdl957  : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate M0_HRDATA_S9  <= "00000000000000000000000000000000";  end generate;
2950 
    xhdl958  : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate M0_HRDATA_S10 <= HRDATA_S10;                          end generate;
2951 
    xhdl959  : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate M0_HRDATA_S10 <= "00000000000000000000000000000000";  end generate;
2952 
    xhdl960  : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate M0_HRDATA_S11 <= HRDATA_S11;                          end generate;
2953 
    xhdl961  : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate M0_HRDATA_S11 <= "00000000000000000000000000000000";  end generate;
2954 
    xhdl962  : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate M0_HRDATA_S12 <= HRDATA_S12;                          end generate;
2955 
    xhdl963  : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate M0_HRDATA_S12 <= "00000000000000000000000000000000";  end generate;
2956 
    xhdl964  : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate M0_HRDATA_S13 <= HRDATA_S13;                          end generate;
2957 
    xhdl965  : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate M0_HRDATA_S13 <= "00000000000000000000000000000000";  end generate;
2958 
    xhdl966  : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate M0_HRDATA_S14 <= HRDATA_S14;                          end generate;
2959 
    xhdl967  : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate M0_HRDATA_S14 <= "00000000000000000000000000000000";  end generate;
2960 
    xhdl968  : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate M0_HRDATA_S15 <= HRDATA_S15;                          end generate;
2961 
    xhdl969  : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate M0_HRDATA_S15 <= "00000000000000000000000000000000";  end generate;
2962 
    xhdl970  : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate M0_HRDATA_S16 <= HRDATA_S16;                          end generate;
2963 
    xhdl971  : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate M0_HRDATA_S16 <= "00000000000000000000000000000000";  end generate;
2964 
    xhdl972  : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate M1_HRDATA_S0  <= HRDATA_S0;                           end generate;
2965 
    xhdl973  : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate M1_HRDATA_S0  <= "00000000000000000000000000000000";  end generate;
2966 
    xhdl974  : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate M1_HRDATA_S1  <= HRDATA_S1;                           end generate;
2967 
    xhdl975  : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate M1_HRDATA_S1  <= "00000000000000000000000000000000";  end generate;
2968 
    xhdl976  : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate M1_HRDATA_S2  <= HRDATA_S2;                           end generate;
2969 
    xhdl977  : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate M1_HRDATA_S2  <= "00000000000000000000000000000000";  end generate;
2970 
    xhdl978  : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate M1_HRDATA_S3  <= HRDATA_S3;                           end generate;
2971 
    xhdl979  : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate M1_HRDATA_S3  <= "00000000000000000000000000000000";  end generate;
2972 
    xhdl980  : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate M1_HRDATA_S4  <= HRDATA_S4;                           end generate;
2973 
    xhdl981  : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate M1_HRDATA_S4  <= "00000000000000000000000000000000";  end generate;
2974 
    xhdl982  : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate M1_HRDATA_S5  <= HRDATA_S5;                           end generate;
2975 
    xhdl983  : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate M1_HRDATA_S5  <= "00000000000000000000000000000000";  end generate;
2976 
    xhdl984  : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate M1_HRDATA_S6  <= HRDATA_S6;                           end generate;
2977 
    xhdl985  : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate M1_HRDATA_S6  <= "00000000000000000000000000000000";  end generate;
2978 
    xhdl986  : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate M1_HRDATA_S7  <= HRDATA_S7;                           end generate;
2979 
    xhdl987  : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate M1_HRDATA_S7  <= "00000000000000000000000000000000";  end generate;
2980 
    xhdl988  : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate M1_HRDATA_S8  <= HRDATA_S8;                           end generate;
2981 
    xhdl989  : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate M1_HRDATA_S8  <= "00000000000000000000000000000000";  end generate;
2982 
    xhdl990  : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate M1_HRDATA_S9  <= HRDATA_S9;                           end generate;
2983 
    xhdl991  : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate M1_HRDATA_S9  <= "00000000000000000000000000000000";  end generate;
2984 
    xhdl992  : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate M1_HRDATA_S10 <= HRDATA_S10;                          end generate;
2985 
    xhdl993  : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate M1_HRDATA_S10 <= "00000000000000000000000000000000";  end generate;
2986 
    xhdl994  : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate M1_HRDATA_S11 <= HRDATA_S11;                          end generate;
2987 
    xhdl995  : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate M1_HRDATA_S11 <= "00000000000000000000000000000000";  end generate;
2988 
    xhdl996  : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate M1_HRDATA_S12 <= HRDATA_S12;                          end generate;
2989 
    xhdl997  : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate M1_HRDATA_S12 <= "00000000000000000000000000000000";  end generate;
2990 
    xhdl998  : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate M1_HRDATA_S13 <= HRDATA_S13;                          end generate;
2991 
    xhdl999  : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate M1_HRDATA_S13 <= "00000000000000000000000000000000";  end generate;
2992 
    xhdl1000 : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate M1_HRDATA_S14 <= HRDATA_S14;                          end generate;
2993 
    xhdl1001 : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate M1_HRDATA_S14 <= "00000000000000000000000000000000";  end generate;
2994 
    xhdl1002 : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate M1_HRDATA_S15 <= HRDATA_S15;                          end generate;
2995 
    xhdl1003 : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate M1_HRDATA_S15 <= "00000000000000000000000000000000";  end generate;
2996 
    xhdl1004 : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate M1_HRDATA_S16 <= HRDATA_S16;                          end generate;
2997 
    xhdl1005 : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate M1_HRDATA_S16 <= "00000000000000000000000000000000";  end generate;
2998 
    xhdl1006 : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate HWDATA_M0S0  <= HWDATA_M0;                          end generate;
2999 
    xhdl1007 : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate HWDATA_M0S0  <= "00000000000000000000000000000000"; end generate;
3000 
    xhdl1008 : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate HWDATA_M0S1  <= HWDATA_M0;                          end generate;
3001 
    xhdl1009 : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate HWDATA_M0S1  <= "00000000000000000000000000000000"; end generate;
3002 
    xhdl1010 : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate HWDATA_M0S2  <= HWDATA_M0;                          end generate;
3003 
    xhdl1011 : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate HWDATA_M0S2  <= "00000000000000000000000000000000"; end generate;
3004 
    xhdl1012 : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate HWDATA_M0S3  <= HWDATA_M0;                          end generate;
3005 
    xhdl1013 : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate HWDATA_M0S3  <= "00000000000000000000000000000000"; end generate;
3006 
    xhdl1014 : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate HWDATA_M0S4  <= HWDATA_M0;                          end generate;
3007 
    xhdl1015 : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate HWDATA_M0S4  <= "00000000000000000000000000000000"; end generate;
3008 
    xhdl1016 : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate HWDATA_M0S5  <= HWDATA_M0;                          end generate;
3009 
    xhdl1017 : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate HWDATA_M0S5  <= "00000000000000000000000000000000"; end generate;
3010 
    xhdl1018 : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate HWDATA_M0S6  <= HWDATA_M0;                          end generate;
3011 
    xhdl1019 : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate HWDATA_M0S6  <= "00000000000000000000000000000000"; end generate;
3012 
    xhdl1020 : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate HWDATA_M0S7  <= HWDATA_M0;                          end generate;
3013 
    xhdl1021 : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate HWDATA_M0S7  <= "00000000000000000000000000000000"; end generate;
3014 
    xhdl1022 : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate HWDATA_M0S8  <= HWDATA_M0;                          end generate;
3015 
    xhdl1023 : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate HWDATA_M0S8  <= "00000000000000000000000000000000"; end generate;
3016 
    xhdl1024 : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate HWDATA_M0S9  <= HWDATA_M0;                          end generate;
3017 
    xhdl1025 : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate HWDATA_M0S9  <= "00000000000000000000000000000000"; end generate;
3018 
    xhdl1026 : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate HWDATA_M0S10 <= HWDATA_M0;                          end generate;
3019 
    xhdl1027 : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate HWDATA_M0S10 <= "00000000000000000000000000000000"; end generate;
3020 
    xhdl1028 : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate HWDATA_M0S11 <= HWDATA_M0;                          end generate;
3021 
    xhdl1029 : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate HWDATA_M0S11 <= "00000000000000000000000000000000"; end generate;
3022 
    xhdl1030 : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate HWDATA_M0S12 <= HWDATA_M0;                          end generate;
3023 
    xhdl1031 : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate HWDATA_M0S12 <= "00000000000000000000000000000000"; end generate;
3024 
    xhdl1032 : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate HWDATA_M0S13 <= HWDATA_M0;                          end generate;
3025 
    xhdl1033 : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate HWDATA_M0S13 <= "00000000000000000000000000000000"; end generate;
3026 
    xhdl1034 : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate HWDATA_M0S14 <= HWDATA_M0;                          end generate;
3027 
    xhdl1035 : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate HWDATA_M0S14 <= "00000000000000000000000000000000"; end generate;
3028 
    xhdl1036 : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate HWDATA_M0S15 <= HWDATA_M0;                          end generate;
3029 
    xhdl1037 : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate HWDATA_M0S15 <= "00000000000000000000000000000000"; end generate;
3030 
    xhdl1038 : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate HWDATA_M0S16 <= HWDATA_M0;                          end generate;
3031 
    xhdl1039 : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate HWDATA_M0S16 <= "00000000000000000000000000000000"; end generate;
3032 
    xhdl1042 : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate HWDATA_M1S0  <= HWDATA_M1;                          end generate;
3033 
    xhdl1043 : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate HWDATA_M1S0  <= "00000000000000000000000000000000"; end generate;
3034 
    xhdl1044 : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate HWDATA_M1S1  <= HWDATA_M1;                          end generate;
3035 
    xhdl1045 : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate HWDATA_M1S1  <= "00000000000000000000000000000000"; end generate;
3036 
    xhdl1046 : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate HWDATA_M1S2  <= HWDATA_M1;                          end generate;
3037 
    xhdl1047 : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate HWDATA_M1S2  <= "00000000000000000000000000000000"; end generate;
3038 
    xhdl1048 : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate HWDATA_M1S3  <= HWDATA_M1;                          end generate;
3039 
    xhdl1049 : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate HWDATA_M1S3  <= "00000000000000000000000000000000"; end generate;
3040 
    xhdl1050 : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate HWDATA_M1S4  <= HWDATA_M1;                          end generate;
3041 
    xhdl1051 : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate HWDATA_M1S4  <= "00000000000000000000000000000000"; end generate;
3042 
    xhdl1052 : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate HWDATA_M1S5  <= HWDATA_M1;                          end generate;
3043 
    xhdl1053 : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate HWDATA_M1S5  <= "00000000000000000000000000000000"; end generate;
3044 
    xhdl1054 : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate HWDATA_M1S6  <= HWDATA_M1;                          end generate;
3045 
    xhdl1055 : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate HWDATA_M1S6  <= "00000000000000000000000000000000"; end generate;
3046 
    xhdl1056 : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate HWDATA_M1S7  <= HWDATA_M1;                          end generate;
3047 
    xhdl1057 : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate HWDATA_M1S7  <= "00000000000000000000000000000000"; end generate;
3048 
    xhdl1058 : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate HWDATA_M1S8  <= HWDATA_M1;                          end generate;
3049 
    xhdl1059 : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate HWDATA_M1S8  <= "00000000000000000000000000000000"; end generate;
3050 
    xhdl1060 : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate HWDATA_M1S9  <= HWDATA_M1;                          end generate;
3051 
    xhdl1061 : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate HWDATA_M1S9  <= "00000000000000000000000000000000"; end generate;
3052 
    xhdl1062 : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate HWDATA_M1S10 <= HWDATA_M1;                          end generate;
3053 
    xhdl1063 : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate HWDATA_M1S10 <= "00000000000000000000000000000000"; end generate;
3054 
    xhdl1064 : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate HWDATA_M1S11 <= HWDATA_M1;                          end generate;
3055 
    xhdl1065 : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate HWDATA_M1S11 <= "00000000000000000000000000000000"; end generate;
3056 
    xhdl1066 : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate HWDATA_M1S12 <= HWDATA_M1;                          end generate;
3057 
    xhdl1067 : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate HWDATA_M1S12 <= "00000000000000000000000000000000"; end generate;
3058 
    xhdl1068 : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate HWDATA_M1S13 <= HWDATA_M1;                          end generate;
3059 
    xhdl1069 : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate HWDATA_M1S13 <= "00000000000000000000000000000000"; end generate;
3060 
    xhdl1070 : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate HWDATA_M1S14 <= HWDATA_M1;                          end generate;
3061 
    xhdl1071 : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate HWDATA_M1S14 <= "00000000000000000000000000000000"; end generate;
3062 
    xhdl1072 : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate HWDATA_M1S15 <= HWDATA_M1;                          end generate;
3063 
    xhdl1073 : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate HWDATA_M1S15 <= "00000000000000000000000000000000"; end generate;
3064 
    xhdl1074 : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate HWDATA_M1S16 <= HWDATA_M1;                          end generate;
3065 
    xhdl1075 : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate HWDATA_M1S16 <= "00000000000000000000000000000000"; end generate;
3066 
    xhdl1078 : if (    (M0_AHBSLOTENABLE_slv( 0)) = '1')  generate M0_HREADYOUT_S0  <= HREADYOUT_S0;  end generate;
3067 
    xhdl1079 : if (not((M0_AHBSLOTENABLE_slv( 0)) = '1')) generate M0_HREADYOUT_S0  <= '1';           end generate;
3068 
    xhdl1080 : if (    (M0_AHBSLOTENABLE_slv( 1)) = '1')  generate M0_HREADYOUT_S1  <= HREADYOUT_S1;  end generate;
3069 
    xhdl1081 : if (not((M0_AHBSLOTENABLE_slv( 1)) = '1')) generate M0_HREADYOUT_S1  <= '1';           end generate;
3070 
    xhdl1082 : if (    (M0_AHBSLOTENABLE_slv( 2)) = '1')  generate M0_HREADYOUT_S2  <= HREADYOUT_S2;  end generate;
3071 
    xhdl1083 : if (not((M0_AHBSLOTENABLE_slv( 2)) = '1')) generate M0_HREADYOUT_S2  <= '1';           end generate;
3072 
    xhdl1084 : if (    (M0_AHBSLOTENABLE_slv( 3)) = '1')  generate M0_HREADYOUT_S3  <= HREADYOUT_S3;  end generate;
3073 
    xhdl1085 : if (not((M0_AHBSLOTENABLE_slv( 3)) = '1')) generate M0_HREADYOUT_S3  <= '1';           end generate;
3074 
    xhdl1086 : if (    (M0_AHBSLOTENABLE_slv( 4)) = '1')  generate M0_HREADYOUT_S4  <= HREADYOUT_S4;  end generate;
3075 
    xhdl1087 : if (not((M0_AHBSLOTENABLE_slv( 4)) = '1')) generate M0_HREADYOUT_S4  <= '1';           end generate;
3076 
    xhdl1088 : if (    (M0_AHBSLOTENABLE_slv( 5)) = '1')  generate M0_HREADYOUT_S5  <= HREADYOUT_S5;  end generate;
3077 
    xhdl1089 : if (not((M0_AHBSLOTENABLE_slv( 5)) = '1')) generate M0_HREADYOUT_S5  <= '1';           end generate;
3078 
    xhdl1090 : if (    (M0_AHBSLOTENABLE_slv( 6)) = '1')  generate M0_HREADYOUT_S6  <= HREADYOUT_S6;  end generate;
3079 
    xhdl1091 : if (not((M0_AHBSLOTENABLE_slv( 6)) = '1')) generate M0_HREADYOUT_S6  <= '1';           end generate;
3080 
    xhdl1092 : if (    (M0_AHBSLOTENABLE_slv( 7)) = '1')  generate M0_HREADYOUT_S7  <= HREADYOUT_S7;  end generate;
3081 
    xhdl1093 : if (not((M0_AHBSLOTENABLE_slv( 7)) = '1')) generate M0_HREADYOUT_S7  <= '1';           end generate;
3082 
    xhdl1094 : if (    (M0_AHBSLOTENABLE_slv( 8)) = '1')  generate M0_HREADYOUT_S8  <= HREADYOUT_S8;  end generate;
3083 
    xhdl1095 : if (not((M0_AHBSLOTENABLE_slv( 8)) = '1')) generate M0_HREADYOUT_S8  <= '1';           end generate;
3084 
    xhdl1096 : if (    (M0_AHBSLOTENABLE_slv( 9)) = '1')  generate M0_HREADYOUT_S9  <= HREADYOUT_S9;  end generate;
3085 
    xhdl1097 : if (not((M0_AHBSLOTENABLE_slv( 9)) = '1')) generate M0_HREADYOUT_S9  <= '1';           end generate;
3086 
    xhdl1098 : if (    (M0_AHBSLOTENABLE_slv(10)) = '1')  generate M0_HREADYOUT_S10 <= HREADYOUT_S10; end generate;
3087 
    xhdl1099 : if (not((M0_AHBSLOTENABLE_slv(10)) = '1')) generate M0_HREADYOUT_S10 <= '1';           end generate;
3088 
    xhdl1100 : if (    (M0_AHBSLOTENABLE_slv(11)) = '1')  generate M0_HREADYOUT_S11 <= HREADYOUT_S11; end generate;
3089 
    xhdl1101 : if (not((M0_AHBSLOTENABLE_slv(11)) = '1')) generate M0_HREADYOUT_S11 <= '1';           end generate;
3090 
    xhdl1102 : if (    (M0_AHBSLOTENABLE_slv(12)) = '1')  generate M0_HREADYOUT_S12 <= HREADYOUT_S12; end generate;
3091 
    xhdl1103 : if (not((M0_AHBSLOTENABLE_slv(12)) = '1')) generate M0_HREADYOUT_S12 <= '1';           end generate;
3092 
    xhdl1104 : if (    (M0_AHBSLOTENABLE_slv(13)) = '1')  generate M0_HREADYOUT_S13 <= HREADYOUT_S13; end generate;
3093 
    xhdl1105 : if (not((M0_AHBSLOTENABLE_slv(13)) = '1')) generate M0_HREADYOUT_S13 <= '1';           end generate;
3094 
    xhdl1106 : if (    (M0_AHBSLOTENABLE_slv(14)) = '1')  generate M0_HREADYOUT_S14 <= HREADYOUT_S14; end generate;
3095 
    xhdl1107 : if (not((M0_AHBSLOTENABLE_slv(14)) = '1')) generate M0_HREADYOUT_S14 <= '1';           end generate;
3096 
    xhdl1108 : if (    (M0_AHBSLOTENABLE_slv(15)) = '1')  generate M0_HREADYOUT_S15 <= HREADYOUT_S15; end generate;
3097 
    xhdl1109 : if (not((M0_AHBSLOTENABLE_slv(15)) = '1')) generate M0_HREADYOUT_S15 <= '1';           end generate;
3098 
    xhdl1110 : if (    (M0_AHBSLOTENABLE_slv(16)) = '1')  generate M0_HREADYOUT_S16 <= HREADYOUT_S16; end generate;
3099 
    xhdl1111 : if (not((M0_AHBSLOTENABLE_slv(16)) = '1')) generate M0_HREADYOUT_S16 <= '1';           end generate;
3100 
    xhdl1114 : if (    (M1_AHBSLOTENABLE_slv( 0)) = '1')  generate M1_HREADYOUT_S0  <= HREADYOUT_S0;  end generate;
3101 
    xhdl1115 : if (not((M1_AHBSLOTENABLE_slv( 0)) = '1')) generate M1_HREADYOUT_S0  <= '1';           end generate;
3102 
    xhdl1116 : if (    (M1_AHBSLOTENABLE_slv( 1)) = '1')  generate M1_HREADYOUT_S1  <= HREADYOUT_S1;  end generate;
3103 
    xhdl1117 : if (not((M1_AHBSLOTENABLE_slv( 1)) = '1')) generate M1_HREADYOUT_S1  <= '1';           end generate;
3104 
    xhdl1118 : if (    (M1_AHBSLOTENABLE_slv( 2)) = '1')  generate M1_HREADYOUT_S2  <= HREADYOUT_S2;  end generate;
3105 
    xhdl1119 : if (not((M1_AHBSLOTENABLE_slv( 2)) = '1')) generate M1_HREADYOUT_S2  <= '1';           end generate;
3106 
    xhdl1120 : if (    (M1_AHBSLOTENABLE_slv( 3)) = '1')  generate M1_HREADYOUT_S3  <= HREADYOUT_S3;  end generate;
3107 
    xhdl1121 : if (not((M1_AHBSLOTENABLE_slv( 3)) = '1')) generate M1_HREADYOUT_S3  <= '1';           end generate;
3108 
    xhdl1122 : if (    (M1_AHBSLOTENABLE_slv( 4)) = '1')  generate M1_HREADYOUT_S4  <= HREADYOUT_S4;  end generate;
3109 
    xhdl1123 : if (not((M1_AHBSLOTENABLE_slv( 4)) = '1')) generate M1_HREADYOUT_S4  <= '1';           end generate;
3110 
    xhdl1124 : if (    (M1_AHBSLOTENABLE_slv( 5)) = '1')  generate M1_HREADYOUT_S5  <= HREADYOUT_S5;  end generate;
3111 
    xhdl1125 : if (not((M1_AHBSLOTENABLE_slv( 5)) = '1')) generate M1_HREADYOUT_S5  <= '1';           end generate;
3112 
    xhdl1126 : if (    (M1_AHBSLOTENABLE_slv( 6)) = '1')  generate M1_HREADYOUT_S6  <= HREADYOUT_S6;  end generate;
3113 
    xhdl1127 : if (not((M1_AHBSLOTENABLE_slv( 6)) = '1')) generate M1_HREADYOUT_S6  <= '1';           end generate;
3114 
    xhdl1128 : if (    (M1_AHBSLOTENABLE_slv( 7)) = '1')  generate M1_HREADYOUT_S7  <= HREADYOUT_S7;  end generate;
3115 
    xhdl1129 : if (not((M1_AHBSLOTENABLE_slv( 7)) = '1')) generate M1_HREADYOUT_S7  <= '1';           end generate;
3116 
    xhdl1130 : if (    (M1_AHBSLOTENABLE_slv( 8)) = '1')  generate M1_HREADYOUT_S8  <= HREADYOUT_S8;  end generate;
3117 
    xhdl1131 : if (not((M1_AHBSLOTENABLE_slv( 8)) = '1')) generate M1_HREADYOUT_S8  <= '1';           end generate;
3118 
    xhdl1132 : if (    (M1_AHBSLOTENABLE_slv( 9)) = '1')  generate M1_HREADYOUT_S9  <= HREADYOUT_S9;  end generate;
3119 
    xhdl1133 : if (not((M1_AHBSLOTENABLE_slv( 9)) = '1')) generate M1_HREADYOUT_S9  <= '1';           end generate;
3120 
    xhdl1134 : if (    (M1_AHBSLOTENABLE_slv(10)) = '1')  generate M1_HREADYOUT_S10 <= HREADYOUT_S10; end generate;
3121 
    xhdl1135 : if (not((M1_AHBSLOTENABLE_slv(10)) = '1')) generate M1_HREADYOUT_S10 <= '1';           end generate;
3122 
    xhdl1136 : if (    (M1_AHBSLOTENABLE_slv(11)) = '1')  generate M1_HREADYOUT_S11 <= HREADYOUT_S11; end generate;
3123 
    xhdl1137 : if (not((M1_AHBSLOTENABLE_slv(11)) = '1')) generate M1_HREADYOUT_S11 <= '1';           end generate;
3124 
    xhdl1138 : if (    (M1_AHBSLOTENABLE_slv(12)) = '1')  generate M1_HREADYOUT_S12 <= HREADYOUT_S12; end generate;
3125 
    xhdl1139 : if (not((M1_AHBSLOTENABLE_slv(12)) = '1')) generate M1_HREADYOUT_S12 <= '1';           end generate;
3126 
    xhdl1140 : if (    (M1_AHBSLOTENABLE_slv(13)) = '1')  generate M1_HREADYOUT_S13 <= HREADYOUT_S13; end generate;
3127 
    xhdl1141 : if (not((M1_AHBSLOTENABLE_slv(13)) = '1')) generate M1_HREADYOUT_S13 <= '1';           end generate;
3128 
    xhdl1142 : if (    (M1_AHBSLOTENABLE_slv(14)) = '1')  generate M1_HREADYOUT_S14 <= HREADYOUT_S14; end generate;
3129 
    xhdl1143 : if (not((M1_AHBSLOTENABLE_slv(14)) = '1')) generate M1_HREADYOUT_S14 <= '1';           end generate;
3130 
    xhdl1144 : if (    (M1_AHBSLOTENABLE_slv(15)) = '1')  generate M1_HREADYOUT_S15 <= HREADYOUT_S15; end generate;
3131 
    xhdl1145 : if (not((M1_AHBSLOTENABLE_slv(15)) = '1')) generate M1_HREADYOUT_S15 <= '1';           end generate;
3132 
    xhdl1146 : if (    (M1_AHBSLOTENABLE_slv(16)) = '1')  generate M1_HREADYOUT_S16 <= HREADYOUT_S16; end generate;
3133 
    xhdl1147 : if (not((M1_AHBSLOTENABLE_slv(16)) = '1')) generate M1_HREADYOUT_S16 <= '1';           end generate;
3134 
 
3135 
 
3136 
    yhdl146  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m2AddrReady_int  <= s0m2AddrReady;  end generate;
3137 
    yhdl147  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m2AddrReady_int  <= '1';            end generate;
3138 
    yhdl148  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m2AddrReady_int  <= s1m2AddrReady;  end generate;
3139 
    yhdl149  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m2AddrReady_int  <= '1';            end generate;
3140 
    yhdl150  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m2AddrReady_int  <= s2m2AddrReady;  end generate;
3141 
    yhdl151  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m2AddrReady_int  <= '1';            end generate;
3142 
    yhdl152  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m2AddrReady_int  <= s3m2AddrReady;  end generate;
3143 
    yhdl153  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m2AddrReady_int  <= '1';            end generate;
3144 
    yhdl154  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m2AddrReady_int  <= s4m2AddrReady;  end generate;
3145 
    yhdl155  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m2AddrReady_int  <= '1';            end generate;
3146 
    yhdl156  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m2AddrReady_int  <= s5m2AddrReady;  end generate;
3147 
    yhdl157  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m2AddrReady_int  <= '1';            end generate;
3148 
    yhdl158  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m2AddrReady_int  <= s6m2AddrReady;  end generate;
3149 
    yhdl159  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m2AddrReady_int  <= '1';            end generate;
3150 
    yhdl160  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m2AddrReady_int  <= s7m2AddrReady;  end generate;
3151 
    yhdl161  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m2AddrReady_int  <= '1';            end generate;
3152 
    yhdl162  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m2AddrReady_int  <= s8m2AddrReady;  end generate;
3153 
    yhdl163  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m2AddrReady_int  <= '1';            end generate;
3154 
    yhdl164  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m2AddrReady_int  <= s9m2AddrReady;  end generate;
3155 
    yhdl165  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m2AddrReady_int  <= '1';            end generate;
3156 
    yhdl166  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate s10m2AddrReady_int <= s10m2AddrReady; end generate;
3157 
    yhdl167  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate s10m2AddrReady_int <= '1';            end generate;
3158 
    yhdl168  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate s11m2AddrReady_int <= s11m2AddrReady; end generate;
3159 
    yhdl169  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate s11m2AddrReady_int <= '1';            end generate;
3160 
    yhdl170  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate s12m2AddrReady_int <= s12m2AddrReady; end generate;
3161 
    yhdl171  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate s12m2AddrReady_int <= '1';            end generate;
3162 
    yhdl172  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate s13m2AddrReady_int <= s13m2AddrReady; end generate;
3163 
    yhdl173  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate s13m2AddrReady_int <= '1';            end generate;
3164 
    yhdl174  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate s14m2AddrReady_int <= s14m2AddrReady; end generate;
3165 
    yhdl175  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate s14m2AddrReady_int <= '1';            end generate;
3166 
    yhdl176  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate s15m2AddrReady_int <= s15m2AddrReady; end generate;
3167 
    yhdl177  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate s15m2AddrReady_int <= '1';            end generate;
3168 
    yhdl178  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate s16m2AddrReady_int <= s16m2AddrReady; end generate;
3169 
    yhdl179  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate s16m2AddrReady_int <= '1';            end generate;
3170 
    yhdl182  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m3AddrReady_int  <= s0m3AddrReady;  end generate;
3171 
    yhdl183  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m3AddrReady_int  <= '1';            end generate;
3172 
    yhdl184  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m3AddrReady_int  <= s1m3AddrReady;  end generate;
3173 
    yhdl185  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m3AddrReady_int  <= '1';            end generate;
3174 
    yhdl186  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m3AddrReady_int  <= s2m3AddrReady;  end generate;
3175 
    yhdl187  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m3AddrReady_int  <= '1';            end generate;
3176 
    yhdl188  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m3AddrReady_int  <= s3m3AddrReady;  end generate;
3177 
    yhdl189  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m3AddrReady_int  <= '1';            end generate;
3178 
    yhdl190  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m3AddrReady_int  <= s4m3AddrReady;  end generate;
3179 
    yhdl191  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m3AddrReady_int  <= '1';            end generate;
3180 
    yhdl192  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m3AddrReady_int  <= s5m3AddrReady;  end generate;
3181 
    yhdl193  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m3AddrReady_int  <= '1';            end generate;
3182 
    yhdl194  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m3AddrReady_int  <= s6m3AddrReady;  end generate;
3183 
    yhdl195  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m3AddrReady_int  <= '1';            end generate;
3184 
    yhdl196  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m3AddrReady_int  <= s7m3AddrReady;  end generate;
3185 
    yhdl197  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m3AddrReady_int  <= '1';            end generate;
3186 
    yhdl198  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m3AddrReady_int  <= s8m3AddrReady;  end generate;
3187 
    yhdl199  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m3AddrReady_int  <= '1';            end generate;
3188 
    yhdl200  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m3AddrReady_int  <= s9m3AddrReady;  end generate;
3189 
    yhdl201  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m3AddrReady_int  <= '1';            end generate;
3190 
    yhdl202  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate s10m3AddrReady_int <= s10m3AddrReady; end generate;
3191 
    yhdl203  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate s10m3AddrReady_int <= '1';            end generate;
3192 
    yhdl204  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate s11m3AddrReady_int <= s11m3AddrReady; end generate;
3193 
    yhdl205  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate s11m3AddrReady_int <= '1';            end generate;
3194 
    yhdl206  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate s12m3AddrReady_int <= s12m3AddrReady; end generate;
3195 
    yhdl207  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate s12m3AddrReady_int <= '1';            end generate;
3196 
    yhdl208  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate s13m3AddrReady_int <= s13m3AddrReady; end generate;
3197 
    yhdl209  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate s13m3AddrReady_int <= '1';            end generate;
3198 
    yhdl210  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate s14m3AddrReady_int <= s14m3AddrReady; end generate;
3199 
    yhdl211  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate s14m3AddrReady_int <= '1';            end generate;
3200 
    yhdl212  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate s15m3AddrReady_int <= s15m3AddrReady; end generate;
3201 
    yhdl213  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate s15m3AddrReady_int <= '1';            end generate;
3202 
    yhdl214  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate s16m3AddrReady_int <= s16m3AddrReady; end generate;
3203 
    yhdl215  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate s16m3AddrReady_int <= '1';            end generate;
3204 
    yhdl218  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m2DataReady_int  <= s0m2DataReady;  end generate;
3205 
    yhdl219  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m2DataReady_int  <= '1';            end generate;
3206 
    yhdl220  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m2DataReady_int  <= s1m2DataReady;  end generate;
3207 
    yhdl221  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m2DataReady_int  <= '1';            end generate;
3208 
    yhdl222  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m2DataReady_int  <= s2m2DataReady;  end generate;
3209 
    yhdl223  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m2DataReady_int  <= '1';            end generate;
3210 
    yhdl224  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m2DataReady_int  <= s3m2DataReady;  end generate;
3211 
    yhdl225  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m2DataReady_int  <= '1';            end generate;
3212 
    yhdl226  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m2DataReady_int  <= s4m2DataReady;  end generate;
3213 
    yhdl227  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m2DataReady_int  <= '1';            end generate;
3214 
    yhdl228  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m2DataReady_int  <= s5m2DataReady;  end generate;
3215 
    yhdl229  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m2DataReady_int  <= '1';            end generate;
3216 
    yhdl230  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m2DataReady_int  <= s6m2DataReady;  end generate;
3217 
    yhdl231  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m2DataReady_int  <= '1';            end generate;
3218 
    yhdl232  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m2DataReady_int  <= s7m2DataReady;  end generate;
3219 
    yhdl233  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m2DataReady_int  <= '1';            end generate;
3220 
    yhdl234  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m2DataReady_int  <= s8m2DataReady;  end generate;
3221 
    yhdl235  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m2DataReady_int  <= '1';            end generate;
3222 
    yhdl236  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m2DataReady_int  <= s9m2DataReady;  end generate;
3223 
    yhdl237  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m2DataReady_int  <= '1';            end generate;
3224 
    yhdl238  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate s10m2DataReady_int <= s10m2DataReady; end generate;
3225 
    yhdl239  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate s10m2DataReady_int <= '1';            end generate;
3226 
    yhdl240  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate s11m2DataReady_int <= s11m2DataReady; end generate;
3227 
    yhdl241  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate s11m2DataReady_int <= '1';            end generate;
3228 
    yhdl242  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate s12m2DataReady_int <= s12m2DataReady; end generate;
3229 
    yhdl243  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate s12m2DataReady_int <= '1';            end generate;
3230 
    yhdl244  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate s13m2DataReady_int <= s13m2DataReady; end generate;
3231 
    yhdl245  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate s13m2DataReady_int <= '1';            end generate;
3232 
    yhdl246  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate s14m2DataReady_int <= s14m2DataReady; end generate;
3233 
    yhdl247  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate s14m2DataReady_int <= '1';            end generate;
3234 
    yhdl248  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate s15m2DataReady_int <= s15m2DataReady; end generate;
3235 
    yhdl249  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate s15m2DataReady_int <= '1';            end generate;
3236 
    yhdl250  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate s16m2DataReady_int <= s16m2DataReady; end generate;
3237 
    yhdl251  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate s16m2DataReady_int <= '1';            end generate;
3238 
    yhdl254  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m3DataReady_int  <= s0m3DataReady;  end generate;
3239 
    yhdl255  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m3DataReady_int  <= '1';            end generate;
3240 
    yhdl256  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m3DataReady_int  <= s1m3DataReady;  end generate;
3241 
    yhdl257  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m3DataReady_int  <= '1';            end generate;
3242 
    yhdl258  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m3DataReady_int  <= s2m3DataReady;  end generate;
3243 
    yhdl259  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m3DataReady_int  <= '1';            end generate;
3244 
    yhdl260  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m3DataReady_int  <= s3m3DataReady;  end generate;
3245 
    yhdl261  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m3DataReady_int  <= '1';            end generate;
3246 
    yhdl262  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m3DataReady_int  <= s4m3DataReady;  end generate;
3247 
    yhdl263  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m3DataReady_int  <= '1';            end generate;
3248 
    yhdl264  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m3DataReady_int  <= s5m3DataReady;  end generate;
3249 
    yhdl265  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m3DataReady_int  <= '1';            end generate;
3250 
    yhdl266  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m3DataReady_int  <= s6m3DataReady;  end generate;
3251 
    yhdl267  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m3DataReady_int  <= '1';            end generate;
3252 
    yhdl268  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m3DataReady_int  <= s7m3DataReady;  end generate;
3253 
    yhdl269  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m3DataReady_int  <= '1';            end generate;
3254 
    yhdl270  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m3DataReady_int  <= s8m3DataReady;  end generate;
3255 
    yhdl271  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m3DataReady_int  <= '1';            end generate;
3256 
    yhdl272  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m3DataReady_int  <= s9m3DataReady;  end generate;
3257 
    yhdl273  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m3DataReady_int  <= '1';            end generate;
3258 
    yhdl274  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate s10m3DataReady_int <= s10m3DataReady; end generate;
3259 
    yhdl275  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate s10m3DataReady_int <= '1';            end generate;
3260 
    yhdl276  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate s11m3DataReady_int <= s11m3DataReady; end generate;
3261 
    yhdl277  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate s11m3DataReady_int <= '1';            end generate;
3262 
    yhdl278  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate s12m3DataReady_int <= s12m3DataReady; end generate;
3263 
    yhdl279  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate s12m3DataReady_int <= '1';            end generate;
3264 
    yhdl280  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate s13m3DataReady_int <= s13m3DataReady; end generate;
3265 
    yhdl281  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate s13m3DataReady_int <= '1';            end generate;
3266 
    yhdl282  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate s14m3DataReady_int <= s14m3DataReady; end generate;
3267 
    yhdl283  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate s14m3DataReady_int <= '1';            end generate;
3268 
    yhdl284  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate s15m3DataReady_int <= s15m3DataReady; end generate;
3269 
    yhdl285  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate s15m3DataReady_int <= '1';            end generate;
3270 
    yhdl286  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate s16m3DataReady_int <= s16m3DataReady; end generate;
3271 
    yhdl287  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate s16m3DataReady_int <= '1';            end generate;
3272 
    yhdl290  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m2HResp_int  <= s0m2HResp;  end generate;
3273 
    yhdl291  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m2HResp_int  <= '0';        end generate;
3274 
    yhdl292  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m2HResp_int  <= s1m2HResp;  end generate;
3275 
    yhdl293  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m2HResp_int  <= '0';        end generate;
3276 
    yhdl294  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m2HResp_int  <= s2m2HResp;  end generate;
3277 
    yhdl295  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m2HResp_int  <= '0';        end generate;
3278 
    yhdl296  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m2HResp_int  <= s3m2HResp;  end generate;
3279 
    yhdl297  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m2HResp_int  <= '0';        end generate;
3280 
    yhdl298  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m2HResp_int  <= s4m2HResp;  end generate;
3281 
    yhdl299  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m2HResp_int  <= '0';        end generate;
3282 
    yhdl300  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m2HResp_int  <= s5m2HResp;  end generate;
3283 
    yhdl301  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m2HResp_int  <= '0';        end generate;
3284 
    yhdl302  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m2HResp_int  <= s6m2HResp;  end generate;
3285 
    yhdl303  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m2HResp_int  <= '0';        end generate;
3286 
    yhdl304  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m2HResp_int  <= s7m2HResp;  end generate;
3287 
    yhdl305  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m2HResp_int  <= '0';        end generate;
3288 
    yhdl306  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m2HResp_int  <= s8m2HResp;  end generate;
3289 
    yhdl307  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m2HResp_int  <= '0';        end generate;
3290 
    yhdl308  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m2HResp_int  <= s9m2HResp;  end generate;
3291 
    yhdl309  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m2HResp_int  <= '0';        end generate;
3292 
    yhdl310  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate s10m2HResp_int <= s10m2HResp; end generate;
3293 
    yhdl311  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate s10m2HResp_int <= '0';        end generate;
3294 
    yhdl312  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate s11m2HResp_int <= s11m2HResp; end generate;
3295 
    yhdl313  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate s11m2HResp_int <= '0';        end generate;
3296 
    yhdl314  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate s12m2HResp_int <= s12m2HResp; end generate;
3297 
    yhdl315  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate s12m2HResp_int <= '0';        end generate;
3298 
    yhdl316  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate s13m2HResp_int <= s13m2HResp; end generate;
3299 
    yhdl317  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate s13m2HResp_int <= '0';        end generate;
3300 
    yhdl318  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate s14m2HResp_int <= s14m2HResp; end generate;
3301 
    yhdl319  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate s14m2HResp_int <= '0';        end generate;
3302 
    yhdl320  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate s15m2HResp_int <= s15m2HResp; end generate;
3303 
    yhdl321  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate s15m2HResp_int <= '0';        end generate;
3304 
    yhdl322  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate s16m2HResp_int <= s16m2HResp; end generate;
3305 
    yhdl323  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate s16m2HResp_int <= '0';        end generate;
3306 
    yhdl326  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate s0m3HResp_int  <= s0m3HResp;  end generate;
3307 
    yhdl327  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate s0m3HResp_int  <= '0';        end generate;
3308 
    yhdl328  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate s1m3HResp_int  <= s1m3HResp;  end generate;
3309 
    yhdl329  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate s1m3HResp_int  <= '0';        end generate;
3310 
    yhdl330  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate s2m3HResp_int  <= s2m3HResp;  end generate;
3311 
    yhdl331  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate s2m3HResp_int  <= '0';        end generate;
3312 
    yhdl332  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate s3m3HResp_int  <= s3m3HResp;  end generate;
3313 
    yhdl333  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate s3m3HResp_int  <= '0';        end generate;
3314 
    yhdl334  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate s4m3HResp_int  <= s4m3HResp;  end generate;
3315 
    yhdl335  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate s4m3HResp_int  <= '0';        end generate;
3316 
    yhdl336  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate s5m3HResp_int  <= s5m3HResp;  end generate;
3317 
    yhdl337  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate s5m3HResp_int  <= '0';        end generate;
3318 
    yhdl338  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate s6m3HResp_int  <= s6m3HResp;  end generate;
3319 
    yhdl339  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate s6m3HResp_int  <= '0';        end generate;
3320 
    yhdl340  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate s7m3HResp_int  <= s7m3HResp;  end generate;
3321 
    yhdl341  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate s7m3HResp_int  <= '0';        end generate;
3322 
    yhdl342  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate s8m3HResp_int  <= s8m3HResp;  end generate;
3323 
    yhdl343  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate s8m3HResp_int  <= '0';        end generate;
3324 
    yhdl344  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate s9m3HResp_int  <= s9m3HResp;  end generate;
3325 
    yhdl345  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate s9m3HResp_int  <= '0';        end generate;
3326 
    yhdl346  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate s10m3HResp_int <= s10m3HResp; end generate;
3327 
    yhdl347  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate s10m3HResp_int <= '0';        end generate;
3328 
    yhdl348  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate s11m3HResp_int <= s11m3HResp; end generate;
3329 
    yhdl349  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate s11m3HResp_int <= '0';        end generate;
3330 
    yhdl350  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate s12m3HResp_int <= s12m3HResp; end generate;
3331 
    yhdl351  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate s12m3HResp_int <= '0';        end generate;
3332 
    yhdl352  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate s13m3HResp_int <= s13m3HResp; end generate;
3333 
    yhdl353  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate s13m3HResp_int <= '0';        end generate;
3334 
    yhdl354  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate s14m3HResp_int <= s14m3HResp; end generate;
3335 
    yhdl355  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate s14m3HResp_int <= '0';        end generate;
3336 
    yhdl356  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate s15m3HResp_int <= s15m3HResp; end generate;
3337 
    yhdl357  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate s15m3HResp_int <= '0';        end generate;
3338 
    yhdl358  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate s16m3HResp_int <= s16m3HResp; end generate;
3339 
    yhdl359  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate s16m3HResp_int <= '0';        end generate;
3340 
    yhdl362  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0AddrSel_int  <= m2s0AddrSel;  end generate;
3341 
    yhdl363  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0AddrSel_int  <= '0';          end generate;
3342 
    yhdl364  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1AddrSel_int  <= m2s1AddrSel;  end generate;
3343 
    yhdl365  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1AddrSel_int  <= '0';          end generate;
3344 
    yhdl366  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2AddrSel_int  <= m2s2AddrSel;  end generate;
3345 
    yhdl367  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2AddrSel_int  <= '0';          end generate;
3346 
    yhdl368  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3AddrSel_int  <= m2s3AddrSel;  end generate;
3347 
    yhdl369  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3AddrSel_int  <= '0';          end generate;
3348 
    yhdl370  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4AddrSel_int  <= m2s4AddrSel;  end generate;
3349 
    yhdl371  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4AddrSel_int  <= '0';          end generate;
3350 
    yhdl372  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5AddrSel_int  <= m2s5AddrSel;  end generate;
3351 
    yhdl373  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5AddrSel_int  <= '0';          end generate;
3352 
    yhdl374  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6AddrSel_int  <= m2s6AddrSel;  end generate;
3353 
    yhdl375  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6AddrSel_int  <= '0';          end generate;
3354 
    yhdl376  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7AddrSel_int  <= m2s7AddrSel;  end generate;
3355 
    yhdl377  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7AddrSel_int  <= '0';          end generate;
3356 
    yhdl378  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8AddrSel_int  <= m2s8AddrSel;  end generate;
3357 
    yhdl379  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8AddrSel_int  <= '0';          end generate;
3358 
    yhdl380  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9AddrSel_int  <= m2s9AddrSel;  end generate;
3359 
    yhdl381  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9AddrSel_int  <= '0';          end generate;
3360 
    yhdl382  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10AddrSel_int <= m2s10AddrSel; end generate;
3361 
    yhdl383  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10AddrSel_int <= '0';          end generate;
3362 
    yhdl384  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11AddrSel_int <= m2s11AddrSel; end generate;
3363 
    yhdl385  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11AddrSel_int <= '0';          end generate;
3364 
    yhdl386  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12AddrSel_int <= m2s12AddrSel; end generate;
3365 
    yhdl387  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12AddrSel_int <= '0';          end generate;
3366 
    yhdl388  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13AddrSel_int <= m2s13AddrSel; end generate;
3367 
    yhdl389  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13AddrSel_int <= '0';          end generate;
3368 
    yhdl390  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14AddrSel_int <= m2s14AddrSel; end generate;
3369 
    yhdl391  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14AddrSel_int <= '0';          end generate;
3370 
    yhdl392  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15AddrSel_int <= m2s15AddrSel; end generate;
3371 
    yhdl393  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15AddrSel_int <= '0';          end generate;
3372 
    yhdl394  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16AddrSel_int <= m2s16AddrSel; end generate;
3373 
    yhdl395  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16AddrSel_int <= '0';          end generate;
3374 
    yhdl398  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0AddrSel_int  <= m3s0AddrSel;  end generate;
3375 
    yhdl399  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0AddrSel_int  <= '0';          end generate;
3376 
    yhdl400  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1AddrSel_int  <= m3s1AddrSel;  end generate;
3377 
    yhdl401  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1AddrSel_int  <= '0';          end generate;
3378 
    yhdl402  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2AddrSel_int  <= m3s2AddrSel;  end generate;
3379 
    yhdl403  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2AddrSel_int  <= '0';          end generate;
3380 
    yhdl404  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3AddrSel_int  <= m3s3AddrSel;  end generate;
3381 
    yhdl405  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3AddrSel_int  <= '0';          end generate;
3382 
    yhdl406  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4AddrSel_int  <= m3s4AddrSel;  end generate;
3383 
    yhdl407  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4AddrSel_int  <= '0';          end generate;
3384 
    yhdl408  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5AddrSel_int  <= m3s5AddrSel;  end generate;
3385 
    yhdl409  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5AddrSel_int  <= '0';          end generate;
3386 
    yhdl410  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6AddrSel_int  <= m3s6AddrSel;  end generate;
3387 
    yhdl411  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6AddrSel_int  <= '0';          end generate;
3388 
    yhdl412  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7AddrSel_int  <= m3s7AddrSel;  end generate;
3389 
    yhdl413  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7AddrSel_int  <= '0';          end generate;
3390 
    yhdl414  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8AddrSel_int  <= m3s8AddrSel;  end generate;
3391 
    yhdl415  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8AddrSel_int  <= '0';          end generate;
3392 
    yhdl416  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9AddrSel_int  <= m3s9AddrSel;  end generate;
3393 
    yhdl417  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9AddrSel_int  <= '0';          end generate;
3394 
    yhdl418  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10AddrSel_int <= m3s10AddrSel; end generate;
3395 
    yhdl419  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10AddrSel_int <= '0';          end generate;
3396 
    yhdl420  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11AddrSel_int <= m3s11AddrSel; end generate;
3397 
    yhdl421  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11AddrSel_int <= '0';          end generate;
3398 
    yhdl422  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12AddrSel_int <= m3s12AddrSel; end generate;
3399 
    yhdl423  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12AddrSel_int <= '0';          end generate;
3400 
    yhdl424  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13AddrSel_int <= m3s13AddrSel; end generate;
3401 
    yhdl425  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13AddrSel_int <= '0';          end generate;
3402 
    yhdl426  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14AddrSel_int <= m3s14AddrSel; end generate;
3403 
    yhdl427  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14AddrSel_int <= '0';          end generate;
3404 
    yhdl428  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15AddrSel_int <= m3s15AddrSel; end generate;
3405 
    yhdl429  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15AddrSel_int <= '0';          end generate;
3406 
    yhdl430  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16AddrSel_int <= m3s16AddrSel; end generate;
3407 
    yhdl431  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16AddrSel_int <= '0';          end generate;
3408 
    yhdl434  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0DataSel_int  <= m2s0DataSel;  end generate;
3409 
    yhdl435  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0DataSel_int  <= '0';          end generate;
3410 
    yhdl436  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1DataSel_int  <= m2s1DataSel;  end generate;
3411 
    yhdl437  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1DataSel_int  <= '0';          end generate;
3412 
    yhdl438  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2DataSel_int  <= m2s2DataSel;  end generate;
3413 
    yhdl439  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2DataSel_int  <= '0';          end generate;
3414 
    yhdl440  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3DataSel_int  <= m2s3DataSel;  end generate;
3415 
    yhdl441  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3DataSel_int  <= '0';          end generate;
3416 
    yhdl442  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4DataSel_int  <= m2s4DataSel;  end generate;
3417 
    yhdl443  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4DataSel_int  <= '0';          end generate;
3418 
    yhdl444  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5DataSel_int  <= m2s5DataSel;  end generate;
3419 
    yhdl445  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5DataSel_int  <= '0';          end generate;
3420 
    yhdl446  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6DataSel_int  <= m2s6DataSel;  end generate;
3421 
    yhdl447  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6DataSel_int  <= '0';          end generate;
3422 
    yhdl448  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7DataSel_int  <= m2s7DataSel;  end generate;
3423 
    yhdl449  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7DataSel_int  <= '0';          end generate;
3424 
    yhdl450  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8DataSel_int  <= m2s8DataSel;  end generate;
3425 
    yhdl451  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8DataSel_int  <= '0';          end generate;
3426 
    yhdl452  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9DataSel_int  <= m2s9DataSel;  end generate;
3427 
    yhdl453  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9DataSel_int  <= '0';          end generate;
3428 
    yhdl454  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10DataSel_int <= m2s10DataSel; end generate;
3429 
    yhdl455  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10DataSel_int <= '0';          end generate;
3430 
    yhdl456  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11DataSel_int <= m2s11DataSel; end generate;
3431 
    yhdl457  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11DataSel_int <= '0';          end generate;
3432 
    yhdl458  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12DataSel_int <= m2s12DataSel; end generate;
3433 
    yhdl459  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12DataSel_int <= '0';          end generate;
3434 
    yhdl460  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13DataSel_int <= m2s13DataSel; end generate;
3435 
    yhdl461  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13DataSel_int <= '0';          end generate;
3436 
    yhdl462  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14DataSel_int <= m2s14DataSel; end generate;
3437 
    yhdl463  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14DataSel_int <= '0';          end generate;
3438 
    yhdl464  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15DataSel_int <= m2s15DataSel; end generate;
3439 
    yhdl465  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15DataSel_int <= '0';          end generate;
3440 
    yhdl466  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16DataSel_int <= m2s16DataSel; end generate;
3441 
    yhdl467  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16DataSel_int <= '0';          end generate;
3442 
    yhdl470  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0DataSel_int  <= m3s0DataSel;  end generate;
3443 
    yhdl471  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0DataSel_int  <= '0';          end generate;
3444 
    yhdl472  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1DataSel_int  <= m3s1DataSel;  end generate;
3445 
    yhdl473  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1DataSel_int  <= '0';          end generate;
3446 
    yhdl474  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2DataSel_int  <= m3s2DataSel;  end generate;
3447 
    yhdl475  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2DataSel_int  <= '0';          end generate;
3448 
    yhdl476  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3DataSel_int  <= m3s3DataSel;  end generate;
3449 
    yhdl477  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3DataSel_int  <= '0';          end generate;
3450 
    yhdl478  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4DataSel_int  <= m3s4DataSel;  end generate;
3451 
    yhdl479  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4DataSel_int  <= '0';          end generate;
3452 
    yhdl480  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5DataSel_int  <= m3s5DataSel;  end generate;
3453 
    yhdl481  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5DataSel_int  <= '0';          end generate;
3454 
    yhdl482  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6DataSel_int  <= m3s6DataSel;  end generate;
3455 
    yhdl483  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6DataSel_int  <= '0';          end generate;
3456 
    yhdl484  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7DataSel_int  <= m3s7DataSel;  end generate;
3457 
    yhdl485  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7DataSel_int  <= '0';          end generate;
3458 
    yhdl486  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8DataSel_int  <= m3s8DataSel;  end generate;
3459 
    yhdl487  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8DataSel_int  <= '0';          end generate;
3460 
    yhdl488  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9DataSel_int  <= m3s9DataSel;  end generate;
3461 
    yhdl489  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9DataSel_int  <= '0';          end generate;
3462 
    yhdl490  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10DataSel_int <= m3s10DataSel; end generate;
3463 
    yhdl491  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10DataSel_int <= '0';          end generate;
3464 
    yhdl492  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11DataSel_int <= m3s11DataSel; end generate;
3465 
    yhdl493  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11DataSel_int <= '0';          end generate;
3466 
    yhdl494  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12DataSel_int <= m3s12DataSel; end generate;
3467 
    yhdl495  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12DataSel_int <= '0';          end generate;
3468 
    yhdl496  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13DataSel_int <= m3s13DataSel; end generate;
3469 
    yhdl497  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13DataSel_int <= '0';          end generate;
3470 
    yhdl498  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14DataSel_int <= m3s14DataSel; end generate;
3471 
    yhdl499  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14DataSel_int <= '0';          end generate;
3472 
    yhdl500  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15DataSel_int <= m3s15DataSel; end generate;
3473 
    yhdl501  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15DataSel_int <= '0';          end generate;
3474 
    yhdl502  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16DataSel_int <= m3s16DataSel; end generate;
3475 
    yhdl503  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16DataSel_int <= '0';          end generate;
3476 
    yhdl506  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0GatedHADDR  <= M2GATEDHADDR;                       end generate;
3477 
    yhdl507  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3478 
    yhdl508  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1GatedHADDR  <= M2GATEDHADDR;                       end generate;
3479 
    yhdl509  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3480 
    yhdl510  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2GatedHADDR  <= M2GATEDHADDR;                       end generate;
3481 
    yhdl511  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3482 
    yhdl512  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3GatedHADDR  <= M2GATEDHADDR;                       end generate;
3483 
    yhdl513  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3484 
    yhdl514  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4GatedHADDR  <= M2GATEDHADDR;                       end generate;
3485 
    yhdl515  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3486 
    yhdl516  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5GatedHADDR  <= M2GATEDHADDR;                       end generate;
3487 
    yhdl517  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3488 
    yhdl518  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6GatedHADDR  <= M2GATEDHADDR;                       end generate;
3489 
    yhdl519  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3490 
    yhdl520  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7GatedHADDR  <= M2GATEDHADDR;                       end generate;
3491 
    yhdl521  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3492 
    yhdl522  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8GatedHADDR  <= M2GATEDHADDR;                       end generate;
3493 
    yhdl523  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3494 
    yhdl524  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9GatedHADDR  <= M2GATEDHADDR;                       end generate;
3495 
    yhdl525  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3496 
    yhdl526  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10GatedHADDR <= M2GATEDHADDR;                       end generate;
3497 
    yhdl527  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10GatedHADDR <= "00000000000000000000000000000000"; end generate;
3498 
    yhdl528  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11GatedHADDR <= M2GATEDHADDR;                       end generate;
3499 
    yhdl529  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11GatedHADDR <= "00000000000000000000000000000000"; end generate;
3500 
    yhdl530  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12GatedHADDR <= M2GATEDHADDR;                       end generate;
3501 
    yhdl531  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12GatedHADDR <= "00000000000000000000000000000000"; end generate;
3502 
    yhdl532  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13GatedHADDR <= M2GATEDHADDR;                       end generate;
3503 
    yhdl533  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13GatedHADDR <= "00000000000000000000000000000000"; end generate;
3504 
    yhdl534  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14GatedHADDR <= M2GATEDHADDR;                       end generate;
3505 
    yhdl535  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14GatedHADDR <= "00000000000000000000000000000000"; end generate;
3506 
    yhdl536  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15GatedHADDR <= M2GATEDHADDR;                       end generate;
3507 
    yhdl537  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15GatedHADDR <= "00000000000000000000000000000000"; end generate;
3508 
    yhdl538  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16GatedHADDR <= M2GATEDHADDR;                       end generate;
3509 
    yhdl539  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16GatedHADDR <= "00000000000000000000000000000000"; end generate;
3510 
    yhdl542  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0GatedHADDR  <= M3GATEDHADDR;                       end generate;
3511 
    yhdl543  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3512 
    yhdl544  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1GatedHADDR  <= M3GATEDHADDR;                       end generate;
3513 
    yhdl545  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3514 
    yhdl546  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2GatedHADDR  <= M3GATEDHADDR;                       end generate;
3515 
    yhdl547  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3516 
    yhdl548  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3GatedHADDR  <= M3GATEDHADDR;                       end generate;
3517 
    yhdl549  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3518 
    yhdl550  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4GatedHADDR  <= M3GATEDHADDR;                       end generate;
3519 
    yhdl551  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3520 
    yhdl552  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5GatedHADDR  <= M3GATEDHADDR;                       end generate;
3521 
    yhdl553  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3522 
    yhdl554  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6GatedHADDR  <= M3GATEDHADDR;                       end generate;
3523 
    yhdl555  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3524 
    yhdl556  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7GatedHADDR  <= M3GATEDHADDR;                       end generate;
3525 
    yhdl557  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3526 
    yhdl558  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8GatedHADDR  <= M3GATEDHADDR;                       end generate;
3527 
    yhdl559  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3528 
    yhdl560  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9GatedHADDR  <= M3GATEDHADDR;                       end generate;
3529 
    yhdl561  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9GatedHADDR  <= "00000000000000000000000000000000"; end generate;
3530 
    yhdl562  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10GatedHADDR <= M3GATEDHADDR;                       end generate;
3531 
    yhdl563  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10GatedHADDR <= "00000000000000000000000000000000"; end generate;
3532 
    yhdl564  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11GatedHADDR <= M3GATEDHADDR;                       end generate;
3533 
    yhdl565  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11GatedHADDR <= "00000000000000000000000000000000"; end generate;
3534 
    yhdl566  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12GatedHADDR <= M3GATEDHADDR;                       end generate;
3535 
    yhdl567  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12GatedHADDR <= "00000000000000000000000000000000"; end generate;
3536 
    yhdl568  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13GatedHADDR <= M3GATEDHADDR;                       end generate;
3537 
    yhdl569  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13GatedHADDR <= "00000000000000000000000000000000"; end generate;
3538 
    yhdl570  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14GatedHADDR <= M3GATEDHADDR;                       end generate;
3539 
    yhdl571  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14GatedHADDR <= "00000000000000000000000000000000"; end generate;
3540 
    yhdl572  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15GatedHADDR <= M3GATEDHADDR;                       end generate;
3541 
    yhdl573  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15GatedHADDR <= "00000000000000000000000000000000"; end generate;
3542 
    yhdl574  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16GatedHADDR <= M3GATEDHADDR;                       end generate;
3543 
    yhdl575  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16GatedHADDR <= "00000000000000000000000000000000"; end generate;
3544 
    yhdl578  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3545 
    yhdl579  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0GatedHMASTLOCK  <= '0';              end generate;
3546 
    yhdl580  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3547 
    yhdl581  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1GatedHMASTLOCK  <= '0';              end generate;
3548 
    yhdl582  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3549 
    yhdl583  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2GatedHMASTLOCK  <= '0';              end generate;
3550 
    yhdl584  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3551 
    yhdl585  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3GatedHMASTLOCK  <= '0';              end generate;
3552 
    yhdl586  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3553 
    yhdl587  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4GatedHMASTLOCK  <= '0';              end generate;
3554 
    yhdl588  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3555 
    yhdl589  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5GatedHMASTLOCK  <= '0';              end generate;
3556 
    yhdl590  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3557 
    yhdl591  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6GatedHMASTLOCK  <= '0';              end generate;
3558 
    yhdl592  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3559 
    yhdl593  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7GatedHMASTLOCK  <= '0';              end generate;
3560 
    yhdl594  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3561 
    yhdl595  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8GatedHMASTLOCK  <= '0';              end generate;
3562 
    yhdl596  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9GatedHMASTLOCK  <= M2GATEDHMASTLOCK; end generate;
3563 
    yhdl597  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9GatedHMASTLOCK  <= '0';              end generate;
3564 
    yhdl598  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3565 
    yhdl599  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10GatedHMASTLOCK <= '0';              end generate;
3566 
    yhdl600  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3567 
    yhdl601  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11GatedHMASTLOCK <= '0';              end generate;
3568 
    yhdl602  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3569 
    yhdl603  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12GatedHMASTLOCK <= '0';              end generate;
3570 
    yhdl604  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3571 
    yhdl605  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13GatedHMASTLOCK <= '0';              end generate;
3572 
    yhdl606  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3573 
    yhdl607  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14GatedHMASTLOCK <= '0';              end generate;
3574 
    yhdl608  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3575 
    yhdl609  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15GatedHMASTLOCK <= '0';              end generate;
3576 
    yhdl610  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16GatedHMASTLOCK <= M2GATEDHMASTLOCK; end generate;
3577 
    yhdl611  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16GatedHMASTLOCK <= '0';              end generate;
3578 
    yhdl614  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3579 
    yhdl615  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0GatedHMASTLOCK  <= '0';              end generate;
3580 
    yhdl616  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3581 
    yhdl617  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1GatedHMASTLOCK  <= '0';              end generate;
3582 
    yhdl618  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3583 
    yhdl619  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2GatedHMASTLOCK  <= '0';              end generate;
3584 
    yhdl620  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3585 
    yhdl621  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3GatedHMASTLOCK  <= '0';              end generate;
3586 
    yhdl622  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3587 
    yhdl623  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4GatedHMASTLOCK  <= '0';              end generate;
3588 
    yhdl624  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3589 
    yhdl625  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5GatedHMASTLOCK  <= '0';              end generate;
3590 
    yhdl626  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3591 
    yhdl627  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6GatedHMASTLOCK  <= '0';              end generate;
3592 
    yhdl628  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3593 
    yhdl629  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7GatedHMASTLOCK  <= '0';              end generate;
3594 
    yhdl630  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3595 
    yhdl631  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8GatedHMASTLOCK  <= '0';              end generate;
3596 
    yhdl632  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9GatedHMASTLOCK  <= M3GATEDHMASTLOCK; end generate;
3597 
    yhdl633  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9GatedHMASTLOCK  <= '0';              end generate;
3598 
    yhdl634  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3599 
    yhdl635  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10GatedHMASTLOCK <= '0';              end generate;
3600 
    yhdl636  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3601 
    yhdl637  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11GatedHMASTLOCK <= '0';              end generate;
3602 
    yhdl638  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3603 
    yhdl639  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12GatedHMASTLOCK <= '0';              end generate;
3604 
    yhdl640  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3605 
    yhdl641  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13GatedHMASTLOCK <= '0';              end generate;
3606 
    yhdl642  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3607 
    yhdl643  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14GatedHMASTLOCK <= '0';              end generate;
3608 
    yhdl644  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3609 
    yhdl645  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15GatedHMASTLOCK <= '0';              end generate;
3610 
    yhdl646  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16GatedHMASTLOCK <= M3GATEDHMASTLOCK; end generate;
3611 
    yhdl647  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16GatedHMASTLOCK <= '0';              end generate;
3612 
    yhdl650  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0GatedHSIZE  <= M2GATEDHSIZE; end generate;
3613 
    yhdl651  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0GatedHSIZE  <= "000";        end generate;
3614 
    yhdl652  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1GatedHSIZE  <= M2GATEDHSIZE; end generate;
3615 
    yhdl653  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1GatedHSIZE  <= "000";        end generate;
3616 
    yhdl654  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2GatedHSIZE  <= M2GATEDHSIZE; end generate;
3617 
    yhdl655  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2GatedHSIZE  <= "000";        end generate;
3618 
    yhdl656  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3GatedHSIZE  <= M2GATEDHSIZE; end generate;
3619 
    yhdl657  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3GatedHSIZE  <= "000";        end generate;
3620 
    yhdl658  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4GatedHSIZE  <= M2GATEDHSIZE; end generate;
3621 
    yhdl659  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4GatedHSIZE  <= "000";        end generate;
3622 
    yhdl660  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5GatedHSIZE  <= M2GATEDHSIZE; end generate;
3623 
    yhdl661  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5GatedHSIZE  <= "000";        end generate;
3624 
    yhdl662  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6GatedHSIZE  <= M2GATEDHSIZE; end generate;
3625 
    yhdl663  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6GatedHSIZE  <= "000";        end generate;
3626 
    yhdl664  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7GatedHSIZE  <= M2GATEDHSIZE; end generate;
3627 
    yhdl665  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7GatedHSIZE  <= "000";        end generate;
3628 
    yhdl666  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8GatedHSIZE  <= M2GATEDHSIZE; end generate;
3629 
    yhdl667  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8GatedHSIZE  <= "000";        end generate;
3630 
    yhdl668  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9GatedHSIZE  <= M2GATEDHSIZE; end generate;
3631 
    yhdl669  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9GatedHSIZE  <= "000";        end generate;
3632 
    yhdl670  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10GatedHSIZE <= M2GATEDHSIZE; end generate;
3633 
    yhdl671  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10GatedHSIZE <= "000";        end generate;
3634 
    yhdl672  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11GatedHSIZE <= M2GATEDHSIZE; end generate;
3635 
    yhdl673  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11GatedHSIZE <= "000";        end generate;
3636 
    yhdl674  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12GatedHSIZE <= M2GATEDHSIZE; end generate;
3637 
    yhdl675  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12GatedHSIZE <= "000";        end generate;
3638 
    yhdl676  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13GatedHSIZE <= M2GATEDHSIZE; end generate;
3639 
    yhdl677  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13GatedHSIZE <= "000";        end generate;
3640 
    yhdl678  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14GatedHSIZE <= M2GATEDHSIZE; end generate;
3641 
    yhdl679  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14GatedHSIZE <= "000";        end generate;
3642 
    yhdl680  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15GatedHSIZE <= M2GATEDHSIZE; end generate;
3643 
    yhdl681  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15GatedHSIZE <= "000";        end generate;
3644 
    yhdl682  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16GatedHSIZE <= M2GATEDHSIZE; end generate;
3645 
    yhdl683  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16GatedHSIZE <= "000";        end generate;
3646 
    yhdl686  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0GatedHSIZE  <= M3GATEDHSIZE; end generate;
3647 
    yhdl687  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0GatedHSIZE  <= "000";        end generate;
3648 
    yhdl688  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1GatedHSIZE  <= M3GATEDHSIZE; end generate;
3649 
    yhdl689  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1GatedHSIZE  <= "000";        end generate;
3650 
    yhdl690  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2GatedHSIZE  <= M3GATEDHSIZE; end generate;
3651 
    yhdl691  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2GatedHSIZE  <= "000";        end generate;
3652 
    yhdl692  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3GatedHSIZE  <= M3GATEDHSIZE; end generate;
3653 
    yhdl693  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3GatedHSIZE  <= "000";        end generate;
3654 
    yhdl694  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4GatedHSIZE  <= M3GATEDHSIZE; end generate;
3655 
    yhdl695  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4GatedHSIZE  <= "000";        end generate;
3656 
    yhdl696  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5GatedHSIZE  <= M3GATEDHSIZE; end generate;
3657 
    yhdl697  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5GatedHSIZE  <= "000";        end generate;
3658 
    yhdl698  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6GatedHSIZE  <= M3GATEDHSIZE; end generate;
3659 
    yhdl699  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6GatedHSIZE  <= "000";        end generate;
3660 
    yhdl700  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7GatedHSIZE  <= M3GATEDHSIZE; end generate;
3661 
    yhdl701  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7GatedHSIZE  <= "000";        end generate;
3662 
    yhdl702  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8GatedHSIZE  <= M3GATEDHSIZE; end generate;
3663 
    yhdl703  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8GatedHSIZE  <= "000";        end generate;
3664 
    yhdl704  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9GatedHSIZE  <= M3GATEDHSIZE; end generate;
3665 
    yhdl705  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9GatedHSIZE  <= "000";        end generate;
3666 
    yhdl706  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10GatedHSIZE <= M3GATEDHSIZE; end generate;
3667 
    yhdl707  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10GatedHSIZE <= "000";        end generate;
3668 
    yhdl708  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11GatedHSIZE <= M3GATEDHSIZE; end generate;
3669 
    yhdl709  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11GatedHSIZE <= "000";        end generate;
3670 
    yhdl710  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12GatedHSIZE <= M3GATEDHSIZE; end generate;
3671 
    yhdl711  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12GatedHSIZE <= "000";        end generate;
3672 
    yhdl712  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13GatedHSIZE <= M3GATEDHSIZE; end generate;
3673 
    yhdl713  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13GatedHSIZE <= "000";        end generate;
3674 
    yhdl714  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14GatedHSIZE <= M3GATEDHSIZE; end generate;
3675 
    yhdl715  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14GatedHSIZE <= "000";        end generate;
3676 
    yhdl716  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15GatedHSIZE <= M3GATEDHSIZE; end generate;
3677 
    yhdl717  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15GatedHSIZE <= "000";        end generate;
3678 
    yhdl718  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16GatedHSIZE <= M3GATEDHSIZE; end generate;
3679 
    yhdl719  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16GatedHSIZE <= "000";        end generate;
3680 
    yhdl722  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0GatedHTRANS  <= M2GATEDHTRANS; end generate;
3681 
    yhdl723  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0GatedHTRANS  <= '0';           end generate;
3682 
    yhdl724  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1GatedHTRANS  <= M2GATEDHTRANS; end generate;
3683 
    yhdl725  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1GatedHTRANS  <= '0';           end generate;
3684 
    yhdl726  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2GatedHTRANS  <= M2GATEDHTRANS; end generate;
3685 
    yhdl727  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2GatedHTRANS  <= '0';           end generate;
3686 
    yhdl728  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3GatedHTRANS  <= M2GATEDHTRANS; end generate;
3687 
    yhdl729  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3GatedHTRANS  <= '0';           end generate;
3688 
    yhdl730  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4GatedHTRANS  <= M2GATEDHTRANS; end generate;
3689 
    yhdl731  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4GatedHTRANS  <= '0';           end generate;
3690 
    yhdl732  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5GatedHTRANS  <= M2GATEDHTRANS; end generate;
3691 
    yhdl733  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5GatedHTRANS  <= '0';           end generate;
3692 
    yhdl734  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6GatedHTRANS  <= M2GATEDHTRANS; end generate;
3693 
    yhdl735  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6GatedHTRANS  <= '0';           end generate;
3694 
    yhdl736  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7GatedHTRANS  <= M2GATEDHTRANS; end generate;
3695 
    yhdl737  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7GatedHTRANS  <= '0';           end generate;
3696 
    yhdl738  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8GatedHTRANS  <= M2GATEDHTRANS; end generate;
3697 
    yhdl739  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8GatedHTRANS  <= '0';           end generate;
3698 
    yhdl740  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9GatedHTRANS  <= M2GATEDHTRANS; end generate;
3699 
    yhdl741  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9GatedHTRANS  <= '0';           end generate;
3700 
    yhdl742  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10GatedHTRANS <= M2GATEDHTRANS; end generate;
3701 
    yhdl743  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10GatedHTRANS <= '0';           end generate;
3702 
    yhdl744  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11GatedHTRANS <= M2GATEDHTRANS; end generate;
3703 
    yhdl745  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11GatedHTRANS <= '0';           end generate;
3704 
    yhdl746  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12GatedHTRANS <= M2GATEDHTRANS; end generate;
3705 
    yhdl747  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12GatedHTRANS <= '0';           end generate;
3706 
    yhdl748  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13GatedHTRANS <= M2GATEDHTRANS; end generate;
3707 
    yhdl749  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13GatedHTRANS <= '0';           end generate;
3708 
    yhdl750  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14GatedHTRANS <= M2GATEDHTRANS; end generate;
3709 
    yhdl751  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14GatedHTRANS <= '0';           end generate;
3710 
    yhdl752  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15GatedHTRANS <= M2GATEDHTRANS; end generate;
3711 
    yhdl753  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15GatedHTRANS <= '0';           end generate;
3712 
    yhdl754  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16GatedHTRANS <= M2GATEDHTRANS; end generate;
3713 
    yhdl755  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16GatedHTRANS <= '0';           end generate;
3714 
    yhdl758  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0GatedHTRANS  <= M3GATEDHTRANS; end generate;
3715 
    yhdl759  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0GatedHTRANS  <= '0';           end generate;
3716 
    yhdl760  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1GatedHTRANS  <= M3GATEDHTRANS; end generate;
3717 
    yhdl761  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1GatedHTRANS  <= '0';           end generate;
3718 
    yhdl762  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2GatedHTRANS  <= M3GATEDHTRANS; end generate;
3719 
    yhdl763  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2GatedHTRANS  <= '0';           end generate;
3720 
    yhdl764  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3GatedHTRANS  <= M3GATEDHTRANS; end generate;
3721 
    yhdl765  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3GatedHTRANS  <= '0';           end generate;
3722 
    yhdl766  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4GatedHTRANS  <= M3GATEDHTRANS; end generate;
3723 
    yhdl767  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4GatedHTRANS  <= '0';           end generate;
3724 
    yhdl768  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5GatedHTRANS  <= M3GATEDHTRANS; end generate;
3725 
    yhdl769  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5GatedHTRANS  <= '0';           end generate;
3726 
    yhdl770  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6GatedHTRANS  <= M3GATEDHTRANS; end generate;
3727 
    yhdl771  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6GatedHTRANS  <= '0';           end generate;
3728 
    yhdl772  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7GatedHTRANS  <= M3GATEDHTRANS; end generate;
3729 
    yhdl773  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7GatedHTRANS  <= '0';           end generate;
3730 
    yhdl774  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8GatedHTRANS  <= M3GATEDHTRANS; end generate;
3731 
    yhdl775  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8GatedHTRANS  <= '0';           end generate;
3732 
    yhdl776  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9GatedHTRANS  <= M3GATEDHTRANS; end generate;
3733 
    yhdl777  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9GatedHTRANS  <= '0';           end generate;
3734 
    yhdl778  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10GatedHTRANS <= M3GATEDHTRANS; end generate;
3735 
    yhdl779  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10GatedHTRANS <= '0';           end generate;
3736 
    yhdl780  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11GatedHTRANS <= M3GATEDHTRANS; end generate;
3737 
    yhdl781  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11GatedHTRANS <= '0';           end generate;
3738 
    yhdl782  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12GatedHTRANS <= M3GATEDHTRANS; end generate;
3739 
    yhdl783  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12GatedHTRANS <= '0';           end generate;
3740 
    yhdl784  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13GatedHTRANS <= M3GATEDHTRANS; end generate;
3741 
    yhdl785  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13GatedHTRANS <= '0';           end generate;
3742 
    yhdl786  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14GatedHTRANS <= M3GATEDHTRANS; end generate;
3743 
    yhdl787  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14GatedHTRANS <= '0';           end generate;
3744 
    yhdl788  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15GatedHTRANS <= M3GATEDHTRANS; end generate;
3745 
    yhdl789  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15GatedHTRANS <= '0';           end generate;
3746 
    yhdl790  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16GatedHTRANS <= M3GATEDHTRANS; end generate;
3747 
    yhdl791  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16GatedHTRANS <= '0';           end generate;
3748 
    yhdl794  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0GatedHWRITE  <= M2GATEDHWRITE; end generate;
3749 
    yhdl795  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0GatedHWRITE  <= '0';           end generate;
3750 
    yhdl796  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1GatedHWRITE  <= M2GATEDHWRITE; end generate;
3751 
    yhdl797  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1GatedHWRITE  <= '0';           end generate;
3752 
    yhdl798  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2GatedHWRITE  <= M2GATEDHWRITE; end generate;
3753 
    yhdl799  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2GatedHWRITE  <= '0';           end generate;
3754 
    yhdl800  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3GatedHWRITE  <= M2GATEDHWRITE; end generate;
3755 
    yhdl801  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3GatedHWRITE  <= '0';           end generate;
3756 
    yhdl802  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4GatedHWRITE  <= M2GATEDHWRITE; end generate;
3757 
    yhdl803  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4GatedHWRITE  <= '0';           end generate;
3758 
    yhdl804  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5GatedHWRITE  <= M2GATEDHWRITE; end generate;
3759 
    yhdl805  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5GatedHWRITE  <= '0';           end generate;
3760 
    yhdl806  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6GatedHWRITE  <= M2GATEDHWRITE; end generate;
3761 
    yhdl807  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6GatedHWRITE  <= '0';           end generate;
3762 
    yhdl808  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7GatedHWRITE  <= M2GATEDHWRITE; end generate;
3763 
    yhdl809  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7GatedHWRITE  <= '0';           end generate;
3764 
    yhdl810  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8GatedHWRITE  <= M2GATEDHWRITE; end generate;
3765 
    yhdl811  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8GatedHWRITE  <= '0';           end generate;
3766 
    yhdl812  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9GatedHWRITE  <= M2GATEDHWRITE; end generate;
3767 
    yhdl813  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9GatedHWRITE  <= '0';           end generate;
3768 
    yhdl814  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10GatedHWRITE <= M2GATEDHWRITE; end generate;
3769 
    yhdl815  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10GatedHWRITE <= '0';           end generate;
3770 
    yhdl816  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11GatedHWRITE <= M2GATEDHWRITE; end generate;
3771 
    yhdl817  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11GatedHWRITE <= '0';           end generate;
3772 
    yhdl818  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12GatedHWRITE <= M2GATEDHWRITE; end generate;
3773 
    yhdl819  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12GatedHWRITE <= '0';           end generate;
3774 
    yhdl820  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13GatedHWRITE <= M2GATEDHWRITE; end generate;
3775 
    yhdl821  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13GatedHWRITE <= '0';           end generate;
3776 
    yhdl822  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14GatedHWRITE <= M2GATEDHWRITE; end generate;
3777 
    yhdl823  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14GatedHWRITE <= '0';           end generate;
3778 
    yhdl824  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15GatedHWRITE <= M2GATEDHWRITE; end generate;
3779 
    yhdl825  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15GatedHWRITE <= '0';           end generate;
3780 
    yhdl826  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16GatedHWRITE <= M2GATEDHWRITE; end generate;
3781 
    yhdl827  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16GatedHWRITE <= '0';           end generate;
3782 
    yhdl830  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0GatedHWRITE  <= M3GATEDHWRITE; end generate;
3783 
    yhdl831  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0GatedHWRITE  <= '0';           end generate;
3784 
    yhdl832  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1GatedHWRITE  <= M3GATEDHWRITE; end generate;
3785 
    yhdl833  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1GatedHWRITE  <= '0';           end generate;
3786 
    yhdl834  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2GatedHWRITE  <= M3GATEDHWRITE; end generate;
3787 
    yhdl835  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2GatedHWRITE  <= '0';           end generate;
3788 
    yhdl836  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3GatedHWRITE  <= M3GATEDHWRITE; end generate;
3789 
    yhdl837  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3GatedHWRITE  <= '0';           end generate;
3790 
    yhdl838  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4GatedHWRITE  <= M3GATEDHWRITE; end generate;
3791 
    yhdl839  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4GatedHWRITE  <= '0';           end generate;
3792 
    yhdl840  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5GatedHWRITE  <= M3GATEDHWRITE; end generate;
3793 
    yhdl841  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5GatedHWRITE  <= '0';           end generate;
3794 
    yhdl842  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6GatedHWRITE  <= M3GATEDHWRITE; end generate;
3795 
    yhdl843  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6GatedHWRITE  <= '0';           end generate;
3796 
    yhdl844  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7GatedHWRITE  <= M3GATEDHWRITE; end generate;
3797 
    yhdl845  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7GatedHWRITE  <= '0';           end generate;
3798 
    yhdl846  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8GatedHWRITE  <= M3GATEDHWRITE; end generate;
3799 
    yhdl847  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8GatedHWRITE  <= '0';           end generate;
3800 
    yhdl848  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9GatedHWRITE  <= M3GATEDHWRITE; end generate;
3801 
    yhdl849  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9GatedHWRITE  <= '0';           end generate;
3802 
    yhdl850  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10GatedHWRITE <= M3GATEDHWRITE; end generate;
3803 
    yhdl851  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10GatedHWRITE <= '0';           end generate;
3804 
    yhdl852  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11GatedHWRITE <= M3GATEDHWRITE; end generate;
3805 
    yhdl853  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11GatedHWRITE <= '0';           end generate;
3806 
    yhdl854  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12GatedHWRITE <= M3GATEDHWRITE; end generate;
3807 
    yhdl855  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12GatedHWRITE <= '0';           end generate;
3808 
    yhdl856  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13GatedHWRITE <= M3GATEDHWRITE; end generate;
3809 
    yhdl857  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13GatedHWRITE <= '0';           end generate;
3810 
    yhdl858  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14GatedHWRITE <= M3GATEDHWRITE; end generate;
3811 
    yhdl859  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14GatedHWRITE <= '0';           end generate;
3812 
    yhdl860  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15GatedHWRITE <= M3GATEDHWRITE; end generate;
3813 
    yhdl861  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15GatedHWRITE <= '0';           end generate;
3814 
    yhdl862  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16GatedHWRITE <= M3GATEDHWRITE; end generate;
3815 
    yhdl863  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16GatedHWRITE <= '0';           end generate;
3816 
    yhdl866  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate m2s0PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3817 
    yhdl867  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate m2s0PrevDataSlaveReady  <= '1';                  end generate;
3818 
    yhdl868  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate m2s1PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3819 
    yhdl869  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate m2s1PrevDataSlaveReady  <= '1';                  end generate;
3820 
    yhdl870  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate m2s2PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3821 
    yhdl871  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate m2s2PrevDataSlaveReady  <= '1';                  end generate;
3822 
    yhdl872  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate m2s3PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3823 
    yhdl873  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate m2s3PrevDataSlaveReady  <= '1';                  end generate;
3824 
    yhdl874  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate m2s4PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3825 
    yhdl875  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate m2s4PrevDataSlaveReady  <= '1';                  end generate;
3826 
    yhdl876  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate m2s5PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3827 
    yhdl877  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate m2s5PrevDataSlaveReady  <= '1';                  end generate;
3828 
    yhdl878  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate m2s6PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3829 
    yhdl879  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate m2s6PrevDataSlaveReady  <= '1';                  end generate;
3830 
    yhdl880  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate m2s7PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3831 
    yhdl881  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate m2s7PrevDataSlaveReady  <= '1';                  end generate;
3832 
    yhdl882  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate m2s8PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3833 
    yhdl883  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate m2s8PrevDataSlaveReady  <= '1';                  end generate;
3834 
    yhdl884  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate m2s9PrevDataSlaveReady  <= m2PrevDataSlaveReady; end generate;
3835 
    yhdl885  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate m2s9PrevDataSlaveReady  <= '1';                  end generate;
3836 
    yhdl886  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate m2s10PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3837 
    yhdl887  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate m2s10PrevDataSlaveReady <= '1';                  end generate;
3838 
    yhdl888  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate m2s11PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3839 
    yhdl889  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate m2s11PrevDataSlaveReady <= '1';                  end generate;
3840 
    yhdl890  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate m2s12PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3841 
    yhdl891  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate m2s12PrevDataSlaveReady <= '1';                  end generate;
3842 
    yhdl892  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate m2s13PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3843 
    yhdl893  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate m2s13PrevDataSlaveReady <= '1';                  end generate;
3844 
    yhdl894  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate m2s14PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3845 
    yhdl895  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate m2s14PrevDataSlaveReady <= '1';                  end generate;
3846 
    yhdl896  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate m2s15PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3847 
    yhdl897  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate m2s15PrevDataSlaveReady <= '1';                  end generate;
3848 
    yhdl898  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate m2s16PrevDataSlaveReady <= m2PrevDataSlaveReady; end generate;
3849 
    yhdl899  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate m2s16PrevDataSlaveReady <= '1';                  end generate;
3850 
    yhdl902  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate m3s0PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3851 
    yhdl903  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate m3s0PrevDataSlaveReady  <= '1';                  end generate;
3852 
    yhdl904  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate m3s1PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3853 
    yhdl905  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate m3s1PrevDataSlaveReady  <= '1';                  end generate;
3854 
    yhdl906  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate m3s2PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3855 
    yhdl907  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate m3s2PrevDataSlaveReady  <= '1';                  end generate;
3856 
    yhdl908  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate m3s3PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3857 
    yhdl909  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate m3s3PrevDataSlaveReady  <= '1';                  end generate;
3858 
    yhdl910  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate m3s4PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3859 
    yhdl911  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate m3s4PrevDataSlaveReady  <= '1';                  end generate;
3860 
    yhdl912  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate m3s5PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3861 
    yhdl913  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate m3s5PrevDataSlaveReady  <= '1';                  end generate;
3862 
    yhdl914  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate m3s6PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3863 
    yhdl915  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate m3s6PrevDataSlaveReady  <= '1';                  end generate;
3864 
    yhdl916  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate m3s7PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3865 
    yhdl917  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate m3s7PrevDataSlaveReady  <= '1';                  end generate;
3866 
    yhdl918  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate m3s8PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3867 
    yhdl919  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate m3s8PrevDataSlaveReady  <= '1';                  end generate;
3868 
    yhdl920  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate m3s9PrevDataSlaveReady  <= m3PrevDataSlaveReady; end generate;
3869 
    yhdl921  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate m3s9PrevDataSlaveReady  <= '1';                  end generate;
3870 
    yhdl922  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate m3s10PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3871 
    yhdl923  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate m3s10PrevDataSlaveReady <= '1';                  end generate;
3872 
    yhdl924  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate m3s11PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3873 
    yhdl925  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate m3s11PrevDataSlaveReady <= '1';                  end generate;
3874 
    yhdl926  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate m3s12PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3875 
    yhdl927  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate m3s12PrevDataSlaveReady <= '1';                  end generate;
3876 
    yhdl928  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate m3s13PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3877 
    yhdl929  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate m3s13PrevDataSlaveReady <= '1';                  end generate;
3878 
    yhdl930  : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate m3s14PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3879 
    yhdl931  : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate m3s14PrevDataSlaveReady <= '1';                  end generate;
3880 
    yhdl932  : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate m3s15PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3881 
    yhdl933  : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate m3s15PrevDataSlaveReady <= '1';                  end generate;
3882 
    yhdl934  : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate m3s16PrevDataSlaveReady <= m3PrevDataSlaveReady; end generate;
3883 
    yhdl935  : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate m3s16PrevDataSlaveReady <= '1';                  end generate;
3884 
    yhdl938  : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate M2_HRDATA_S0  <= HRDATA_S0;                           end generate;
3885 
    yhdl939  : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate M2_HRDATA_S0  <= "00000000000000000000000000000000";  end generate;
3886 
    yhdl940  : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate M2_HRDATA_S1  <= HRDATA_S1;                           end generate;
3887 
    yhdl941  : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate M2_HRDATA_S1  <= "00000000000000000000000000000000";  end generate;
3888 
    yhdl942  : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate M2_HRDATA_S2  <= HRDATA_S2;                           end generate;
3889 
    yhdl943  : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate M2_HRDATA_S2  <= "00000000000000000000000000000000";  end generate;
3890 
    yhdl944  : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate M2_HRDATA_S3  <= HRDATA_S3;                           end generate;
3891 
    yhdl945  : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate M2_HRDATA_S3  <= "00000000000000000000000000000000";  end generate;
3892 
    yhdl946  : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate M2_HRDATA_S4  <= HRDATA_S4;                           end generate;
3893 
    yhdl947  : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate M2_HRDATA_S4  <= "00000000000000000000000000000000";  end generate;
3894 
    yhdl948  : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate M2_HRDATA_S5  <= HRDATA_S5;                           end generate;
3895 
    yhdl949  : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate M2_HRDATA_S5  <= "00000000000000000000000000000000";  end generate;
3896 
    yhdl950  : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate M2_HRDATA_S6  <= HRDATA_S6;                           end generate;
3897 
    yhdl951  : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate M2_HRDATA_S6  <= "00000000000000000000000000000000";  end generate;
3898 
    yhdl952  : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate M2_HRDATA_S7  <= HRDATA_S7;                           end generate;
3899 
    yhdl953  : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate M2_HRDATA_S7  <= "00000000000000000000000000000000";  end generate;
3900 
    yhdl954  : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate M2_HRDATA_S8  <= HRDATA_S8;                           end generate;
3901 
    yhdl955  : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate M2_HRDATA_S8  <= "00000000000000000000000000000000";  end generate;
3902 
    yhdl956  : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate M2_HRDATA_S9  <= HRDATA_S9;                           end generate;
3903 
    yhdl957  : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate M2_HRDATA_S9  <= "00000000000000000000000000000000";  end generate;
3904 
    yhdl958  : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate M2_HRDATA_S10 <= HRDATA_S10;                          end generate;
3905 
    yhdl959  : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate M2_HRDATA_S10 <= "00000000000000000000000000000000";  end generate;
3906 
    yhdl960  : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate M2_HRDATA_S11 <= HRDATA_S11;                          end generate;
3907 
    yhdl961  : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate M2_HRDATA_S11 <= "00000000000000000000000000000000";  end generate;
3908 
    yhdl962  : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate M2_HRDATA_S12 <= HRDATA_S12;                          end generate;
3909 
    yhdl963  : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate M2_HRDATA_S12 <= "00000000000000000000000000000000";  end generate;
3910 
    yhdl964  : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate M2_HRDATA_S13 <= HRDATA_S13;                          end generate;
3911 
    yhdl965  : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate M2_HRDATA_S13 <= "00000000000000000000000000000000";  end generate;
3912 
    yhdl966  : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate M2_HRDATA_S14 <= HRDATA_S14;                          end generate;
3913 
    yhdl967  : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate M2_HRDATA_S14 <= "00000000000000000000000000000000";  end generate;
3914 
    yhdl968  : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate M2_HRDATA_S15 <= HRDATA_S15;                          end generate;
3915 
    yhdl969  : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate M2_HRDATA_S15 <= "00000000000000000000000000000000";  end generate;
3916 
    yhdl970  : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate M2_HRDATA_S16 <= HRDATA_S16;                          end generate;
3917 
    yhdl971  : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate M2_HRDATA_S16 <= "00000000000000000000000000000000";  end generate;
3918 
    yhdl972  : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate M3_HRDATA_S0  <= HRDATA_S0;                           end generate;
3919 
    yhdl973  : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate M3_HRDATA_S0  <= "00000000000000000000000000000000";  end generate;
3920 
    yhdl974  : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate M3_HRDATA_S1  <= HRDATA_S1;                           end generate;
3921 
    yhdl975  : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate M3_HRDATA_S1  <= "00000000000000000000000000000000";  end generate;
3922 
    yhdl976  : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate M3_HRDATA_S2  <= HRDATA_S2;                           end generate;
3923 
    yhdl977  : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate M3_HRDATA_S2  <= "00000000000000000000000000000000";  end generate;
3924 
    yhdl978  : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate M3_HRDATA_S3  <= HRDATA_S3;                           end generate;
3925 
    yhdl979  : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate M3_HRDATA_S3  <= "00000000000000000000000000000000";  end generate;
3926 
    yhdl980  : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate M3_HRDATA_S4  <= HRDATA_S4;                           end generate;
3927 
    yhdl981  : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate M3_HRDATA_S4  <= "00000000000000000000000000000000";  end generate;
3928 
    yhdl982  : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate M3_HRDATA_S5  <= HRDATA_S5;                           end generate;
3929 
    yhdl983  : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate M3_HRDATA_S5  <= "00000000000000000000000000000000";  end generate;
3930 
    yhdl984  : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate M3_HRDATA_S6  <= HRDATA_S6;                           end generate;
3931 
    yhdl985  : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate M3_HRDATA_S6  <= "00000000000000000000000000000000";  end generate;
3932 
    yhdl986  : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate M3_HRDATA_S7  <= HRDATA_S7;                           end generate;
3933 
    yhdl987  : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate M3_HRDATA_S7  <= "00000000000000000000000000000000";  end generate;
3934 
    yhdl988  : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate M3_HRDATA_S8  <= HRDATA_S8;                           end generate;
3935 
    yhdl989  : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate M3_HRDATA_S8  <= "00000000000000000000000000000000";  end generate;
3936 
    yhdl990  : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate M3_HRDATA_S9  <= HRDATA_S9;                           end generate;
3937 
    yhdl991  : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate M3_HRDATA_S9  <= "00000000000000000000000000000000";  end generate;
3938 
    yhdl992  : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate M3_HRDATA_S10 <= HRDATA_S10;                          end generate;
3939 
    yhdl993  : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate M3_HRDATA_S10 <= "00000000000000000000000000000000";  end generate;
3940 
    yhdl994  : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate M3_HRDATA_S11 <= HRDATA_S11;                          end generate;
3941 
    yhdl995  : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate M3_HRDATA_S11 <= "00000000000000000000000000000000";  end generate;
3942 
    yhdl996  : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate M3_HRDATA_S12 <= HRDATA_S12;                          end generate;
3943 
    yhdl997  : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate M3_HRDATA_S12 <= "00000000000000000000000000000000";  end generate;
3944 
    yhdl998  : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate M3_HRDATA_S13 <= HRDATA_S13;                          end generate;
3945 
    yhdl999  : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate M3_HRDATA_S13 <= "00000000000000000000000000000000";  end generate;
3946 
    yhdl1000 : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate M3_HRDATA_S14 <= HRDATA_S14;                          end generate;
3947 
    yhdl1001 : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate M3_HRDATA_S14 <= "00000000000000000000000000000000";  end generate;
3948 
    yhdl1002 : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate M3_HRDATA_S15 <= HRDATA_S15;                          end generate;
3949 
    yhdl1003 : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate M3_HRDATA_S15 <= "00000000000000000000000000000000";  end generate;
3950 
    yhdl1004 : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate M3_HRDATA_S16 <= HRDATA_S16;                          end generate;
3951 
    yhdl1005 : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate M3_HRDATA_S16 <= "00000000000000000000000000000000";  end generate;
3952 
    yhdl1006 : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate HWDATA_M2S0  <= HWDATA_M2;                          end generate;
3953 
    yhdl1007 : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate HWDATA_M2S0  <= "00000000000000000000000000000000"; end generate;
3954 
    yhdl1008 : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate HWDATA_M2S1  <= HWDATA_M2;                          end generate;
3955 
    yhdl1009 : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate HWDATA_M2S1  <= "00000000000000000000000000000000"; end generate;
3956 
    yhdl1010 : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate HWDATA_M2S2  <= HWDATA_M2;                          end generate;
3957 
    yhdl1011 : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate HWDATA_M2S2  <= "00000000000000000000000000000000"; end generate;
3958 
    yhdl1012 : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate HWDATA_M2S3  <= HWDATA_M2;                          end generate;
3959 
    yhdl1013 : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate HWDATA_M2S3  <= "00000000000000000000000000000000"; end generate;
3960 
    yhdl1014 : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate HWDATA_M2S4  <= HWDATA_M2;                          end generate;
3961 
    yhdl1015 : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate HWDATA_M2S4  <= "00000000000000000000000000000000"; end generate;
3962 
    yhdl1016 : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate HWDATA_M2S5  <= HWDATA_M2;                          end generate;
3963 
    yhdl1017 : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate HWDATA_M2S5  <= "00000000000000000000000000000000"; end generate;
3964 
    yhdl1018 : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate HWDATA_M2S6  <= HWDATA_M2;                          end generate;
3965 
    yhdl1019 : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate HWDATA_M2S6  <= "00000000000000000000000000000000"; end generate;
3966 
    yhdl1020 : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate HWDATA_M2S7  <= HWDATA_M2;                          end generate;
3967 
    yhdl1021 : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate HWDATA_M2S7  <= "00000000000000000000000000000000"; end generate;
3968 
    yhdl1022 : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate HWDATA_M2S8  <= HWDATA_M2;                          end generate;
3969 
    yhdl1023 : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate HWDATA_M2S8  <= "00000000000000000000000000000000"; end generate;
3970 
    yhdl1024 : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate HWDATA_M2S9  <= HWDATA_M2;                          end generate;
3971 
    yhdl1025 : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate HWDATA_M2S9  <= "00000000000000000000000000000000"; end generate;
3972 
    yhdl1026 : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate HWDATA_M2S10 <= HWDATA_M2;                          end generate;
3973 
    yhdl1027 : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate HWDATA_M2S10 <= "00000000000000000000000000000000"; end generate;
3974 
    yhdl1028 : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate HWDATA_M2S11 <= HWDATA_M2;                          end generate;
3975 
    yhdl1029 : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate HWDATA_M2S11 <= "00000000000000000000000000000000"; end generate;
3976 
    yhdl1030 : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate HWDATA_M2S12 <= HWDATA_M2;                          end generate;
3977 
    yhdl1031 : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate HWDATA_M2S12 <= "00000000000000000000000000000000"; end generate;
3978 
    yhdl1032 : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate HWDATA_M2S13 <= HWDATA_M2;                          end generate;
3979 
    yhdl1033 : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate HWDATA_M2S13 <= "00000000000000000000000000000000"; end generate;
3980 
    yhdl1034 : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate HWDATA_M2S14 <= HWDATA_M2;                          end generate;
3981 
    yhdl1035 : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate HWDATA_M2S14 <= "00000000000000000000000000000000"; end generate;
3982 
    yhdl1036 : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate HWDATA_M2S15 <= HWDATA_M2;                          end generate;
3983 
    yhdl1037 : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate HWDATA_M2S15 <= "00000000000000000000000000000000"; end generate;
3984 
    yhdl1038 : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate HWDATA_M2S16 <= HWDATA_M2;                          end generate;
3985 
    yhdl1039 : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate HWDATA_M2S16 <= "00000000000000000000000000000000"; end generate;
3986 
    yhdl1042 : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate HWDATA_M3S0  <= HWDATA_M3;                          end generate;
3987 
    yhdl1043 : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate HWDATA_M3S0  <= "00000000000000000000000000000000"; end generate;
3988 
    yhdl1044 : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate HWDATA_M3S1  <= HWDATA_M3;                          end generate;
3989 
    yhdl1045 : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate HWDATA_M3S1  <= "00000000000000000000000000000000"; end generate;
3990 
    yhdl1046 : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate HWDATA_M3S2  <= HWDATA_M3;                          end generate;
3991 
    yhdl1047 : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate HWDATA_M3S2  <= "00000000000000000000000000000000"; end generate;
3992 
    yhdl1048 : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate HWDATA_M3S3  <= HWDATA_M3;                          end generate;
3993 
    yhdl1049 : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate HWDATA_M3S3  <= "00000000000000000000000000000000"; end generate;
3994 
    yhdl1050 : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate HWDATA_M3S4  <= HWDATA_M3;                          end generate;
3995 
    yhdl1051 : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate HWDATA_M3S4  <= "00000000000000000000000000000000"; end generate;
3996 
    yhdl1052 : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate HWDATA_M3S5  <= HWDATA_M3;                          end generate;
3997 
    yhdl1053 : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate HWDATA_M3S5  <= "00000000000000000000000000000000"; end generate;
3998 
    yhdl1054 : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate HWDATA_M3S6  <= HWDATA_M3;                          end generate;
3999 
    yhdl1055 : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate HWDATA_M3S6  <= "00000000000000000000000000000000"; end generate;
4000 
    yhdl1056 : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate HWDATA_M3S7  <= HWDATA_M3;                          end generate;
4001 
    yhdl1057 : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate HWDATA_M3S7  <= "00000000000000000000000000000000"; end generate;
4002 
    yhdl1058 : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate HWDATA_M3S8  <= HWDATA_M3;                          end generate;
4003 
    yhdl1059 : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate HWDATA_M3S8  <= "00000000000000000000000000000000"; end generate;
4004 
    yhdl1060 : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate HWDATA_M3S9  <= HWDATA_M3;                          end generate;
4005 
    yhdl1061 : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate HWDATA_M3S9  <= "00000000000000000000000000000000"; end generate;
4006 
    yhdl1062 : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate HWDATA_M3S10 <= HWDATA_M3;                          end generate;
4007 
    yhdl1063 : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate HWDATA_M3S10 <= "00000000000000000000000000000000"; end generate;
4008 
    yhdl1064 : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate HWDATA_M3S11 <= HWDATA_M3;                          end generate;
4009 
    yhdl1065 : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate HWDATA_M3S11 <= "00000000000000000000000000000000"; end generate;
4010 
    yhdl1066 : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate HWDATA_M3S12 <= HWDATA_M3;                          end generate;
4011 
    yhdl1067 : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate HWDATA_M3S12 <= "00000000000000000000000000000000"; end generate;
4012 
    yhdl1068 : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate HWDATA_M3S13 <= HWDATA_M3;                          end generate;
4013 
    yhdl1069 : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate HWDATA_M3S13 <= "00000000000000000000000000000000"; end generate;
4014 
    yhdl1070 : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate HWDATA_M3S14 <= HWDATA_M3;                          end generate;
4015 
    yhdl1071 : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate HWDATA_M3S14 <= "00000000000000000000000000000000"; end generate;
4016 
    yhdl1072 : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate HWDATA_M3S15 <= HWDATA_M3;                          end generate;
4017 
    yhdl1073 : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate HWDATA_M3S15 <= "00000000000000000000000000000000"; end generate;
4018 
    yhdl1074 : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate HWDATA_M3S16 <= HWDATA_M3;                          end generate;
4019 
    yhdl1075 : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate HWDATA_M3S16 <= "00000000000000000000000000000000"; end generate;
4020 
    yhdl1078 : if (    (M2_AHBSLOTENABLE_slv( 0)) = '1')  generate M2_HREADYOUT_S0  <= HREADYOUT_S0;  end generate;
4021 
    yhdl1079 : if (not((M2_AHBSLOTENABLE_slv( 0)) = '1')) generate M2_HREADYOUT_S0  <= '1';           end generate;
4022 
    yhdl1080 : if (    (M2_AHBSLOTENABLE_slv( 1)) = '1')  generate M2_HREADYOUT_S1  <= HREADYOUT_S1;  end generate;
4023 
    yhdl1081 : if (not((M2_AHBSLOTENABLE_slv( 1)) = '1')) generate M2_HREADYOUT_S1  <= '1';           end generate;
4024 
    yhdl1082 : if (    (M2_AHBSLOTENABLE_slv( 2)) = '1')  generate M2_HREADYOUT_S2  <= HREADYOUT_S2;  end generate;
4025 
    yhdl1083 : if (not((M2_AHBSLOTENABLE_slv( 2)) = '1')) generate M2_HREADYOUT_S2  <= '1';           end generate;
4026 
    yhdl1084 : if (    (M2_AHBSLOTENABLE_slv( 3)) = '1')  generate M2_HREADYOUT_S3  <= HREADYOUT_S3;  end generate;
4027 
    yhdl1085 : if (not((M2_AHBSLOTENABLE_slv( 3)) = '1')) generate M2_HREADYOUT_S3  <= '1';           end generate;
4028 
    yhdl1086 : if (    (M2_AHBSLOTENABLE_slv( 4)) = '1')  generate M2_HREADYOUT_S4  <= HREADYOUT_S4;  end generate;
4029 
    yhdl1087 : if (not((M2_AHBSLOTENABLE_slv( 4)) = '1')) generate M2_HREADYOUT_S4  <= '1';           end generate;
4030 
    yhdl1088 : if (    (M2_AHBSLOTENABLE_slv( 5)) = '1')  generate M2_HREADYOUT_S5  <= HREADYOUT_S5;  end generate;
4031 
    yhdl1089 : if (not((M2_AHBSLOTENABLE_slv( 5)) = '1')) generate M2_HREADYOUT_S5  <= '1';           end generate;
4032 
    yhdl1090 : if (    (M2_AHBSLOTENABLE_slv( 6)) = '1')  generate M2_HREADYOUT_S6  <= HREADYOUT_S6;  end generate;
4033 
    yhdl1091 : if (not((M2_AHBSLOTENABLE_slv( 6)) = '1')) generate M2_HREADYOUT_S6  <= '1';           end generate;
4034 
    yhdl1092 : if (    (M2_AHBSLOTENABLE_slv( 7)) = '1')  generate M2_HREADYOUT_S7  <= HREADYOUT_S7;  end generate;
4035 
    yhdl1093 : if (not((M2_AHBSLOTENABLE_slv( 7)) = '1')) generate M2_HREADYOUT_S7  <= '1';           end generate;
4036 
    yhdl1094 : if (    (M2_AHBSLOTENABLE_slv( 8)) = '1')  generate M2_HREADYOUT_S8  <= HREADYOUT_S8;  end generate;
4037 
    yhdl1095 : if (not((M2_AHBSLOTENABLE_slv( 8)) = '1')) generate M2_HREADYOUT_S8  <= '1';           end generate;
4038 
    yhdl1096 : if (    (M2_AHBSLOTENABLE_slv( 9)) = '1')  generate M2_HREADYOUT_S9  <= HREADYOUT_S9;  end generate;
4039 
    yhdl1097 : if (not((M2_AHBSLOTENABLE_slv( 9)) = '1')) generate M2_HREADYOUT_S9  <= '1';           end generate;
4040 
    yhdl1098 : if (    (M2_AHBSLOTENABLE_slv(10)) = '1')  generate M2_HREADYOUT_S10 <= HREADYOUT_S10; end generate;
4041 
    yhdl1099 : if (not((M2_AHBSLOTENABLE_slv(10)) = '1')) generate M2_HREADYOUT_S10 <= '1';           end generate;
4042 
    yhdl1100 : if (    (M2_AHBSLOTENABLE_slv(11)) = '1')  generate M2_HREADYOUT_S11 <= HREADYOUT_S11; end generate;
4043 
    yhdl1101 : if (not((M2_AHBSLOTENABLE_slv(11)) = '1')) generate M2_HREADYOUT_S11 <= '1';           end generate;
4044 
    yhdl1102 : if (    (M2_AHBSLOTENABLE_slv(12)) = '1')  generate M2_HREADYOUT_S12 <= HREADYOUT_S12; end generate;
4045 
    yhdl1103 : if (not((M2_AHBSLOTENABLE_slv(12)) = '1')) generate M2_HREADYOUT_S12 <= '1';           end generate;
4046 
    yhdl1104 : if (    (M2_AHBSLOTENABLE_slv(13)) = '1')  generate M2_HREADYOUT_S13 <= HREADYOUT_S13; end generate;
4047 
    yhdl1105 : if (not((M2_AHBSLOTENABLE_slv(13)) = '1')) generate M2_HREADYOUT_S13 <= '1';           end generate;
4048 
    yhdl1106 : if (    (M2_AHBSLOTENABLE_slv(14)) = '1')  generate M2_HREADYOUT_S14 <= HREADYOUT_S14; end generate;
4049 
    yhdl1107 : if (not((M2_AHBSLOTENABLE_slv(14)) = '1')) generate M2_HREADYOUT_S14 <= '1';           end generate;
4050 
    yhdl1108 : if (    (M2_AHBSLOTENABLE_slv(15)) = '1')  generate M2_HREADYOUT_S15 <= HREADYOUT_S15; end generate;
4051 
    yhdl1109 : if (not((M2_AHBSLOTENABLE_slv(15)) = '1')) generate M2_HREADYOUT_S15 <= '1';           end generate;
4052 
    yhdl1110 : if (    (M2_AHBSLOTENABLE_slv(16)) = '1')  generate M2_HREADYOUT_S16 <= HREADYOUT_S16; end generate;
4053 
    yhdl1111 : if (not((M2_AHBSLOTENABLE_slv(16)) = '1')) generate M2_HREADYOUT_S16 <= '1';           end generate;
4054 
    yhdl1114 : if (    (M3_AHBSLOTENABLE_slv( 0)) = '1')  generate M3_HREADYOUT_S0  <= HREADYOUT_S0;  end generate;
4055 
    yhdl1115 : if (not((M3_AHBSLOTENABLE_slv( 0)) = '1')) generate M3_HREADYOUT_S0  <= '1';           end generate;
4056 
    yhdl1116 : if (    (M3_AHBSLOTENABLE_slv( 1)) = '1')  generate M3_HREADYOUT_S1  <= HREADYOUT_S1;  end generate;
4057 
    yhdl1117 : if (not((M3_AHBSLOTENABLE_slv( 1)) = '1')) generate M3_HREADYOUT_S1  <= '1';           end generate;
4058 
    yhdl1118 : if (    (M3_AHBSLOTENABLE_slv( 2)) = '1')  generate M3_HREADYOUT_S2  <= HREADYOUT_S2;  end generate;
4059 
    yhdl1119 : if (not((M3_AHBSLOTENABLE_slv( 2)) = '1')) generate M3_HREADYOUT_S2  <= '1';           end generate;
4060 
    yhdl1120 : if (    (M3_AHBSLOTENABLE_slv( 3)) = '1')  generate M3_HREADYOUT_S3  <= HREADYOUT_S3;  end generate;
4061 
    yhdl1121 : if (not((M3_AHBSLOTENABLE_slv( 3)) = '1')) generate M3_HREADYOUT_S3  <= '1';           end generate;
4062 
    yhdl1122 : if (    (M3_AHBSLOTENABLE_slv( 4)) = '1')  generate M3_HREADYOUT_S4  <= HREADYOUT_S4;  end generate;
4063 
    yhdl1123 : if (not((M3_AHBSLOTENABLE_slv( 4)) = '1')) generate M3_HREADYOUT_S4  <= '1';           end generate;
4064 
    yhdl1124 : if (    (M3_AHBSLOTENABLE_slv( 5)) = '1')  generate M3_HREADYOUT_S5  <= HREADYOUT_S5;  end generate;
4065 
    yhdl1125 : if (not((M3_AHBSLOTENABLE_slv( 5)) = '1')) generate M3_HREADYOUT_S5  <= '1';           end generate;
4066 
    yhdl1126 : if (    (M3_AHBSLOTENABLE_slv( 6)) = '1')  generate M3_HREADYOUT_S6  <= HREADYOUT_S6;  end generate;
4067 
    yhdl1127 : if (not((M3_AHBSLOTENABLE_slv( 6)) = '1')) generate M3_HREADYOUT_S6  <= '1';           end generate;
4068 
    yhdl1128 : if (    (M3_AHBSLOTENABLE_slv( 7)) = '1')  generate M3_HREADYOUT_S7  <= HREADYOUT_S7;  end generate;
4069 
    yhdl1129 : if (not((M3_AHBSLOTENABLE_slv( 7)) = '1')) generate M3_HREADYOUT_S7  <= '1';           end generate;
4070 
    yhdl1130 : if (    (M3_AHBSLOTENABLE_slv( 8)) = '1')  generate M3_HREADYOUT_S8  <= HREADYOUT_S8;  end generate;
4071 
    yhdl1131 : if (not((M3_AHBSLOTENABLE_slv( 8)) = '1')) generate M3_HREADYOUT_S8  <= '1';           end generate;
4072 
    yhdl1132 : if (    (M3_AHBSLOTENABLE_slv( 9)) = '1')  generate M3_HREADYOUT_S9  <= HREADYOUT_S9;  end generate;
4073 
    yhdl1133 : if (not((M3_AHBSLOTENABLE_slv( 9)) = '1')) generate M3_HREADYOUT_S9  <= '1';           end generate;
4074 
    yhdl1134 : if (    (M3_AHBSLOTENABLE_slv(10)) = '1')  generate M3_HREADYOUT_S10 <= HREADYOUT_S10; end generate;
4075 
    yhdl1135 : if (not((M3_AHBSLOTENABLE_slv(10)) = '1')) generate M3_HREADYOUT_S10 <= '1';           end generate;
4076 
    yhdl1136 : if (    (M3_AHBSLOTENABLE_slv(11)) = '1')  generate M3_HREADYOUT_S11 <= HREADYOUT_S11; end generate;
4077 
    yhdl1137 : if (not((M3_AHBSLOTENABLE_slv(11)) = '1')) generate M3_HREADYOUT_S11 <= '1';           end generate;
4078 
    yhdl1138 : if (    (M3_AHBSLOTENABLE_slv(12)) = '1')  generate M3_HREADYOUT_S12 <= HREADYOUT_S12; end generate;
4079 
    yhdl1139 : if (not((M3_AHBSLOTENABLE_slv(12)) = '1')) generate M3_HREADYOUT_S12 <= '1';           end generate;
4080 
    yhdl1140 : if (    (M3_AHBSLOTENABLE_slv(13)) = '1')  generate M3_HREADYOUT_S13 <= HREADYOUT_S13; end generate;
4081 
    yhdl1141 : if (not((M3_AHBSLOTENABLE_slv(13)) = '1')) generate M3_HREADYOUT_S13 <= '1';           end generate;
4082 
    yhdl1142 : if (    (M3_AHBSLOTENABLE_slv(14)) = '1')  generate M3_HREADYOUT_S14 <= HREADYOUT_S14; end generate;
4083 
    yhdl1143 : if (not((M3_AHBSLOTENABLE_slv(14)) = '1')) generate M3_HREADYOUT_S14 <= '1';           end generate;
4084 
    yhdl1144 : if (    (M3_AHBSLOTENABLE_slv(15)) = '1')  generate M3_HREADYOUT_S15 <= HREADYOUT_S15; end generate;
4085 
    yhdl1145 : if (not((M3_AHBSLOTENABLE_slv(15)) = '1')) generate M3_HREADYOUT_S15 <= '1';           end generate;
4086 
    yhdl1146 : if (    (M3_AHBSLOTENABLE_slv(16)) = '1')  generate M3_HREADYOUT_S16 <= HREADYOUT_S16; end generate;
4087 
    yhdl1147 : if (not((M3_AHBSLOTENABLE_slv(16)) = '1')) generate M3_HREADYOUT_S16 <= '1';           end generate;
4088 
 
4089 
 
4090 
    xhdl1150 : if (   ( M0_AHBSLOTENABLE_slv( 0) or M1_AHBSLOTENABLE_slv( 0) or M2_AHBSLOTENABLE_slv( 0) or M3_AHBSLOTENABLE_slv( 0)) = '1')  generate INT_HREADYOUT_S0  <= HREADYOUT_S0;  end generate;
4091 
    xhdl1151 : if (not((M0_AHBSLOTENABLE_slv( 0) or M1_AHBSLOTENABLE_slv( 0) or M2_AHBSLOTENABLE_slv( 0) or M3_AHBSLOTENABLE_slv( 0)) = '1')) generate INT_HREADYOUT_S0  <= '1';           end generate;
4092 
    xhdl1152 : if (   ( M0_AHBSLOTENABLE_slv( 1) or M1_AHBSLOTENABLE_slv( 1) or M2_AHBSLOTENABLE_slv( 1) or M3_AHBSLOTENABLE_slv( 1)) = '1')  generate INT_HREADYOUT_S1  <= HREADYOUT_S1;  end generate;
4093 
    xhdl1153 : if (not((M0_AHBSLOTENABLE_slv( 1) or M1_AHBSLOTENABLE_slv( 1) or M2_AHBSLOTENABLE_slv( 1) or M3_AHBSLOTENABLE_slv( 1)) = '1')) generate INT_HREADYOUT_S1  <= '1';           end generate;
4094 
    xhdl1154 : if (   ( M0_AHBSLOTENABLE_slv( 2) or M1_AHBSLOTENABLE_slv( 2) or M2_AHBSLOTENABLE_slv( 2) or M3_AHBSLOTENABLE_slv( 2)) = '1')  generate INT_HREADYOUT_S2  <= HREADYOUT_S2;  end generate;
4095 
    xhdl1155 : if (not((M0_AHBSLOTENABLE_slv( 2) or M1_AHBSLOTENABLE_slv( 2) or M2_AHBSLOTENABLE_slv( 2) or M3_AHBSLOTENABLE_slv( 2)) = '1')) generate INT_HREADYOUT_S2  <= '1';           end generate;
4096 
    xhdl1156 : if (   ( M0_AHBSLOTENABLE_slv( 3) or M1_AHBSLOTENABLE_slv( 3) or M2_AHBSLOTENABLE_slv( 3) or M3_AHBSLOTENABLE_slv( 3)) = '1')  generate INT_HREADYOUT_S3  <= HREADYOUT_S3;  end generate;
4097 
    xhdl1157 : if (not((M0_AHBSLOTENABLE_slv( 3) or M1_AHBSLOTENABLE_slv( 3) or M2_AHBSLOTENABLE_slv( 3) or M3_AHBSLOTENABLE_slv( 3)) = '1')) generate INT_HREADYOUT_S3  <= '1';           end generate;
4098 
    xhdl1158 : if (   ( M0_AHBSLOTENABLE_slv( 4) or M1_AHBSLOTENABLE_slv( 4) or M2_AHBSLOTENABLE_slv( 4) or M3_AHBSLOTENABLE_slv( 4)) = '1')  generate INT_HREADYOUT_S4  <= HREADYOUT_S4;  end generate;
4099 
    xhdl1159 : if (not((M0_AHBSLOTENABLE_slv( 4) or M1_AHBSLOTENABLE_slv( 4) or M2_AHBSLOTENABLE_slv( 4) or M3_AHBSLOTENABLE_slv( 4)) = '1')) generate INT_HREADYOUT_S4  <= '1';           end generate;
4100 
    xhdl1160 : if (   ( M0_AHBSLOTENABLE_slv( 5) or M1_AHBSLOTENABLE_slv( 5) or M2_AHBSLOTENABLE_slv( 5) or M3_AHBSLOTENABLE_slv( 5)) = '1')  generate INT_HREADYOUT_S5  <= HREADYOUT_S5;  end generate;
4101 
    xhdl1161 : if (not((M0_AHBSLOTENABLE_slv( 5) or M1_AHBSLOTENABLE_slv( 5) or M2_AHBSLOTENABLE_slv( 5) or M3_AHBSLOTENABLE_slv( 5)) = '1')) generate INT_HREADYOUT_S5  <= '1';           end generate;
4102 
    xhdl1162 : if (   ( M0_AHBSLOTENABLE_slv( 6) or M1_AHBSLOTENABLE_slv( 6) or M2_AHBSLOTENABLE_slv( 6) or M3_AHBSLOTENABLE_slv( 6)) = '1')  generate INT_HREADYOUT_S6  <= HREADYOUT_S6;  end generate;
4103 
    xhdl1163 : if (not((M0_AHBSLOTENABLE_slv( 6) or M1_AHBSLOTENABLE_slv( 6) or M2_AHBSLOTENABLE_slv( 6) or M3_AHBSLOTENABLE_slv( 6)) = '1')) generate INT_HREADYOUT_S6  <= '1';           end generate;
4104 
    xhdl1164 : if (   ( M0_AHBSLOTENABLE_slv( 7) or M1_AHBSLOTENABLE_slv( 7) or M2_AHBSLOTENABLE_slv( 7) or M3_AHBSLOTENABLE_slv( 7)) = '1')  generate INT_HREADYOUT_S7  <= HREADYOUT_S7;  end generate;
4105 
    xhdl1165 : if (not((M0_AHBSLOTENABLE_slv( 7) or M1_AHBSLOTENABLE_slv( 7) or M2_AHBSLOTENABLE_slv( 7) or M3_AHBSLOTENABLE_slv( 7)) = '1')) generate INT_HREADYOUT_S7  <= '1';           end generate;
4106 
    xhdl1166 : if (   ( M0_AHBSLOTENABLE_slv( 8) or M1_AHBSLOTENABLE_slv( 8) or M2_AHBSLOTENABLE_slv( 8) or M3_AHBSLOTENABLE_slv( 8)) = '1')  generate INT_HREADYOUT_S8  <= HREADYOUT_S8;  end generate;
4107 
    xhdl1167 : if (not((M0_AHBSLOTENABLE_slv( 8) or M1_AHBSLOTENABLE_slv( 8) or M2_AHBSLOTENABLE_slv( 8) or M3_AHBSLOTENABLE_slv( 8)) = '1')) generate INT_HREADYOUT_S8  <= '1';           end generate;
4108 
    xhdl1168 : if (   ( M0_AHBSLOTENABLE_slv( 9) or M1_AHBSLOTENABLE_slv( 9) or M2_AHBSLOTENABLE_slv( 9) or M3_AHBSLOTENABLE_slv( 9)) = '1')  generate INT_HREADYOUT_S9  <= HREADYOUT_S9;  end generate;
4109 
    xhdl1169 : if (not((M0_AHBSLOTENABLE_slv( 9) or M1_AHBSLOTENABLE_slv( 9) or M2_AHBSLOTENABLE_slv( 9) or M3_AHBSLOTENABLE_slv( 9)) = '1')) generate INT_HREADYOUT_S9  <= '1';           end generate;
4110 
    xhdl1170 : if (   ( M0_AHBSLOTENABLE_slv(10) or M1_AHBSLOTENABLE_slv(10) or M2_AHBSLOTENABLE_slv(10) or M3_AHBSLOTENABLE_slv(10)) = '1')  generate INT_HREADYOUT_S10 <= HREADYOUT_S10; end generate;
4111 
    xhdl1171 : if (not((M0_AHBSLOTENABLE_slv(10) or M1_AHBSLOTENABLE_slv(10) or M2_AHBSLOTENABLE_slv(10) or M3_AHBSLOTENABLE_slv(10)) = '1')) generate INT_HREADYOUT_S10 <= '1';           end generate;
4112 
    xhdl1172 : if (   ( M0_AHBSLOTENABLE_slv(11) or M1_AHBSLOTENABLE_slv(11) or M2_AHBSLOTENABLE_slv(11) or M3_AHBSLOTENABLE_slv(11)) = '1')  generate INT_HREADYOUT_S11 <= HREADYOUT_S11; end generate;
4113 
    xhdl1173 : if (not((M0_AHBSLOTENABLE_slv(11) or M1_AHBSLOTENABLE_slv(11) or M2_AHBSLOTENABLE_slv(11) or M3_AHBSLOTENABLE_slv(11)) = '1')) generate INT_HREADYOUT_S11 <= '1';           end generate;
4114 
    xhdl1174 : if (   ( M0_AHBSLOTENABLE_slv(12) or M1_AHBSLOTENABLE_slv(12) or M2_AHBSLOTENABLE_slv(12) or M3_AHBSLOTENABLE_slv(12)) = '1')  generate INT_HREADYOUT_S12 <= HREADYOUT_S12; end generate;
4115 
    xhdl1175 : if (not((M0_AHBSLOTENABLE_slv(12) or M1_AHBSLOTENABLE_slv(12) or M2_AHBSLOTENABLE_slv(12) or M3_AHBSLOTENABLE_slv(12)) = '1')) generate INT_HREADYOUT_S12 <= '1';           end generate;
4116 
    xhdl1176 : if (   ( M0_AHBSLOTENABLE_slv(13) or M1_AHBSLOTENABLE_slv(13) or M2_AHBSLOTENABLE_slv(13) or M3_AHBSLOTENABLE_slv(13)) = '1')  generate INT_HREADYOUT_S13 <= HREADYOUT_S13; end generate;
4117 
    xhdl1177 : if (not((M0_AHBSLOTENABLE_slv(13) or M1_AHBSLOTENABLE_slv(13) or M2_AHBSLOTENABLE_slv(13) or M3_AHBSLOTENABLE_slv(13)) = '1')) generate INT_HREADYOUT_S13 <= '1';           end generate;
4118 
    xhdl1178 : if (   ( M0_AHBSLOTENABLE_slv(14) or M1_AHBSLOTENABLE_slv(14) or M2_AHBSLOTENABLE_slv(14) or M3_AHBSLOTENABLE_slv(14)) = '1')  generate INT_HREADYOUT_S14 <= HREADYOUT_S14; end generate;
4119 
    xhdl1179 : if (not((M0_AHBSLOTENABLE_slv(14) or M1_AHBSLOTENABLE_slv(14) or M2_AHBSLOTENABLE_slv(14) or M3_AHBSLOTENABLE_slv(14)) = '1')) generate INT_HREADYOUT_S14 <= '1';           end generate;
4120 
    xhdl1180 : if (   ( M0_AHBSLOTENABLE_slv(15) or M1_AHBSLOTENABLE_slv(15) or M2_AHBSLOTENABLE_slv(15) or M3_AHBSLOTENABLE_slv(15)) = '1')  generate INT_HREADYOUT_S15 <= HREADYOUT_S15; end generate;
4121 
    xhdl1181 : if (not((M0_AHBSLOTENABLE_slv(15) or M1_AHBSLOTENABLE_slv(15) or M2_AHBSLOTENABLE_slv(15) or M3_AHBSLOTENABLE_slv(15)) = '1')) generate INT_HREADYOUT_S15 <= '1';           end generate;
4122 
    xhdl1182 : if (   ( M0_AHBSLOTENABLE_slv(16) or M1_AHBSLOTENABLE_slv(16) or M2_AHBSLOTENABLE_slv(16) or M3_AHBSLOTENABLE_slv(16)) = '1')  generate INT_HREADYOUT_S16 <= HREADYOUT_S16; end generate;
4123 
    xhdl1183 : if (not((M0_AHBSLOTENABLE_slv(16) or M1_AHBSLOTENABLE_slv(16) or M2_AHBSLOTENABLE_slv(16) or M3_AHBSLOTENABLE_slv(16)) = '1')) generate INT_HREADYOUT_S16 <= '1';           end generate;
4124 
    xhdl1184 : if (   ( M0_AHBSLOTENABLE_slv( 0) or M1_AHBSLOTENABLE_slv( 0) or M2_AHBSLOTENABLE_slv( 0) or M3_AHBSLOTENABLE_slv( 0)) = '1')  generate INT_HRESP_S0  <= HRESP_S0;  end generate;
4125 
    xhdl1185 : if (not((M0_AHBSLOTENABLE_slv( 0) or M1_AHBSLOTENABLE_slv( 0) or M2_AHBSLOTENABLE_slv( 0) or M3_AHBSLOTENABLE_slv( 0)) = '1')) generate INT_HRESP_S0  <= '0';       end generate;
4126 
    xhdl1186 : if (   ( M0_AHBSLOTENABLE_slv( 1) or M1_AHBSLOTENABLE_slv( 1) or M2_AHBSLOTENABLE_slv( 1) or M3_AHBSLOTENABLE_slv( 1)) = '1')  generate INT_HRESP_S1  <= HRESP_S1;  end generate;
4127 
    xhdl1187 : if (not((M0_AHBSLOTENABLE_slv( 1) or M1_AHBSLOTENABLE_slv( 1) or M2_AHBSLOTENABLE_slv( 1) or M3_AHBSLOTENABLE_slv( 1)) = '1')) generate INT_HRESP_S1  <= '0';       end generate;
4128 
    xhdl1188 : if (   ( M0_AHBSLOTENABLE_slv( 2) or M1_AHBSLOTENABLE_slv( 2) or M2_AHBSLOTENABLE_slv( 2) or M3_AHBSLOTENABLE_slv( 2)) = '1')  generate INT_HRESP_S2  <= HRESP_S2;  end generate;
4129 
    xhdl1189 : if (not((M0_AHBSLOTENABLE_slv( 2) or M1_AHBSLOTENABLE_slv( 2) or M2_AHBSLOTENABLE_slv( 2) or M3_AHBSLOTENABLE_slv( 2)) = '1')) generate INT_HRESP_S2  <= '0';       end generate;
4130 
    xhdl1190 : if (   ( M0_AHBSLOTENABLE_slv( 3) or M1_AHBSLOTENABLE_slv( 3) or M2_AHBSLOTENABLE_slv( 3) or M3_AHBSLOTENABLE_slv( 3)) = '1')  generate INT_HRESP_S3  <= HRESP_S3;  end generate;
4131 
    xhdl1191 : if (not((M0_AHBSLOTENABLE_slv( 3) or M1_AHBSLOTENABLE_slv( 3) or M2_AHBSLOTENABLE_slv( 3) or M3_AHBSLOTENABLE_slv( 3)) = '1')) generate INT_HRESP_S3  <= '0';       end generate;
4132 
    xhdl1192 : if (   ( M0_AHBSLOTENABLE_slv( 4) or M1_AHBSLOTENABLE_slv( 4) or M2_AHBSLOTENABLE_slv( 4) or M3_AHBSLOTENABLE_slv( 4)) = '1')  generate INT_HRESP_S4  <= HRESP_S4;  end generate;
4133 
    xhdl1193 : if (not((M0_AHBSLOTENABLE_slv( 4) or M1_AHBSLOTENABLE_slv( 4) or M2_AHBSLOTENABLE_slv( 4) or M3_AHBSLOTENABLE_slv( 4)) = '1')) generate INT_HRESP_S4  <= '0';       end generate;
4134 
    xhdl1194 : if (   ( M0_AHBSLOTENABLE_slv( 5) or M1_AHBSLOTENABLE_slv( 5) or M2_AHBSLOTENABLE_slv( 5) or M3_AHBSLOTENABLE_slv( 5)) = '1')  generate INT_HRESP_S5  <= HRESP_S5;  end generate;
4135 
    xhdl1195 : if (not((M0_AHBSLOTENABLE_slv( 5) or M1_AHBSLOTENABLE_slv( 5) or M2_AHBSLOTENABLE_slv( 5) or M3_AHBSLOTENABLE_slv( 5)) = '1')) generate INT_HRESP_S5  <= '0';       end generate;
4136 
    xhdl1196 : if (   ( M0_AHBSLOTENABLE_slv( 6) or M1_AHBSLOTENABLE_slv( 6) or M2_AHBSLOTENABLE_slv( 6) or M3_AHBSLOTENABLE_slv( 6)) = '1')  generate INT_HRESP_S6  <= HRESP_S6;  end generate;
4137 
    xhdl1197 : if (not((M0_AHBSLOTENABLE_slv( 6) or M1_AHBSLOTENABLE_slv( 6) or M2_AHBSLOTENABLE_slv( 6) or M3_AHBSLOTENABLE_slv( 6)) = '1')) generate INT_HRESP_S6  <= '0';       end generate;
4138 
    xhdl1198 : if (   ( M0_AHBSLOTENABLE_slv( 7) or M1_AHBSLOTENABLE_slv( 7) or M2_AHBSLOTENABLE_slv( 7) or M3_AHBSLOTENABLE_slv( 7)) = '1')  generate INT_HRESP_S7  <= HRESP_S7;  end generate;
4139 
    xhdl1199 : if (not((M0_AHBSLOTENABLE_slv( 7) or M1_AHBSLOTENABLE_slv( 7) or M2_AHBSLOTENABLE_slv( 7) or M3_AHBSLOTENABLE_slv( 7)) = '1')) generate INT_HRESP_S7  <= '0';       end generate;
4140 
    xhdl1200 : if (   ( M0_AHBSLOTENABLE_slv( 8) or M1_AHBSLOTENABLE_slv( 8) or M2_AHBSLOTENABLE_slv( 8) or M3_AHBSLOTENABLE_slv( 8)) = '1')  generate INT_HRESP_S8  <= HRESP_S8;  end generate;
4141 
    xhdl1201 : if (not((M0_AHBSLOTENABLE_slv( 8) or M1_AHBSLOTENABLE_slv( 8) or M2_AHBSLOTENABLE_slv( 8) or M3_AHBSLOTENABLE_slv( 8)) = '1')) generate INT_HRESP_S8  <= '0';       end generate;
4142 
    xhdl1202 : if (   ( M0_AHBSLOTENABLE_slv( 9) or M1_AHBSLOTENABLE_slv( 9) or M2_AHBSLOTENABLE_slv( 9) or M3_AHBSLOTENABLE_slv( 9)) = '1')  generate INT_HRESP_S9  <= HRESP_S9;  end generate;
4143 
    xhdl1203 : if (not((M0_AHBSLOTENABLE_slv( 9) or M1_AHBSLOTENABLE_slv( 9) or M2_AHBSLOTENABLE_slv( 9) or M3_AHBSLOTENABLE_slv( 9)) = '1')) generate INT_HRESP_S9  <= '0';       end generate;
4144 
    xhdl1204 : if (   ( M0_AHBSLOTENABLE_slv(10) or M1_AHBSLOTENABLE_slv(10) or M2_AHBSLOTENABLE_slv(10) or M3_AHBSLOTENABLE_slv(10)) = '1')  generate INT_HRESP_S10 <= HRESP_S10; end generate;
4145 
    xhdl1205 : if (not((M0_AHBSLOTENABLE_slv(10) or M1_AHBSLOTENABLE_slv(10) or M2_AHBSLOTENABLE_slv(10) or M3_AHBSLOTENABLE_slv(10)) = '1')) generate INT_HRESP_S10 <= '0';       end generate;
4146 
    xhdl1206 : if (   ( M0_AHBSLOTENABLE_slv(11) or M1_AHBSLOTENABLE_slv(11) or M2_AHBSLOTENABLE_slv(11) or M3_AHBSLOTENABLE_slv(11)) = '1')  generate INT_HRESP_S11 <= HRESP_S11; end generate;
4147 
    xhdl1207 : if (not((M0_AHBSLOTENABLE_slv(11) or M1_AHBSLOTENABLE_slv(11) or M2_AHBSLOTENABLE_slv(11) or M3_AHBSLOTENABLE_slv(11)) = '1')) generate INT_HRESP_S11 <= '0';       end generate;
4148 
    xhdl1208 : if (   ( M0_AHBSLOTENABLE_slv(12) or M1_AHBSLOTENABLE_slv(12) or M2_AHBSLOTENABLE_slv(12) or M3_AHBSLOTENABLE_slv(12)) = '1')  generate INT_HRESP_S12 <= HRESP_S12; end generate;
4149 
    xhdl1209 : if (not((M0_AHBSLOTENABLE_slv(12) or M1_AHBSLOTENABLE_slv(12) or M2_AHBSLOTENABLE_slv(12) or M3_AHBSLOTENABLE_slv(12)) = '1')) generate INT_HRESP_S12 <= '0';       end generate;
4150 
    xhdl1210 : if (   ( M0_AHBSLOTENABLE_slv(13) or M1_AHBSLOTENABLE_slv(13) or M2_AHBSLOTENABLE_slv(13) or M3_AHBSLOTENABLE_slv(13)) = '1')  generate INT_HRESP_S13 <= HRESP_S13; end generate;
4151 
    xhdl1211 : if (not((M0_AHBSLOTENABLE_slv(13) or M1_AHBSLOTENABLE_slv(13) or M2_AHBSLOTENABLE_slv(13) or M3_AHBSLOTENABLE_slv(13)) = '1')) generate INT_HRESP_S13 <= '0';       end generate;
4152 
    xhdl1212 : if (   ( M0_AHBSLOTENABLE_slv(14) or M1_AHBSLOTENABLE_slv(14) or M2_AHBSLOTENABLE_slv(14) or M3_AHBSLOTENABLE_slv(14)) = '1')  generate INT_HRESP_S14 <= HRESP_S14; end generate;
4153 
    xhdl1213 : if (not((M0_AHBSLOTENABLE_slv(14) or M1_AHBSLOTENABLE_slv(14) or M2_AHBSLOTENABLE_slv(14) or M3_AHBSLOTENABLE_slv(14)) = '1')) generate INT_HRESP_S14 <= '0';       end generate;
4154 
    xhdl1214 : if (   ( M0_AHBSLOTENABLE_slv(15) or M1_AHBSLOTENABLE_slv(15) or M2_AHBSLOTENABLE_slv(15) or M3_AHBSLOTENABLE_slv(15)) = '1')  generate INT_HRESP_S15 <= HRESP_S15; end generate;
4155 
    xhdl1215 : if (not((M0_AHBSLOTENABLE_slv(15) or M1_AHBSLOTENABLE_slv(15) or M2_AHBSLOTENABLE_slv(15) or M3_AHBSLOTENABLE_slv(15)) = '1')) generate INT_HRESP_S15 <= '0';       end generate;
4156 
    xhdl1216 : if (   ( M0_AHBSLOTENABLE_slv(16) or M1_AHBSLOTENABLE_slv(16) or M2_AHBSLOTENABLE_slv(16) or M3_AHBSLOTENABLE_slv(16)) = '1')  generate INT_HRESP_S16 <= HRESP_S16; end generate;
4157 
    xhdl1217 : if (not((M0_AHBSLOTENABLE_slv(16) or M1_AHBSLOTENABLE_slv(16) or M2_AHBSLOTENABLE_slv(16) or M3_AHBSLOTENABLE_slv(16)) = '1')) generate INT_HRESP_S16 <= '0';       end generate;
4158 
 
4159 
 
4160 
    xhdl1218 <= (s16m0AddrReady_int & s15m0AddrReady_int & s14m0AddrReady_int & s13m0AddrReady_int & s12m0AddrReady_int & s11m0AddrReady_int & s10m0AddrReady_int & s9m0AddrReady_int & s8m0AddrReady_int & s7m0AddrReady_int & s6m0AddrReady_int & s5m0AddrReady_int & s4m0AddrReady_int & s3m0AddrReady_int & s2m0AddrReady_int & s1m0AddrReady_int & s0m0AddrReady_int);
4161 
    xhdl1219 <= (s16m0DataReady_int & s15m0DataReady_int & s14m0DataReady_int & s13m0DataReady_int & s12m0DataReady_int & s11m0DataReady_int & s10m0DataReady_int & s9m0DataReady_int & s8m0DataReady_int & s7m0DataReady_int & s6m0DataReady_int & s5m0DataReady_int & s4m0DataReady_int & s3m0DataReady_int & s2m0DataReady_int & s1m0DataReady_int & s0m0DataReady_int);
4162 
    xhdl1220 <= (s16m0HResp_int & s15m0HResp_int & s14m0HResp_int & s13m0HResp_int & s12m0HResp_int & s11m0HResp_int & s10m0HResp_int & s9m0HResp_int & s8m0HResp_int & s7m0HResp_int & s6m0HResp_int & s5m0HResp_int & s4m0HResp_int & s3m0HResp_int & s2m0HResp_int & s1m0HResp_int & s0m0HResp_int);
4163 
    (m0s16AddrSel, m0s15AddrSel, m0s14AddrSel, m0s13AddrSel, m0s12AddrSel, m0s11AddrSel, m0s10AddrSel, m0s9AddrSel, m0s8AddrSel, m0s7AddrSel, m0s6AddrSel, m0s5AddrSel, m0s4AddrSel, m0s3AddrSel, m0s2AddrSel, m0s1AddrSel, m0s0AddrSel) <= xhdl1221;
4164 
    (m0s16DataSel, m0s15DataSel, m0s14DataSel, m0s13DataSel, m0s12DataSel, m0s11DataSel, m0s10DataSel, m0s9DataSel, m0s8DataSel, m0s7DataSel, m0s6DataSel, m0s5DataSel, m0s4DataSel, m0s3DataSel, m0s2DataSel, m0s1DataSel, m0s0DataSel) <= xhdl1222;
4165 
    masterstage_0 : COREAHBLITE_MASTERSTAGE
4166 
        generic map (
4167 
            MEMSPACE         => MEMSPACE,
4168 
            HADDR_SHG_CFG    => HADDR_SHG_CFG,
4169 
            SC               => SC,
4170 
            M_AHBSLOTENABLE  => M0_AHBSLOTENABLE,
4171 
                        SYNC_RESET       => SYNC_RESET
4172 
        )
4173 
        port map (
4174 
            HCLK                => HCLK,
4175 
            HRESETN             => HRESETN,
4176 
            REMAP               => REMAP_M0,
4177 
            HADDR               => HADDR_M0,
4178 
            HMASTLOCK           => HMASTLOCK_M0,
4179 
            HSIZE               => HSIZE_M0,
4180 
            HTRANS              => HTRANS_M0,
4181 
            HWRITE              => HWRITE_M0,
4182 
            HRESP               => HRESP_M0_xhdl55,
4183 
            HRDATA              => HRDATA_M0_xhdl34,
4184 
            HREADY_M            => HREADY_M0_pre,
4185 
            SADDRREADY          => xhdl1218,
4186 
            SDATAREADY          => xhdl1219,
4187 
            SHRESP              => xhdl1220,
4188 
            GATEDHADDR          => M0GATEDHADDR,
4189 
            GATEDHMASTLOCK      => M0GATEDHMASTLOCK,
4190 
            GATEDHSIZE          => M0GATEDHSIZE,
4191 
            GATEDHTRANS         => M0GATEDHTRANS,
4192 
            GATEDHWRITE         => M0GATEDHWRITE,
4193 
            SADDRSEL            => xhdl1221,
4194 
            SDATASEL            => xhdl1222,
4195 
            PREVDATASLAVEREADY  => m0PrevDataSlaveReady,
4196 
            HRDATA_S0           => M0_HRDATA_S0,
4197 
            HREADYOUT_S0        => M0_HREADYOUT_S0,
4198 
            HRDATA_S1           => M0_HRDATA_S1,
4199 
            HREADYOUT_S1        => M0_HREADYOUT_S1,
4200 
            HRDATA_S2           => M0_HRDATA_S2,
4201 
            HREADYOUT_S2        => M0_HREADYOUT_S2,
4202 
            HRDATA_S3           => M0_HRDATA_S3,
4203 
            HREADYOUT_S3        => M0_HREADYOUT_S3,
4204 
            HRDATA_S4           => M0_HRDATA_S4,
4205 
            HREADYOUT_S4        => M0_HREADYOUT_S4,
4206 
            HRDATA_S5           => M0_HRDATA_S5,
4207 
            HREADYOUT_S5        => M0_HREADYOUT_S5,
4208 
            HRDATA_S6           => M0_HRDATA_S6,
4209 
            HREADYOUT_S6        => M0_HREADYOUT_S6,
4210 
            HRDATA_S7           => M0_HRDATA_S7,
4211 
            HREADYOUT_S7        => M0_HREADYOUT_S7,
4212 
            HRDATA_S8           => M0_HRDATA_S8,
4213 
            HREADYOUT_S8        => M0_HREADYOUT_S8,
4214 
            HRDATA_S9           => M0_HRDATA_S9,
4215 
            HREADYOUT_S9        => M0_HREADYOUT_S9,
4216 
            HRDATA_S10          => M0_HRDATA_S10,
4217 
            HREADYOUT_S10       => M0_HREADYOUT_S10,
4218 
            HRDATA_S11          => M0_HRDATA_S11,
4219 
            HREADYOUT_S11       => M0_HREADYOUT_S11,
4220 
            HRDATA_S12          => M0_HRDATA_S12,
4221 
            HREADYOUT_S12       => M0_HREADYOUT_S12,
4222 
            HRDATA_S13          => M0_HRDATA_S13,
4223 
            HREADYOUT_S13       => M0_HREADYOUT_S13,
4224 
            HRDATA_S14          => M0_HRDATA_S14,
4225 
            HREADYOUT_S14       => M0_HREADYOUT_S14,
4226 
            HRDATA_S15          => M0_HRDATA_S15,
4227 
            HREADYOUT_S15       => M0_HREADYOUT_S15,
4228 
            HRDATA_S16          => M0_HRDATA_S16,
4229 
            HREADYOUT_S16       => M0_HREADYOUT_S16
4230 
        );
4231 
 
4232 
 
4233 
    xhdl1223 <= (s16m1AddrReady_int & s15m1AddrReady_int & s14m1AddrReady_int & s13m1AddrReady_int & s12m1AddrReady_int & s11m1AddrReady_int & s10m1AddrReady_int & s9m1AddrReady_int & s8m1AddrReady_int & s7m1AddrReady_int & s6m1AddrReady_int & s5m1AddrReady_int & s4m1AddrReady_int & s3m1AddrReady_int & s2m1AddrReady_int & s1m1AddrReady_int & s0m1AddrReady_int);
4234 
    xhdl1224 <= (s16m1DataReady_int & s15m1DataReady_int & s14m1DataReady_int & s13m1DataReady_int & s12m1DataReady_int & s11m1DataReady_int & s10m1DataReady_int & s9m1DataReady_int & s8m1DataReady_int & s7m1DataReady_int & s6m1DataReady_int & s5m1DataReady_int & s4m1DataReady_int & s3m1DataReady_int & s2m1DataReady_int & s1m1DataReady_int & s0m1DataReady_int);
4235 
    xhdl1225 <= (s16m1HResp_int & s15m1HResp_int & s14m1HResp_int & s13m1HResp_int & s12m1HResp_int & s11m1HResp_int & s10m1HResp_int & s9m1HResp_int & s8m1HResp_int & s7m1HResp_int & s6m1HResp_int & s5m1HResp_int & s4m1HResp_int & s3m1HResp_int & s2m1HResp_int & s1m1HResp_int & s0m1HResp_int);
4236 
    (m1s16AddrSel, m1s15AddrSel, m1s14AddrSel, m1s13AddrSel, m1s12AddrSel, m1s11AddrSel, m1s10AddrSel, m1s9AddrSel, m1s8AddrSel, m1s7AddrSel, m1s6AddrSel, m1s5AddrSel, m1s4AddrSel, m1s3AddrSel, m1s2AddrSel, m1s1AddrSel, m1s0AddrSel) <= xhdl1226;
4237 
    (m1s16DataSel, m1s15DataSel, m1s14DataSel, m1s13DataSel, m1s12DataSel, m1s11DataSel, m1s10DataSel, m1s9DataSel, m1s8DataSel, m1s7DataSel, m1s6DataSel, m1s5DataSel, m1s4DataSel, m1s3DataSel, m1s2DataSel, m1s1DataSel, m1s0DataSel) <= xhdl1227;
4238 
    masterstage_1 : COREAHBLITE_MASTERSTAGE
4239 
        generic map (
4240 
            MEMSPACE         => MEMSPACE,
4241 
            HADDR_SHG_CFG    => HADDR_SHG_CFG,
4242 
            SC               => SC,
4243 
            M_AHBSLOTENABLE  => M1_AHBSLOTENABLE,
4244 
                        SYNC_RESET       => SYNC_RESET
4245 
        )
4246 
        port map (
4247 
            HCLK                => HCLK,
4248 
            HRESETN             => HRESETN,
4249 
            REMAP               => '0',
4250 
            HADDR               => HADDR_M1,
4251 
            HMASTLOCK           => HMASTLOCK_M1,
4252 
            HSIZE               => HSIZE_M1,
4253 
            HTRANS              => HTRANS_M1,
4254 
            HWRITE              => HWRITE_M1,
4255 
            HRESP               => HRESP_M1_xhdl56,
4256 
            HRDATA              => HRDATA_M1_xhdl35,
4257 
            HREADY_M            => HREADY_M1_pre,
4258 
            SADDRREADY          => xhdl1223,
4259 
            SDATAREADY          => xhdl1224,
4260 
            SHRESP              => xhdl1225,
4261 
            GATEDHADDR          => M1GATEDHADDR,
4262 
            GATEDHMASTLOCK      => M1GATEDHMASTLOCK,
4263 
            GATEDHSIZE          => M1GATEDHSIZE,
4264 
            GATEDHTRANS         => M1GATEDHTRANS,
4265 
            GATEDHWRITE         => M1GATEDHWRITE,
4266 
            SADDRSEL            => xhdl1226,
4267 
            SDATASEL            => xhdl1227,
4268 
            PREVDATASLAVEREADY  => m1PrevDataSlaveReady,
4269 
            HRDATA_S0           => M1_HRDATA_S0,
4270 
            HREADYOUT_S0        => M1_HREADYOUT_S0,
4271 
            HRDATA_S1           => M1_HRDATA_S1,
4272 
            HREADYOUT_S1        => M1_HREADYOUT_S1,
4273 
            HRDATA_S2           => M1_HRDATA_S2,
4274 
            HREADYOUT_S2        => M1_HREADYOUT_S2,
4275 
            HRDATA_S3           => M1_HRDATA_S3,
4276 
            HREADYOUT_S3        => M1_HREADYOUT_S3,
4277 
            HRDATA_S4           => M1_HRDATA_S4,
4278 
            HREADYOUT_S4        => M1_HREADYOUT_S4,
4279 
            HRDATA_S5           => M1_HRDATA_S5,
4280 
            HREADYOUT_S5        => M1_HREADYOUT_S5,
4281 
            HRDATA_S6           => M1_HRDATA_S6,
4282 
            HREADYOUT_S6        => M1_HREADYOUT_S6,
4283 
            HRDATA_S7           => M1_HRDATA_S7,
4284 
            HREADYOUT_S7        => M1_HREADYOUT_S7,
4285 
            HRDATA_S8           => M1_HRDATA_S8,
4286 
            HREADYOUT_S8        => M1_HREADYOUT_S8,
4287 
            HRDATA_S9           => M1_HRDATA_S9,
4288 
            HREADYOUT_S9        => M1_HREADYOUT_S9,
4289 
            HRDATA_S10          => M1_HRDATA_S10,
4290 
            HREADYOUT_S10       => M1_HREADYOUT_S10,
4291 
            HRDATA_S11          => M1_HRDATA_S11,
4292 
            HREADYOUT_S11       => M1_HREADYOUT_S11,
4293 
            HRDATA_S12          => M1_HRDATA_S12,
4294 
            HREADYOUT_S12       => M1_HREADYOUT_S12,
4295 
            HRDATA_S13          => M1_HRDATA_S13,
4296 
            HREADYOUT_S13       => M1_HREADYOUT_S13,
4297 
            HRDATA_S14          => M1_HRDATA_S14,
4298 
            HREADYOUT_S14       => M1_HREADYOUT_S14,
4299 
            HRDATA_S15          => M1_HRDATA_S15,
4300 
            HREADYOUT_S15       => M1_HREADYOUT_S15,
4301 
            HRDATA_S16          => M1_HRDATA_S16,
4302 
            HREADYOUT_S16       => M1_HREADYOUT_S16
4303 
        );
4304 
 
4305 
 
4306 
    hdl1218 <= (s16m2AddrReady_int & s15m2AddrReady_int & s14m2AddrReady_int & s13m2AddrReady_int & s12m2AddrReady_int & s11m2AddrReady_int & s10m2AddrReady_int & s9m2AddrReady_int & s8m2AddrReady_int & s7m2AddrReady_int & s6m2AddrReady_int & s5m2AddrReady_int & s4m2AddrReady_int & s3m2AddrReady_int & s2m2AddrReady_int & s1m2AddrReady_int & s0m2AddrReady_int);
4307 
    hdl1219 <= (s16m2DataReady_int & s15m2DataReady_int & s14m2DataReady_int & s13m2DataReady_int & s12m2DataReady_int & s11m2DataReady_int & s10m2DataReady_int & s9m2DataReady_int & s8m2DataReady_int & s7m2DataReady_int & s6m2DataReady_int & s5m2DataReady_int & s4m2DataReady_int & s3m2DataReady_int & s2m2DataReady_int & s1m2DataReady_int & s0m2DataReady_int);
4308 
    hdl1220 <= (s16m2HResp_int & s15m2HResp_int & s14m2HResp_int & s13m2HResp_int & s12m2HResp_int & s11m2HResp_int & s10m2HResp_int & s9m2HResp_int & s8m2HResp_int & s7m2HResp_int & s6m2HResp_int & s5m2HResp_int & s4m2HResp_int & s3m2HResp_int & s2m2HResp_int & s1m2HResp_int & s0m2HResp_int);
4309 
    (m2s16AddrSel, m2s15AddrSel, m2s14AddrSel, m2s13AddrSel, m2s12AddrSel, m2s11AddrSel, m2s10AddrSel, m2s9AddrSel, m2s8AddrSel, m2s7AddrSel, m2s6AddrSel, m2s5AddrSel, m2s4AddrSel, m2s3AddrSel, m2s2AddrSel, m2s1AddrSel, m2s0AddrSel) <= hdl1221;
4310 
    (m2s16DataSel, m2s15DataSel, m2s14DataSel, m2s13DataSel, m2s12DataSel, m2s11DataSel, m2s10DataSel, m2s9DataSel, m2s8DataSel, m2s7DataSel, m2s6DataSel, m2s5DataSel, m2s4DataSel, m2s3DataSel, m2s2DataSel, m2s1DataSel, m2s0DataSel) <= hdl1222;
4311 
    masterstage_2 : COREAHBLITE_MASTERSTAGE
4312 
        generic map (
4313 
            MEMSPACE         => MEMSPACE,
4314 
            HADDR_SHG_CFG    => HADDR_SHG_CFG,
4315 
            SC               => SC,
4316 
            M_AHBSLOTENABLE  => M2_AHBSLOTENABLE,
4317 
                        SYNC_RESET       => SYNC_RESET
4318 
        )
4319 
        port map (
4320 
            HCLK                => HCLK,
4321 
            HRESETN             => HRESETN,
4322 
            REMAP               => '0',
4323 
            HADDR               => HADDR_M2,
4324 
            HMASTLOCK           => HMASTLOCK_M2,
4325 
            HSIZE               => HSIZE_M2,
4326 
            HTRANS              => HTRANS_M2,
4327 
            HWRITE              => HWRITE_M2,
4328 
            HRESP               => HRESP_M2_xhdl55,
4329 
            HRDATA              => HRDATA_M2_xhdl34,
4330 
            HREADY_M            => HREADY_M2_pre,
4331 
            SADDRREADY          => hdl1218,
4332 
            SDATAREADY          => hdl1219,
4333 
            SHRESP              => hdl1220,
4334 
            GATEDHADDR          => M2GATEDHADDR,
4335 
            GATEDHMASTLOCK      => M2GATEDHMASTLOCK,
4336 
            GATEDHSIZE          => M2GATEDHSIZE,
4337 
            GATEDHTRANS         => M2GATEDHTRANS,
4338 
            GATEDHWRITE         => M2GATEDHWRITE,
4339 
            SADDRSEL            => hdl1221,
4340 
            SDATASEL            => hdl1222,
4341 
            PREVDATASLAVEREADY  => m2PrevDataSlaveReady,
4342 
            HRDATA_S0           => M2_HRDATA_S0,
4343 
            HREADYOUT_S0        => M2_HREADYOUT_S0,
4344 
            HRDATA_S1           => M2_HRDATA_S1,
4345 
            HREADYOUT_S1        => M2_HREADYOUT_S1,
4346 
            HRDATA_S2           => M2_HRDATA_S2,
4347 
            HREADYOUT_S2        => M2_HREADYOUT_S2,
4348 
            HRDATA_S3           => M2_HRDATA_S3,
4349 
            HREADYOUT_S3        => M2_HREADYOUT_S3,
4350 
            HRDATA_S4           => M2_HRDATA_S4,
4351 
            HREADYOUT_S4        => M2_HREADYOUT_S4,
4352 
            HRDATA_S5           => M2_HRDATA_S5,
4353 
            HREADYOUT_S5        => M2_HREADYOUT_S5,
4354 
            HRDATA_S6           => M2_HRDATA_S6,
4355 
            HREADYOUT_S6        => M2_HREADYOUT_S6,
4356 
            HRDATA_S7           => M2_HRDATA_S7,
4357 
            HREADYOUT_S7        => M2_HREADYOUT_S7,
4358 
            HRDATA_S8           => M2_HRDATA_S8,
4359 
            HREADYOUT_S8        => M2_HREADYOUT_S8,
4360 
            HRDATA_S9           => M2_HRDATA_S9,
4361 
            HREADYOUT_S9        => M2_HREADYOUT_S9,
4362 
            HRDATA_S10          => M2_HRDATA_S10,
4363 
            HREADYOUT_S10       => M2_HREADYOUT_S10,
4364 
            HRDATA_S11          => M2_HRDATA_S11,
4365 
            HREADYOUT_S11       => M2_HREADYOUT_S11,
4366 
            HRDATA_S12          => M2_HRDATA_S12,
4367 
            HREADYOUT_S12       => M2_HREADYOUT_S12,
4368 
            HRDATA_S13          => M2_HRDATA_S13,
4369 
            HREADYOUT_S13       => M2_HREADYOUT_S13,
4370 
            HRDATA_S14          => M2_HRDATA_S14,
4371 
            HREADYOUT_S14       => M2_HREADYOUT_S14,
4372 
            HRDATA_S15          => M2_HRDATA_S15,
4373 
            HREADYOUT_S15       => M2_HREADYOUT_S15,
4374 
            HRDATA_S16          => M2_HRDATA_S16,
4375 
            HREADYOUT_S16       => M2_HREADYOUT_S16
4376 
        );
4377 
 
4378 
 
4379 
    hdl1223 <= (s16m3AddrReady_int & s15m3AddrReady_int & s14m3AddrReady_int & s13m3AddrReady_int & s12m3AddrReady_int & s11m3AddrReady_int & s10m3AddrReady_int & s9m3AddrReady_int & s8m3AddrReady_int & s7m3AddrReady_int & s6m3AddrReady_int & s5m3AddrReady_int & s4m3AddrReady_int & s3m3AddrReady_int & s2m3AddrReady_int & s1m3AddrReady_int & s0m3AddrReady_int);
4380 
    hdl1224 <= (s16m3DataReady_int & s15m3DataReady_int & s14m3DataReady_int & s13m3DataReady_int & s12m3DataReady_int & s11m3DataReady_int & s10m3DataReady_int & s9m3DataReady_int & s8m3DataReady_int & s7m3DataReady_int & s6m3DataReady_int & s5m3DataReady_int & s4m3DataReady_int & s3m3DataReady_int & s2m3DataReady_int & s1m3DataReady_int & s0m3DataReady_int);
4381 
    hdl1225 <= (s16m3HResp_int & s15m3HResp_int & s14m3HResp_int & s13m3HResp_int & s12m3HResp_int & s11m3HResp_int & s10m3HResp_int & s9m3HResp_int & s8m3HResp_int & s7m3HResp_int & s6m3HResp_int & s5m3HResp_int & s4m3HResp_int & s3m3HResp_int & s2m3HResp_int & s1m3HResp_int & s0m3HResp_int);
4382 
    (m3s16AddrSel, m3s15AddrSel, m3s14AddrSel, m3s13AddrSel, m3s12AddrSel, m3s11AddrSel, m3s10AddrSel, m3s9AddrSel, m3s8AddrSel, m3s7AddrSel, m3s6AddrSel, m3s5AddrSel, m3s4AddrSel, m3s3AddrSel, m3s2AddrSel, m3s1AddrSel, m3s0AddrSel) <= hdl1226;
4383 
    (m3s16DataSel, m3s15DataSel, m3s14DataSel, m3s13DataSel, m3s12DataSel, m3s11DataSel, m3s10DataSel, m3s9DataSel, m3s8DataSel, m3s7DataSel, m3s6DataSel, m3s5DataSel, m3s4DataSel, m3s3DataSel, m3s2DataSel, m3s1DataSel, m3s0DataSel) <= hdl1227;
4384 
    masterstage_3 : COREAHBLITE_MASTERSTAGE
4385 
        generic map (
4386 
            MEMSPACE         => MEMSPACE,
4387 
            HADDR_SHG_CFG    => HADDR_SHG_CFG,
4388 
            SC               => SC,
4389 
            M_AHBSLOTENABLE  => M3_AHBSLOTENABLE,
4390 
                        SYNC_RESET       => SYNC_RESET
4391 
        )
4392 
        port map (
4393 
            HCLK                => HCLK,
4394 
            HRESETN             => HRESETN,
4395 
            REMAP               => '0',
4396 
            HADDR               => HADDR_M3,
4397 
            HMASTLOCK           => HMASTLOCK_M3,
4398 
            HSIZE               => HSIZE_M3,
4399 
            HTRANS              => HTRANS_M3,
4400 
            HWRITE              => HWRITE_M3,
4401 
            HRESP               => HRESP_M3_xhdl56,
4402 
            HRDATA              => HRDATA_M3_xhdl35,
4403 
            HREADY_M            => HREADY_M3_pre,
4404 
            SADDRREADY          => hdl1223,
4405 
            SDATAREADY          => hdl1224,
4406 
            SHRESP              => hdl1225,
4407 
            GATEDHADDR          => M3GATEDHADDR,
4408 
            GATEDHMASTLOCK      => M3GATEDHMASTLOCK,
4409 
            GATEDHSIZE          => M3GATEDHSIZE,
4410 
            GATEDHTRANS         => M3GATEDHTRANS,
4411 
            GATEDHWRITE         => M3GATEDHWRITE,
4412 
            SADDRSEL            => hdl1226,
4413 
            SDATASEL            => hdl1227,
4414 
            PREVDATASLAVEREADY  => m3PrevDataSlaveReady,
4415 
            HRDATA_S0           => M3_HRDATA_S0,
4416 
            HREADYOUT_S0        => M3_HREADYOUT_S0,
4417 
            HRDATA_S1           => M3_HRDATA_S1,
4418 
            HREADYOUT_S1        => M3_HREADYOUT_S1,
4419 
            HRDATA_S2           => M3_HRDATA_S2,
4420 
            HREADYOUT_S2        => M3_HREADYOUT_S2,
4421 
            HRDATA_S3           => M3_HRDATA_S3,
4422 
            HREADYOUT_S3        => M3_HREADYOUT_S3,
4423 
            HRDATA_S4           => M3_HRDATA_S4,
4424 
            HREADYOUT_S4        => M3_HREADYOUT_S4,
4425 
            HRDATA_S5           => M3_HRDATA_S5,
4426 
            HREADYOUT_S5        => M3_HREADYOUT_S5,
4427 
            HRDATA_S6           => M3_HRDATA_S6,
4428 
            HREADYOUT_S6        => M3_HREADYOUT_S6,
4429 
            HRDATA_S7           => M3_HRDATA_S7,
4430 
            HREADYOUT_S7        => M3_HREADYOUT_S7,
4431 
            HRDATA_S8           => M3_HRDATA_S8,
4432 
            HREADYOUT_S8        => M3_HREADYOUT_S8,
4433 
            HRDATA_S9           => M3_HRDATA_S9,
4434 
            HREADYOUT_S9        => M3_HREADYOUT_S9,
4435 
            HRDATA_S10          => M3_HRDATA_S10,
4436 
            HREADYOUT_S10       => M3_HREADYOUT_S10,
4437 
            HRDATA_S11          => M3_HRDATA_S11,
4438 
            HREADYOUT_S11       => M3_HREADYOUT_S11,
4439 
            HRDATA_S12          => M3_HRDATA_S12,
4440 
            HREADYOUT_S12       => M3_HREADYOUT_S12,
4441 
            HRDATA_S13          => M3_HRDATA_S13,
4442 
            HREADYOUT_S13       => M3_HREADYOUT_S13,
4443 
            HRDATA_S14          => M3_HRDATA_S14,
4444 
            HREADYOUT_S14       => M3_HREADYOUT_S14,
4445 
            HRDATA_S15          => M3_HRDATA_S15,
4446 
            HREADYOUT_S15       => M3_HREADYOUT_S15,
4447 
            HRDATA_S16          => M3_HRDATA_S16,
4448 
            HREADYOUT_S16       => M3_HREADYOUT_S16
4449 
        );
4450 
 
4451 
 
4452 
    xhdl1228 <= (m3s0AddrSel_int & m2s0AddrSel_int & m1s0AddrSel_int & m0s0AddrSel_int);
4453 
    xhdl1229 <= (m3s0DataSel_int & m2s0DataSel_int & m1s0DataSel_int & m0s0DataSel_int);
4454 
    xhdl1230 <= (m3s0PrevDataSlaveReady & m2s0PrevDataSlaveReady & m1s0PrevDataSlaveReady & m0s0PrevDataSlaveReady);
4455 
    (s0m3AddrReady, s0m2AddrReady, s0m1AddrReady, s0m0AddrReady) <= xhdl1231;
4456 
    (s0m3DataReady, s0m2DataReady, s0m1DataReady, s0m0DataReady) <= xhdl1232;
4457 
    (s0m3HResp, s0m2HResp, s0m1HResp, s0m0HResp) <= xhdl1233;
4458 
    slavestage_0 : COREAHBLITE_SLAVESTAGE
4459 
                generic map(SYNC_RESET => SYNC_RESET)
4460 
        port map (
4461 
            HCLK                 => HCLK,
4462 
            HRESETN              => HRESETN,
4463 
            HREADYOUT            => INT_HREADYOUT_S0,
4464 
            HRESP                => INT_HRESP_S0,
4465 
            HSEL                 => HSEL_S0_xhdl57,
4466 
            HADDR                => HADDR_S0_xhdl0,
4467 
            HSIZE                => HSIZE_S0_xhdl74,
4468 
            HTRANS               => HTRANS_S0_xhdl91,
4469 
            HWRITE               => HWRITE_S0_xhdl125,
4470 
            HWDATA               => HWDATA_S0_xhdl108,
4471 
            HREADY_S             => HREADY_S0_xhdl38,
4472 
            HMASTLOCK            => HMASTLOCK_S0_xhdl17,
4473 
            MADDRSEL             => xhdl1228,
4474 
            MDATASEL             => xhdl1229,
4475 
            MPREVDATASLAVEREADY  => xhdl1230,
4476 
            MADDRREADY           => xhdl1231,
4477 
            MDATAREADY           => xhdl1232,
4478 
            MHRESP               => xhdl1233,
4479 
            M0GATEDHADDR         => m0s0GatedHADDR,
4480 
            M0GATEDHMASTLOCK     => m0s0GatedHMASTLOCK,
4481 
            M0GATEDHSIZE         => m0s0GatedHSIZE,
4482 
            M0GATEDHTRANS        => m0s0GatedHTRANS,
4483 
            M0GATEDHWRITE        => m0s0GatedHWRITE,
4484 
            M1GATEDHADDR         => m1s0GatedHADDR,
4485 
            M1GATEDHMASTLOCK     => m1s0GatedHMASTLOCK,
4486 
            M1GATEDHSIZE         => m1s0GatedHSIZE,
4487 
            M1GATEDHTRANS        => m1s0GatedHTRANS,
4488 
            M1GATEDHWRITE        => m1s0GatedHWRITE,
4489 
            M2GATEDHADDR         => m2s0GatedHADDR,
4490 
            M2GATEDHMASTLOCK     => m2s0GatedHMASTLOCK,
4491 
            M2GATEDHSIZE         => m2s0GatedHSIZE,
4492 
            M2GATEDHTRANS        => m2s0GatedHTRANS,
4493 
            M2GATEDHWRITE        => m2s0GatedHWRITE,
4494 
            M3GATEDHADDR         => m3s0GatedHADDR,
4495 
            M3GATEDHMASTLOCK     => m3s0GatedHMASTLOCK,
4496 
            M3GATEDHSIZE         => m3s0GatedHSIZE,
4497 
            M3GATEDHTRANS        => m3s0GatedHTRANS,
4498 
            M3GATEDHWRITE        => m3s0GatedHWRITE,
4499 
            HWDATA_M0            => HWDATA_M0S0,
4500 
            HWDATA_M1            => HWDATA_M1S0,
4501 
            HWDATA_M2            => HWDATA_M2S0,
4502 
            HWDATA_M3            => HWDATA_M3S0
4503 
        );
4504 
 
4505 
 
4506 
    xhdl1234 <= (m3s1AddrSel_int & m2s1AddrSel_int & m1s1AddrSel_int & m0s1AddrSel_int);
4507 
    xhdl1235 <= (m3s1DataSel_int & m2s1DataSel_int & m1s1DataSel_int & m0s1DataSel_int);
4508 
    xhdl1236 <= (m3s1PrevDataSlaveReady & m2s1PrevDataSlaveReady & m1s1PrevDataSlaveReady & m0s1PrevDataSlaveReady);
4509 
    (s1m3AddrReady, s1m2AddrReady, s1m1AddrReady, s1m0AddrReady) <= xhdl1237;
4510 
    (s1m3DataReady, s1m2DataReady, s1m1DataReady, s1m0DataReady) <= xhdl1238;
4511 
    (s1m3HResp, s1m2HResp, s1m1HResp, s1m0HResp) <= xhdl1239;
4512 
    slavestage_1 : COREAHBLITE_SLAVESTAGE
4513 
                generic map(SYNC_RESET => SYNC_RESET)
4514 
        port map (
4515 
            HCLK                 => HCLK,
4516 
            HRESETN              => HRESETN,
4517 
            HREADYOUT            => INT_HREADYOUT_S1,
4518 
            HRESP                => INT_HRESP_S1,
4519 
            HSEL                 => HSEL_S1_xhdl58,
4520 
            HADDR                => HADDR_S1_xhdl1,
4521 
            HSIZE                => HSIZE_S1_xhdl75,
4522 
            HTRANS               => HTRANS_S1_xhdl92,
4523 
            HWRITE               => HWRITE_S1_xhdl126,
4524 
            HWDATA               => HWDATA_S1_xhdl109,
4525 
            HREADY_S             => HREADY_S1_xhdl39,
4526 
            HMASTLOCK            => HMASTLOCK_S1_xhdl18,
4527 
            MADDRSEL             => xhdl1234,
4528 
            MDATASEL             => xhdl1235,
4529 
            MPREVDATASLAVEREADY  => xhdl1236,
4530 
            MADDRREADY           => xhdl1237,
4531 
            MDATAREADY           => xhdl1238,
4532 
            MHRESP               => xhdl1239,
4533 
            M0GATEDHADDR         => m0s1GatedHADDR,
4534 
            M0GATEDHMASTLOCK     => m0s1GatedHMASTLOCK,
4535 
            M0GATEDHSIZE         => m0s1GatedHSIZE,
4536 
            M0GATEDHTRANS        => m0s1GatedHTRANS,
4537 
            M0GATEDHWRITE        => m0s1GatedHWRITE,
4538 
            M1GATEDHADDR         => m1s1GatedHADDR,
4539 
            M1GATEDHMASTLOCK     => m1s1GatedHMASTLOCK,
4540 
            M1GATEDHSIZE         => m1s1GatedHSIZE,
4541 
            M1GATEDHTRANS        => m1s1GatedHTRANS,
4542 
            M1GATEDHWRITE        => m1s1GatedHWRITE,
4543 
            M2GATEDHADDR         => m2s1GatedHADDR,
4544 
            M2GATEDHMASTLOCK     => m2s1GatedHMASTLOCK,
4545 
            M2GATEDHSIZE         => m2s1GatedHSIZE,
4546 
            M2GATEDHTRANS        => m2s1GatedHTRANS,
4547 
            M2GATEDHWRITE        => m2s1GatedHWRITE,
4548 
            M3GATEDHADDR         => m3s1GatedHADDR,
4549 
            M3GATEDHMASTLOCK     => m3s1GatedHMASTLOCK,
4550 
            M3GATEDHSIZE         => m3s1GatedHSIZE,
4551 
            M3GATEDHTRANS        => m3s1GatedHTRANS,
4552 
            M3GATEDHWRITE        => m3s1GatedHWRITE,
4553 
            HWDATA_M0            => HWDATA_M0S1,
4554 
            HWDATA_M1            => HWDATA_M1S1,
4555 
            HWDATA_M2            => HWDATA_M2S1,
4556 
            HWDATA_M3            => HWDATA_M3S1
4557 
        );
4558 
 
4559 
 
4560 
    xhdl1240 <= (m3s2AddrSel_int & m2s2AddrSel_int & m1s2AddrSel_int & m0s2AddrSel_int);
4561 
    xhdl1241 <= (m3s2DataSel_int & m2s2DataSel_int & m1s2DataSel_int & m0s2DataSel_int);
4562 
    xhdl1242 <= (m3s2PrevDataSlaveReady & m2s2PrevDataSlaveReady & m1s2PrevDataSlaveReady & m0s2PrevDataSlaveReady);
4563 
    (s2m3AddrReady, s2m2AddrReady, s2m1AddrReady, s2m0AddrReady) <= xhdl1243;
4564 
    (s2m3DataReady, s2m2DataReady, s2m1DataReady, s2m0DataReady) <= xhdl1244;
4565 
    (s2m3HResp, s2m2HResp, s2m1HResp, s2m0HResp) <= xhdl1245;
4566 
    slavestage_2 : COREAHBLITE_SLAVESTAGE
4567 
                generic map(SYNC_RESET => SYNC_RESET)
4568 
        port map (
4569 
            HCLK                 => HCLK,
4570 
            HRESETN              => HRESETN,
4571 
            HREADYOUT            => INT_HREADYOUT_S2,
4572 
            HRESP                => INT_HRESP_S2,
4573 
            HSEL                 => HSEL_S2_xhdl65,
4574 
            HADDR                => HADDR_S2_xhdl8,
4575 
            HSIZE                => HSIZE_S2_xhdl82,
4576 
            HTRANS               => HTRANS_S2_xhdl99,
4577 
            HWRITE               => HWRITE_S2_xhdl133,
4578 
            HWDATA               => HWDATA_S2_xhdl116,
4579 
            HREADY_S             => HREADY_S2_xhdl46,
4580 
            HMASTLOCK            => HMASTLOCK_S2_xhdl25,
4581 
            MADDRSEL             => xhdl1240,
4582 
            MDATASEL             => xhdl1241,
4583 
            MPREVDATASLAVEREADY  => xhdl1242,
4584 
            MADDRREADY           => xhdl1243,
4585 
            MDATAREADY           => xhdl1244,
4586 
            MHRESP               => xhdl1245,
4587 
            M0GATEDHADDR         => m0s2GatedHADDR,
4588 
            M0GATEDHMASTLOCK     => m0s2GatedHMASTLOCK,
4589 
            M0GATEDHSIZE         => m0s2GatedHSIZE,
4590 
            M0GATEDHTRANS        => m0s2GatedHTRANS,
4591 
            M0GATEDHWRITE        => m0s2GatedHWRITE,
4592 
            M1GATEDHADDR         => m1s2GatedHADDR,
4593 
            M1GATEDHMASTLOCK     => m1s2GatedHMASTLOCK,
4594 
            M1GATEDHSIZE         => m1s2GatedHSIZE,
4595 
            M1GATEDHTRANS        => m1s2GatedHTRANS,
4596 
            M1GATEDHWRITE        => m1s2GatedHWRITE,
4597 
            M2GATEDHADDR         => m2s2GatedHADDR,
4598 
            M2GATEDHMASTLOCK     => m2s2GatedHMASTLOCK,
4599 
            M2GATEDHSIZE         => m2s2GatedHSIZE,
4600 
            M2GATEDHTRANS        => m2s2GatedHTRANS,
4601 
            M2GATEDHWRITE        => m2s2GatedHWRITE,
4602 
            M3GATEDHADDR         => m3s2GatedHADDR,
4603 
            M3GATEDHMASTLOCK     => m3s2GatedHMASTLOCK,
4604 
            M3GATEDHSIZE         => m3s2GatedHSIZE,
4605 
            M3GATEDHTRANS        => m3s2GatedHTRANS,
4606 
            M3GATEDHWRITE        => m3s2GatedHWRITE,
4607 
            HWDATA_M0            => HWDATA_M0S2,
4608 
            HWDATA_M1            => HWDATA_M1S2,
4609 
            HWDATA_M2            => HWDATA_M2S2,
4610 
            HWDATA_M3            => HWDATA_M3S2
4611 
        );
4612 
 
4613 
 
4614 
    xhdl1246 <= (m3s3AddrSel_int & m2s3AddrSel_int & m1s3AddrSel_int & m0s3AddrSel_int);
4615 
    xhdl1247 <= (m3s3DataSel_int & m2s3DataSel_int & m1s3DataSel_int & m0s3DataSel_int);
4616 
    xhdl1248 <= (m3s3PrevDataSlaveReady & m2s3PrevDataSlaveReady & m1s3PrevDataSlaveReady & m0s3PrevDataSlaveReady);
4617 
    (s3m3AddrReady, s3m2AddrReady, s3m1AddrReady, s3m0AddrReady) <= xhdl1249;
4618 
    (s3m3DataReady, s3m2DataReady, s3m1DataReady, s3m0DataReady) <= xhdl1250;
4619 
    (s3m3HResp, s3m2HResp, s3m1HResp, s3m0HResp) <= xhdl1251;
4620 
    slavestage_3 : COREAHBLITE_SLAVESTAGE
4621 
                generic map(SYNC_RESET => SYNC_RESET)
4622 
        port map (
4623 
            HCLK                 => HCLK,
4624 
            HRESETN              => HRESETN,
4625 
            HREADYOUT            => INT_HREADYOUT_S3,
4626 
            HRESP                => INT_HRESP_S3,
4627 
            HSEL                 => HSEL_S3_xhdl66,
4628 
            HADDR                => HADDR_S3_xhdl9,
4629 
            HSIZE                => HSIZE_S3_xhdl83,
4630 
            HTRANS               => HTRANS_S3_xhdl100,
4631 
            HWRITE               => HWRITE_S3_xhdl134,
4632 
            HWDATA               => HWDATA_S3_xhdl117,
4633 
            HREADY_S             => HREADY_S3_xhdl47,
4634 
            HMASTLOCK            => HMASTLOCK_S3_xhdl26,
4635 
            MADDRSEL             => xhdl1246,
4636 
            MDATASEL             => xhdl1247,
4637 
            MPREVDATASLAVEREADY  => xhdl1248,
4638 
            MADDRREADY           => xhdl1249,
4639 
            MDATAREADY           => xhdl1250,
4640 
            MHRESP               => xhdl1251,
4641 
            M0GATEDHADDR         => m0s3GatedHADDR,
4642 
            M0GATEDHMASTLOCK     => m0s3GatedHMASTLOCK,
4643 
            M0GATEDHSIZE         => m0s3GatedHSIZE,
4644 
            M0GATEDHTRANS        => m0s3GatedHTRANS,
4645 
            M0GATEDHWRITE        => m0s3GatedHWRITE,
4646 
            M1GATEDHADDR         => m1s3GatedHADDR,
4647 
            M1GATEDHMASTLOCK     => m1s3GatedHMASTLOCK,
4648 
            M1GATEDHSIZE         => m1s3GatedHSIZE,
4649 
            M1GATEDHTRANS        => m1s3GatedHTRANS,
4650 
            M1GATEDHWRITE        => m1s3GatedHWRITE,
4651 
            M2GATEDHADDR         => m2s3GatedHADDR,
4652 
            M2GATEDHMASTLOCK     => m2s3GatedHMASTLOCK,
4653 
            M2GATEDHSIZE         => m2s3GatedHSIZE,
4654 
            M2GATEDHTRANS        => m2s3GatedHTRANS,
4655 
            M2GATEDHWRITE        => m2s3GatedHWRITE,
4656 
            M3GATEDHADDR         => m3s3GatedHADDR,
4657 
            M3GATEDHMASTLOCK     => m3s3GatedHMASTLOCK,
4658 
            M3GATEDHSIZE         => m3s3GatedHSIZE,
4659 
            M3GATEDHTRANS        => m3s3GatedHTRANS,
4660 
            M3GATEDHWRITE        => m3s3GatedHWRITE,
4661 
            HWDATA_M0            => HWDATA_M0S3,
4662 
            HWDATA_M1            => HWDATA_M1S3,
4663 
            HWDATA_M2            => HWDATA_M2S3,
4664 
            HWDATA_M3            => HWDATA_M3S3
4665 
        );
4666 
 
4667 
 
4668 
    xhdl1252 <= (m3s4AddrSel_int & m2s4AddrSel_int & m1s4AddrSel_int & m0s4AddrSel_int);
4669 
    xhdl1253 <= (m3s4DataSel_int & m2s4DataSel_int & m1s4DataSel_int & m0s4DataSel_int);
4670 
    xhdl1254 <= (m3s4PrevDataSlaveReady & m2s4PrevDataSlaveReady & m1s4PrevDataSlaveReady & m0s4PrevDataSlaveReady);
4671 
    (s4m3AddrReady, s4m2AddrReady, s4m1AddrReady, s4m0AddrReady) <= xhdl1255;
4672 
    (s4m3DataReady, s4m2DataReady, s4m1DataReady, s4m0DataReady) <= xhdl1256;
4673 
    (s4m3HResp, s4m2HResp, s4m1HResp, s4m0HResp) <= xhdl1257;
4674 
    slavestage_4 : COREAHBLITE_SLAVESTAGE
4675 
                generic map(SYNC_RESET => SYNC_RESET)
4676 
        port map (
4677 
            HCLK                 => HCLK,
4678 
            HRESETN              => HRESETN,
4679 
            HREADYOUT            => INT_HREADYOUT_S4,
4680 
            HRESP                => INT_HRESP_S4,
4681 
            HSEL                 => HSEL_S4_xhdl67,
4682 
            HADDR                => HADDR_S4_xhdl10,
4683 
            HSIZE                => HSIZE_S4_xhdl84,
4684 
            HTRANS               => HTRANS_S4_xhdl101,
4685 
            HWRITE               => HWRITE_S4_xhdl135,
4686 
            HWDATA               => HWDATA_S4_xhdl118,
4687 
            HREADY_S             => HREADY_S4_xhdl48,
4688 
            HMASTLOCK            => HMASTLOCK_S4_xhdl27,
4689 
            MADDRSEL             => xhdl1252,
4690 
            MDATASEL             => xhdl1253,
4691 
            MPREVDATASLAVEREADY  => xhdl1254,
4692 
            MADDRREADY           => xhdl1255,
4693 
            MDATAREADY           => xhdl1256,
4694 
            MHRESP               => xhdl1257,
4695 
            M0GATEDHADDR         => m0s4GatedHADDR,
4696 
            M0GATEDHMASTLOCK     => m0s4GatedHMASTLOCK,
4697 
            M0GATEDHSIZE         => m0s4GatedHSIZE,
4698 
            M0GATEDHTRANS        => m0s4GatedHTRANS,
4699 
            M0GATEDHWRITE        => m0s4GatedHWRITE,
4700 
            M1GATEDHADDR         => m1s4GatedHADDR,
4701 
            M1GATEDHMASTLOCK     => m1s4GatedHMASTLOCK,
4702 
            M1GATEDHSIZE         => m1s4GatedHSIZE,
4703 
            M1GATEDHTRANS        => m1s4GatedHTRANS,
4704 
            M1GATEDHWRITE        => m1s4GatedHWRITE,
4705 
            M2GATEDHADDR         => m2s4GatedHADDR,
4706 
            M2GATEDHMASTLOCK     => m2s4GatedHMASTLOCK,
4707 
            M2GATEDHSIZE         => m2s4GatedHSIZE,
4708 
            M2GATEDHTRANS        => m2s4GatedHTRANS,
4709 
            M2GATEDHWRITE        => m2s4GatedHWRITE,
4710 
            M3GATEDHADDR         => m3s4GatedHADDR,
4711 
            M3GATEDHMASTLOCK     => m3s4GatedHMASTLOCK,
4712 
            M3GATEDHSIZE         => m3s4GatedHSIZE,
4713 
            M3GATEDHTRANS        => m3s4GatedHTRANS,
4714 
            M3GATEDHWRITE        => m3s4GatedHWRITE,
4715 
            HWDATA_M0            => HWDATA_M0S4,
4716 
            HWDATA_M1            => HWDATA_M1S4,
4717 
            HWDATA_M2            => HWDATA_M2S4,
4718 
            HWDATA_M3            => HWDATA_M3S4
4719 
        );
4720 
 
4721 
 
4722 
    xhdl1258 <= (m3s5AddrSel_int & m2s5AddrSel_int & m1s5AddrSel_int & m0s5AddrSel_int);
4723 
    xhdl1259 <= (m3s5DataSel_int & m2s5DataSel_int & m1s5DataSel_int & m0s5DataSel_int);
4724 
    xhdl1260 <= (m3s5PrevDataSlaveReady & m2s5PrevDataSlaveReady & m1s5PrevDataSlaveReady & m0s5PrevDataSlaveReady);
4725 
    (s5m3AddrReady, s5m2AddrReady, s5m1AddrReady, s5m0AddrReady) <= xhdl1261;
4726 
    (s5m3DataReady, s5m2DataReady, s5m1DataReady, s5m0DataReady) <= xhdl1262;
4727 
    (s5m3HResp, s5m2HResp, s5m1HResp, s5m0HResp) <= xhdl1263;
4728 
    slavestage_5 : COREAHBLITE_SLAVESTAGE
4729 
                generic map(SYNC_RESET => SYNC_RESET)
4730 
        port map (
4731 
            HCLK                 => HCLK,
4732 
            HRESETN              => HRESETN,
4733 
            HREADYOUT            => INT_HREADYOUT_S5,
4734 
            HRESP                => INT_HRESP_S5,
4735 
            HSEL                 => HSEL_S5_xhdl68,
4736 
            HADDR                => HADDR_S5_xhdl11,
4737 
            HSIZE                => HSIZE_S5_xhdl85,
4738 
            HTRANS               => HTRANS_S5_xhdl102,
4739 
            HWRITE               => HWRITE_S5_xhdl136,
4740 
            HWDATA               => HWDATA_S5_xhdl119,
4741 
            HREADY_S             => HREADY_S5_xhdl49,
4742 
            HMASTLOCK            => HMASTLOCK_S5_xhdl28,
4743 
            MADDRSEL             => xhdl1258,
4744 
            MDATASEL             => xhdl1259,
4745 
            MPREVDATASLAVEREADY  => xhdl1260,
4746 
            MADDRREADY           => xhdl1261,
4747 
            MDATAREADY           => xhdl1262,
4748 
            MHRESP               => xhdl1263,
4749 
            M0GATEDHADDR         => m0s5GatedHADDR,
4750 
            M0GATEDHMASTLOCK     => m0s5GatedHMASTLOCK,
4751 
            M0GATEDHSIZE         => m0s5GatedHSIZE,
4752 
            M0GATEDHTRANS        => m0s5GatedHTRANS,
4753 
            M0GATEDHWRITE        => m0s5GatedHWRITE,
4754 
            M1GATEDHADDR         => m1s5GatedHADDR,
4755 
            M1GATEDHMASTLOCK     => m1s5GatedHMASTLOCK,
4756 
            M1GATEDHSIZE         => m1s5GatedHSIZE,
4757 
            M1GATEDHTRANS        => m1s5GatedHTRANS,
4758 
            M1GATEDHWRITE        => m1s5GatedHWRITE,
4759 
            M2GATEDHADDR         => m2s5GatedHADDR,
4760 
            M2GATEDHMASTLOCK     => m2s5GatedHMASTLOCK,
4761 
            M2GATEDHSIZE         => m2s5GatedHSIZE,
4762 
            M2GATEDHTRANS        => m2s5GatedHTRANS,
4763 
            M2GATEDHWRITE        => m2s5GatedHWRITE,
4764 
            M3GATEDHADDR         => m3s5GatedHADDR,
4765 
            M3GATEDHMASTLOCK     => m3s5GatedHMASTLOCK,
4766 
            M3GATEDHSIZE         => m3s5GatedHSIZE,
4767 
            M3GATEDHTRANS        => m3s5GatedHTRANS,
4768 
            M3GATEDHWRITE        => m3s5GatedHWRITE,
4769 
            HWDATA_M0            => HWDATA_M0S5,
4770 
            HWDATA_M1            => HWDATA_M1S5,
4771 
            HWDATA_M2            => HWDATA_M2S5,
4772 
            HWDATA_M3            => HWDATA_M3S5
4773 
        );
4774 
 
4775 
 
4776 
    xhdl1264 <= (m3s6AddrSel_int & m2s6AddrSel_int & m1s6AddrSel_int & m0s6AddrSel_int);
4777 
    xhdl1265 <= (m3s6DataSel_int & m2s6DataSel_int & m1s6DataSel_int & m0s6DataSel_int);
4778 
    xhdl1266 <= (m3s6PrevDataSlaveReady & m2s6PrevDataSlaveReady & m1s6PrevDataSlaveReady & m0s6PrevDataSlaveReady);
4779 
    (s6m3AddrReady, s6m2AddrReady, s6m1AddrReady, s6m0AddrReady) <= xhdl1267;
4780 
    (s6m3DataReady, s6m2DataReady, s6m1DataReady, s6m0DataReady) <= xhdl1268;
4781 
    (s6m3HResp, s6m2HResp, s6m1HResp, s6m0HResp) <= xhdl1269;
4782 
    slavestage_6 : COREAHBLITE_SLAVESTAGE
4783 
                generic map(SYNC_RESET => SYNC_RESET)
4784 
        port map (
4785 
            HCLK                 => HCLK,
4786 
            HRESETN              => HRESETN,
4787 
            HREADYOUT            => INT_HREADYOUT_S6,
4788 
            HRESP                => INT_HRESP_S6,
4789 
            HSEL                 => HSEL_S6_xhdl69,
4790 
            HADDR                => HADDR_S6_xhdl12,
4791 
            HSIZE                => HSIZE_S6_xhdl86,
4792 
            HTRANS               => HTRANS_S6_xhdl103,
4793 
            HWRITE               => HWRITE_S6_xhdl137,
4794 
            HWDATA               => HWDATA_S6_xhdl120,
4795 
            HREADY_S             => HREADY_S6_xhdl50,
4796 
            HMASTLOCK            => HMASTLOCK_S6_xhdl29,
4797 
            MADDRSEL             => xhdl1264,
4798 
            MDATASEL             => xhdl1265,
4799 
            MPREVDATASLAVEREADY  => xhdl1266,
4800 
            MADDRREADY           => xhdl1267,
4801 
            MDATAREADY           => xhdl1268,
4802 
            MHRESP               => xhdl1269,
4803 
            M0GATEDHADDR         => m0s6GatedHADDR,
4804 
            M0GATEDHMASTLOCK     => m0s6GatedHMASTLOCK,
4805 
            M0GATEDHSIZE         => m0s6GatedHSIZE,
4806 
            M0GATEDHTRANS        => m0s6GatedHTRANS,
4807 
            M0GATEDHWRITE        => m0s6GatedHWRITE,
4808 
            M1GATEDHADDR         => m1s6GatedHADDR,
4809 
            M1GATEDHMASTLOCK     => m1s6GatedHMASTLOCK,
4810 
            M1GATEDHSIZE         => m1s6GatedHSIZE,
4811 
            M1GATEDHTRANS        => m1s6GatedHTRANS,
4812 
            M1GATEDHWRITE        => m1s6GatedHWRITE,
4813 
            M2GATEDHADDR         => m2s6GatedHADDR,
4814 
            M2GATEDHMASTLOCK     => m2s6GatedHMASTLOCK,
4815 
            M2GATEDHSIZE         => m2s6GatedHSIZE,
4816 
            M2GATEDHTRANS        => m2s6GatedHTRANS,
4817 
            M2GATEDHWRITE        => m2s6GatedHWRITE,
4818 
            M3GATEDHADDR         => m3s6GatedHADDR,
4819 
            M3GATEDHMASTLOCK     => m3s6GatedHMASTLOCK,
4820 
            M3GATEDHSIZE         => m3s6GatedHSIZE,
4821 
            M3GATEDHTRANS        => m3s6GatedHTRANS,
4822 
            M3GATEDHWRITE        => m3s6GatedHWRITE,
4823 
            HWDATA_M0            => HWDATA_M0S6,
4824 
            HWDATA_M1            => HWDATA_M1S6,
4825 
            HWDATA_M2            => HWDATA_M2S6,
4826 
            HWDATA_M3            => HWDATA_M3S6
4827 
        );
4828 
 
4829 
 
4830 
    xhdl1270 <= (m3s7AddrSel_int & m2s7AddrSel_int & m1s7AddrSel_int & m0s7AddrSel_int);
4831 
    xhdl1271 <= (m3s7DataSel_int & m2s7DataSel_int & m1s7DataSel_int & m0s7DataSel_int);
4832 
    xhdl1272 <= (m3s7PrevDataSlaveReady & m2s7PrevDataSlaveReady & m1s7PrevDataSlaveReady & m0s7PrevDataSlaveReady);
4833 
    (s7m3AddrReady, s7m2AddrReady, s7m1AddrReady, s7m0AddrReady) <= xhdl1273;
4834 
    (s7m3DataReady, s7m2DataReady, s7m1DataReady, s7m0DataReady) <= xhdl1274;
4835 
    (s7m3HResp, s7m2HResp, s7m1HResp, s7m0HResp) <= xhdl1275;
4836 
    slavestage_7 : COREAHBLITE_SLAVESTAGE
4837 
                generic map(SYNC_RESET => SYNC_RESET)
4838 
        port map (
4839 
            HCLK                 => HCLK,
4840 
            HRESETN              => HRESETN,
4841 
            HREADYOUT            => INT_HREADYOUT_S7,
4842 
            HRESP                => INT_HRESP_S7,
4843 
            HSEL                 => HSEL_S7_xhdl70,
4844 
            HADDR                => HADDR_S7_xhdl13,
4845 
            HSIZE                => HSIZE_S7_xhdl87,
4846 
            HTRANS               => HTRANS_S7_xhdl104,
4847 
            HWRITE               => HWRITE_S7_xhdl138,
4848 
            HWDATA               => HWDATA_S7_xhdl121,
4849 
            HREADY_S             => HREADY_S7_xhdl51,
4850 
            HMASTLOCK            => HMASTLOCK_S7_xhdl30,
4851 
            MADDRSEL             => xhdl1270,
4852 
            MDATASEL             => xhdl1271,
4853 
            MPREVDATASLAVEREADY  => xhdl1272,
4854 
            MADDRREADY           => xhdl1273,
4855 
            MDATAREADY           => xhdl1274,
4856 
            MHRESP               => xhdl1275,
4857 
            M0GATEDHADDR         => m0s7GatedHADDR,
4858 
            M0GATEDHMASTLOCK     => m0s7GatedHMASTLOCK,
4859 
            M0GATEDHSIZE         => m0s7GatedHSIZE,
4860 
            M0GATEDHTRANS        => m0s7GatedHTRANS,
4861 
            M0GATEDHWRITE        => m0s7GatedHWRITE,
4862 
            M1GATEDHADDR         => m1s7GatedHADDR,
4863 
            M1GATEDHMASTLOCK     => m1s7GatedHMASTLOCK,
4864 
            M1GATEDHSIZE         => m1s7GatedHSIZE,
4865 
            M1GATEDHTRANS        => m1s7GatedHTRANS,
4866 
            M1GATEDHWRITE        => m1s7GatedHWRITE,
4867 
            M2GATEDHADDR         => m2s7GatedHADDR,
4868 
            M2GATEDHMASTLOCK     => m2s7GatedHMASTLOCK,
4869 
            M2GATEDHSIZE         => m2s7GatedHSIZE,
4870 
            M2GATEDHTRANS        => m2s7GatedHTRANS,
4871 
            M2GATEDHWRITE        => m2s7GatedHWRITE,
4872 
            M3GATEDHADDR         => m3s7GatedHADDR,
4873 
            M3GATEDHMASTLOCK     => m3s7GatedHMASTLOCK,
4874 
            M3GATEDHSIZE         => m3s7GatedHSIZE,
4875 
            M3GATEDHTRANS        => m3s7GatedHTRANS,
4876 
            M3GATEDHWRITE        => m3s7GatedHWRITE,
4877 
            HWDATA_M0            => HWDATA_M0S7,
4878 
            HWDATA_M1            => HWDATA_M1S7,
4879 
            HWDATA_M2            => HWDATA_M2S7,
4880 
            HWDATA_M3            => HWDATA_M3S7
4881 
        );
4882 
 
4883 
 
4884 
    xhdl1276 <= (m3s8AddrSel_int & m2s8AddrSel_int & m1s8AddrSel_int & m0s8AddrSel_int);
4885 
    xhdl1277 <= (m3s8DataSel_int & m2s8DataSel_int & m1s8DataSel_int & m0s8DataSel_int);
4886 
    xhdl1278 <= (m3s8PrevDataSlaveReady & m2s8PrevDataSlaveReady & m1s8PrevDataSlaveReady & m0s8PrevDataSlaveReady);
4887 
    (s8m3AddrReady, s8m2AddrReady, s8m1AddrReady, s8m0AddrReady) <= xhdl1279;
4888 
    (s8m3DataReady, s8m2DataReady, s8m1DataReady, s8m0DataReady) <= xhdl1280;
4889 
    (s8m3HResp, s8m2HResp, s8m1HResp, s8m0HResp) <= xhdl1281;
4890 
    slavestage_8 : COREAHBLITE_SLAVESTAGE
4891 
                generic map(SYNC_RESET => SYNC_RESET)
4892 
        port map (
4893 
            HCLK                 => HCLK,
4894 
            HRESETN              => HRESETN,
4895 
            HREADYOUT            => INT_HREADYOUT_S8,
4896 
            HRESP                => INT_HRESP_S8,
4897 
            HSEL                 => HSEL_S8_xhdl71,
4898 
            HADDR                => HADDR_S8_xhdl14,
4899 
            HSIZE                => HSIZE_S8_xhdl88,
4900 
            HTRANS               => HTRANS_S8_xhdl105,
4901 
            HWRITE               => HWRITE_S8_xhdl139,
4902 
            HWDATA               => HWDATA_S8_xhdl122,
4903 
            HREADY_S             => HREADY_S8_xhdl52,
4904 
            HMASTLOCK            => HMASTLOCK_S8_xhdl31,
4905 
            MADDRSEL             => xhdl1276,
4906 
            MDATASEL             => xhdl1277,
4907 
            MPREVDATASLAVEREADY  => xhdl1278,
4908 
            MADDRREADY           => xhdl1279,
4909 
            MDATAREADY           => xhdl1280,
4910 
            MHRESP               => xhdl1281,
4911 
            M0GATEDHADDR         => m0s8GatedHADDR,
4912 
            M0GATEDHMASTLOCK     => m0s8GatedHMASTLOCK,
4913 
            M0GATEDHSIZE         => m0s8GatedHSIZE,
4914 
            M0GATEDHTRANS        => m0s8GatedHTRANS,
4915 
            M0GATEDHWRITE        => m0s8GatedHWRITE,
4916 
            M1GATEDHADDR         => m1s8GatedHADDR,
4917 
            M1GATEDHMASTLOCK     => m1s8GatedHMASTLOCK,
4918 
            M1GATEDHSIZE         => m1s8GatedHSIZE,
4919 
            M1GATEDHTRANS        => m1s8GatedHTRANS,
4920 
            M1GATEDHWRITE        => m1s8GatedHWRITE,
4921 
            M2GATEDHADDR         => m2s8GatedHADDR,
4922 
            M2GATEDHMASTLOCK     => m2s8GatedHMASTLOCK,
4923 
            M2GATEDHSIZE         => m2s8GatedHSIZE,
4924 
            M2GATEDHTRANS        => m2s8GatedHTRANS,
4925 
            M2GATEDHWRITE        => m2s8GatedHWRITE,
4926 
            M3GATEDHADDR         => m3s8GatedHADDR,
4927 
            M3GATEDHMASTLOCK     => m3s8GatedHMASTLOCK,
4928 
            M3GATEDHSIZE         => m3s8GatedHSIZE,
4929 
            M3GATEDHTRANS        => m3s8GatedHTRANS,
4930 
            M3GATEDHWRITE        => m3s8GatedHWRITE,
4931 
            HWDATA_M0            => HWDATA_M0S8,
4932 
            HWDATA_M1            => HWDATA_M1S8,
4933 
            HWDATA_M2            => HWDATA_M2S8,
4934 
            HWDATA_M3            => HWDATA_M3S8
4935 
        );
4936 
 
4937 
 
4938 
    xhdl1282 <= (m3s9AddrSel_int & m2s9AddrSel_int & m1s9AddrSel_int & m0s9AddrSel_int);
4939 
    xhdl1283 <= (m3s9DataSel_int & m2s9DataSel_int & m1s9DataSel_int & m0s9DataSel_int);
4940 
    xhdl1284 <= (m3s9PrevDataSlaveReady & m2s9PrevDataSlaveReady & m1s9PrevDataSlaveReady & m0s9PrevDataSlaveReady);
4941 
    (s9m3AddrReady, s9m2AddrReady, s9m1AddrReady, s9m0AddrReady) <= xhdl1285;
4942 
    (s9m3DataReady, s9m2DataReady, s9m1DataReady, s9m0DataReady) <= xhdl1286;
4943 
    (s9m3HResp, s9m2HResp, s9m1HResp, s9m0HResp) <= xhdl1287;
4944 
    slavestage_9 : COREAHBLITE_SLAVESTAGE
4945 
                generic map(SYNC_RESET => SYNC_RESET)
4946 
        port map (
4947 
            HCLK                 => HCLK,
4948 
            HRESETN              => HRESETN,
4949 
            HREADYOUT            => INT_HREADYOUT_S9,
4950 
            HRESP                => INT_HRESP_S9,
4951 
            HSEL                 => HSEL_S9_xhdl72,
4952 
            HADDR                => HADDR_S9_xhdl15,
4953 
            HSIZE                => HSIZE_S9_xhdl89,
4954 
            HTRANS               => HTRANS_S9_xhdl106,
4955 
            HWRITE               => HWRITE_S9_xhdl140,
4956 
            HWDATA               => HWDATA_S9_xhdl123,
4957 
            HREADY_S             => HREADY_S9_xhdl53,
4958 
            HMASTLOCK            => HMASTLOCK_S9_xhdl32,
4959 
            MADDRSEL             => xhdl1282,
4960 
            MDATASEL             => xhdl1283,
4961 
            MPREVDATASLAVEREADY  => xhdl1284,
4962 
            MADDRREADY           => xhdl1285,
4963 
            MDATAREADY           => xhdl1286,
4964 
            MHRESP               => xhdl1287,
4965 
            M0GATEDHADDR         => m0s9GatedHADDR,
4966 
            M0GATEDHMASTLOCK     => m0s9GatedHMASTLOCK,
4967 
            M0GATEDHSIZE         => m0s9GatedHSIZE,
4968 
            M0GATEDHTRANS        => m0s9GatedHTRANS,
4969 
            M0GATEDHWRITE        => m0s9GatedHWRITE,
4970 
            M1GATEDHADDR         => m1s9GatedHADDR,
4971 
            M1GATEDHMASTLOCK     => m1s9GatedHMASTLOCK,
4972 
            M1GATEDHSIZE         => m1s9GatedHSIZE,
4973 
            M1GATEDHTRANS        => m1s9GatedHTRANS,
4974 
            M1GATEDHWRITE        => m1s9GatedHWRITE,
4975 
            M2GATEDHADDR         => m2s9GatedHADDR,
4976 
            M2GATEDHMASTLOCK     => m2s9GatedHMASTLOCK,
4977 
            M2GATEDHSIZE         => m2s9GatedHSIZE,
4978 
            M2GATEDHTRANS        => m2s9GatedHTRANS,
4979 
            M2GATEDHWRITE        => m2s9GatedHWRITE,
4980 
            M3GATEDHADDR         => m3s9GatedHADDR,
4981 
            M3GATEDHMASTLOCK     => m3s9GatedHMASTLOCK,
4982 
            M3GATEDHSIZE         => m3s9GatedHSIZE,
4983 
            M3GATEDHTRANS        => m3s9GatedHTRANS,
4984 
            M3GATEDHWRITE        => m3s9GatedHWRITE,
4985 
            HWDATA_M0            => HWDATA_M0S9,
4986 
            HWDATA_M1            => HWDATA_M1S9,
4987 
            HWDATA_M2            => HWDATA_M2S9,
4988 
            HWDATA_M3            => HWDATA_M3S9
4989 
        );
4990 
 
4991 
 
4992 
    xhdl1288 <= (m3s10AddrSel_int & m2s10AddrSel_int & m1s10AddrSel_int & m0s10AddrSel_int);
4993 
    xhdl1289 <= (m3s10DataSel_int & m2s10DataSel_int & m1s10DataSel_int & m0s10DataSel_int);
4994 
    xhdl1290 <= (m3s10PrevDataSlaveReady & m2s10PrevDataSlaveReady & m1s10PrevDataSlaveReady & m0s10PrevDataSlaveReady);
4995 
    (s10m3AddrReady, s10m2AddrReady, s10m1AddrReady, s10m0AddrReady) <= xhdl1291;
4996 
    (s10m3DataReady, s10m2DataReady, s10m1DataReady, s10m0DataReady) <= xhdl1292;
4997 
    (s10m3HResp, s10m2HResp, s10m1HResp, s10m0HResp) <= xhdl1293;
4998 
    slavestage_10 : COREAHBLITE_SLAVESTAGE
4999 
                generic map(SYNC_RESET => SYNC_RESET)
5000 
        port map (
5001 
            HCLK                 => HCLK,
5002 
            HRESETN              => HRESETN,
5003 
            HREADYOUT            => INT_HREADYOUT_S10,
5004 
            HRESP                => INT_HRESP_S10,
5005 
            HSEL                 => HSEL_S10_xhdl59,
5006 
            HADDR                => HADDR_S10_xhdl2,
5007 
            HSIZE                => HSIZE_S10_xhdl76,
5008 
            HTRANS               => HTRANS_S10_xhdl93,
5009 
            HWRITE               => HWRITE_S10_xhdl127,
5010 
            HWDATA               => HWDATA_S10_xhdl110,
5011 
            HREADY_S             => HREADY_S10_xhdl40,
5012 
            HMASTLOCK            => HMASTLOCK_S10_xhdl19,
5013 
            MADDRSEL             => xhdl1288,
5014 
            MDATASEL             => xhdl1289,
5015 
            MPREVDATASLAVEREADY  => xhdl1290,
5016 
            MADDRREADY           => xhdl1291,
5017 
            MDATAREADY           => xhdl1292,
5018 
            MHRESP               => xhdl1293,
5019 
            M0GATEDHADDR         => m0s10GatedHADDR,
5020 
            M0GATEDHMASTLOCK     => m0s10GatedHMASTLOCK,
5021 
            M0GATEDHSIZE         => m0s10GatedHSIZE,
5022 
            M0GATEDHTRANS        => m0s10GatedHTRANS,
5023 
            M0GATEDHWRITE        => m0s10GatedHWRITE,
5024 
            M1GATEDHADDR         => m1s10GatedHADDR,
5025 
            M1GATEDHMASTLOCK     => m1s10GatedHMASTLOCK,
5026 
            M1GATEDHSIZE         => m1s10GatedHSIZE,
5027 
            M1GATEDHTRANS        => m1s10GatedHTRANS,
5028 
            M1GATEDHWRITE        => m1s10GatedHWRITE,
5029 
            M2GATEDHADDR         => m2s10GatedHADDR,
5030 
            M2GATEDHMASTLOCK     => m2s10GatedHMASTLOCK,
5031 
            M2GATEDHSIZE         => m2s10GatedHSIZE,
5032 
            M2GATEDHTRANS        => m2s10GatedHTRANS,
5033 
            M2GATEDHWRITE        => m2s10GatedHWRITE,
5034 
            M3GATEDHADDR         => m3s10GatedHADDR,
5035 
            M3GATEDHMASTLOCK     => m3s10GatedHMASTLOCK,
5036 
            M3GATEDHSIZE         => m3s10GatedHSIZE,
5037 
            M3GATEDHTRANS        => m3s10GatedHTRANS,
5038 
            M3GATEDHWRITE        => m3s10GatedHWRITE,
5039 
            HWDATA_M0            => HWDATA_M0S10,
5040 
            HWDATA_M1            => HWDATA_M1S10,
5041 
            HWDATA_M2            => HWDATA_M2S10,
5042 
            HWDATA_M3            => HWDATA_M3S10
5043 
        );
5044 
 
5045 
 
5046 
    xhdl1294 <= (m3s11AddrSel_int & m2s11AddrSel_int & m1s11AddrSel_int & m0s11AddrSel_int);
5047 
    xhdl1295 <= (m3s11DataSel_int & m2s11DataSel_int & m1s11DataSel_int & m0s11DataSel_int);
5048 
    xhdl1296 <= (m3s11PrevDataSlaveReady & m2s11PrevDataSlaveReady & m1s11PrevDataSlaveReady & m0s11PrevDataSlaveReady);
5049 
    (s11m3AddrReady, s11m2AddrReady, s11m1AddrReady, s11m0AddrReady) <= xhdl1297;
5050 
    (s11m3DataReady, s11m2DataReady, s11m1DataReady, s11m0DataReady) <= xhdl1298;
5051 
    (s11m3HResp, s11m2HResp, s11m1HResp, s11m0HResp) <= xhdl1299;
5052 
    slavestage_11 : COREAHBLITE_SLAVESTAGE
5053 
                generic map(SYNC_RESET => SYNC_RESET)
5054 
        port map (
5055 
            HCLK                 => HCLK,
5056 
            HRESETN              => HRESETN,
5057 
            HREADYOUT            => INT_HREADYOUT_S11,
5058 
            HRESP                => INT_HRESP_S11,
5059 
            HSEL                 => HSEL_S11_xhdl60,
5060 
            HADDR                => HADDR_S11_xhdl3,
5061 
            HSIZE                => HSIZE_S11_xhdl77,
5062 
            HTRANS               => HTRANS_S11_xhdl94,
5063 
            HWRITE               => HWRITE_S11_xhdl128,
5064 
            HWDATA               => HWDATA_S11_xhdl111,
5065 
            HREADY_S             => HREADY_S11_xhdl41,
5066 
            HMASTLOCK            => HMASTLOCK_S11_xhdl20,
5067 
            MADDRSEL             => xhdl1294,
5068 
            MDATASEL             => xhdl1295,
5069 
            MPREVDATASLAVEREADY  => xhdl1296,
5070 
            MADDRREADY           => xhdl1297,
5071 
            MDATAREADY           => xhdl1298,
5072 
            MHRESP               => xhdl1299,
5073 
            M0GATEDHADDR         => m0s11GatedHADDR,
5074 
            M0GATEDHMASTLOCK     => m0s11GatedHMASTLOCK,
5075 
            M0GATEDHSIZE         => m0s11GatedHSIZE,
5076 
            M0GATEDHTRANS        => m0s11GatedHTRANS,
5077 
            M0GATEDHWRITE        => m0s11GatedHWRITE,
5078 
            M1GATEDHADDR         => m1s11GatedHADDR,
5079 
            M1GATEDHMASTLOCK     => m1s11GatedHMASTLOCK,
5080 
            M1GATEDHSIZE         => m1s11GatedHSIZE,
5081 
            M1GATEDHTRANS        => m1s11GatedHTRANS,
5082 
            M1GATEDHWRITE        => m1s11GatedHWRITE,
5083 
            M2GATEDHADDR         => m2s11GatedHADDR,
5084 
            M2GATEDHMASTLOCK     => m2s11GatedHMASTLOCK,
5085 
            M2GATEDHSIZE         => m2s11GatedHSIZE,
5086 
            M2GATEDHTRANS        => m2s11GatedHTRANS,
5087 
            M2GATEDHWRITE        => m2s11GatedHWRITE,
5088 
            M3GATEDHADDR         => m3s11GatedHADDR,
5089 
            M3GATEDHMASTLOCK     => m3s11GatedHMASTLOCK,
5090 
            M3GATEDHSIZE         => m3s11GatedHSIZE,
5091 
            M3GATEDHTRANS        => m3s11GatedHTRANS,
5092 
            M3GATEDHWRITE        => m3s11GatedHWRITE,
5093 
            HWDATA_M0            => HWDATA_M0S11,
5094 
            HWDATA_M1            => HWDATA_M1S11,
5095 
            HWDATA_M2            => HWDATA_M2S11,
5096 
            HWDATA_M3            => HWDATA_M3S11
5097 
        );
5098 
 
5099 
 
5100 
    xhdl1300 <= (m3s12AddrSel_int & m2s12AddrSel_int & m1s12AddrSel_int & m0s12AddrSel_int);
5101 
    xhdl1301 <= (m3s12DataSel_int & m2s12DataSel_int & m1s12DataSel_int & m0s12DataSel_int);
5102 
    xhdl1302 <= (m3s12PrevDataSlaveReady & m2s12PrevDataSlaveReady & m1s12PrevDataSlaveReady & m0s12PrevDataSlaveReady);
5103 
    (s12m3AddrReady, s12m2AddrReady, s12m1AddrReady, s12m0AddrReady) <= xhdl1303;
5104 
    (s12m3DataReady, s12m2DataReady, s12m1DataReady, s12m0DataReady) <= xhdl1304;
5105 
    (s12m3HResp, s12m2HResp, s12m1HResp, s12m0HResp) <= xhdl1305;
5106 
    slavestage_12 : COREAHBLITE_SLAVESTAGE
5107 
                generic map(SYNC_RESET => SYNC_RESET)
5108 
        port map (
5109 
            HCLK                 => HCLK,
5110 
            HRESETN              => HRESETN,
5111 
            HREADYOUT            => INT_HREADYOUT_S12,
5112 
            HRESP                => INT_HRESP_S12,
5113 
            HSEL                 => HSEL_S12_xhdl61,
5114 
            HADDR                => HADDR_S12_xhdl4,
5115 
            HSIZE                => HSIZE_S12_xhdl78,
5116 
            HTRANS               => HTRANS_S12_xhdl95,
5117 
            HWRITE               => HWRITE_S12_xhdl129,
5118 
            HWDATA               => HWDATA_S12_xhdl112,
5119 
            HREADY_S             => HREADY_S12_xhdl42,
5120 
            HMASTLOCK            => HMASTLOCK_S12_xhdl21,
5121 
            MADDRSEL             => xhdl1300,
5122 
            MDATASEL             => xhdl1301,
5123 
            MPREVDATASLAVEREADY  => xhdl1302,
5124 
            MADDRREADY           => xhdl1303,
5125 
            MDATAREADY           => xhdl1304,
5126 
            MHRESP               => xhdl1305,
5127 
            M0GATEDHADDR         => m0s12GatedHADDR,
5128 
            M0GATEDHMASTLOCK     => m0s12GatedHMASTLOCK,
5129 
            M0GATEDHSIZE         => m0s12GatedHSIZE,
5130 
            M0GATEDHTRANS        => m0s12GatedHTRANS,
5131 
            M0GATEDHWRITE        => m0s12GatedHWRITE,
5132 
            M1GATEDHADDR         => m1s12GatedHADDR,
5133 
            M1GATEDHMASTLOCK     => m1s12GatedHMASTLOCK,
5134 
            M1GATEDHSIZE         => m1s12GatedHSIZE,
5135 
            M1GATEDHTRANS        => m1s12GatedHTRANS,
5136 
            M1GATEDHWRITE        => m1s12GatedHWRITE,
5137 
            M2GATEDHADDR         => m2s12GatedHADDR,
5138 
            M2GATEDHMASTLOCK     => m2s12GatedHMASTLOCK,
5139 
            M2GATEDHSIZE         => m2s12GatedHSIZE,
5140 
            M2GATEDHTRANS        => m2s12GatedHTRANS,
5141 
            M2GATEDHWRITE        => m2s12GatedHWRITE,
5142 
            M3GATEDHADDR         => m3s12GatedHADDR,
5143 
            M3GATEDHMASTLOCK     => m3s12GatedHMASTLOCK,
5144 
            M3GATEDHSIZE         => m3s12GatedHSIZE,
5145 
            M3GATEDHTRANS        => m3s12GatedHTRANS,
5146 
            M3GATEDHWRITE        => m3s12GatedHWRITE,
5147 
            HWDATA_M0            => HWDATA_M0S12,
5148 
            HWDATA_M1            => HWDATA_M1S12,
5149 
            HWDATA_M2            => HWDATA_M2S12,
5150 
            HWDATA_M3            => HWDATA_M3S12
5151 
        );
5152 
 
5153 
 
5154 
    xhdl1306 <= (m3s13AddrSel_int & m2s13AddrSel_int & m1s13AddrSel_int & m0s13AddrSel_int);
5155 
    xhdl1307 <= (m3s13DataSel_int & m2s13DataSel_int & m1s13DataSel_int & m0s13DataSel_int);
5156 
    xhdl1308 <= (m3s13PrevDataSlaveReady & m2s13PrevDataSlaveReady & m1s13PrevDataSlaveReady & m0s13PrevDataSlaveReady);
5157 
    (s13m3AddrReady, s13m2AddrReady, s13m1AddrReady, s13m0AddrReady) <= xhdl1309;
5158 
    (s13m3DataReady, s13m2DataReady, s13m1DataReady, s13m0DataReady) <= xhdl1310;
5159 
    (s13m3HResp, s13m2HResp, s13m1HResp, s13m0HResp) <= xhdl1311;
5160 
    slavestage_13 : COREAHBLITE_SLAVESTAGE
5161 
                generic map(SYNC_RESET => SYNC_RESET)
5162 
        port map (
5163 
            HCLK                 => HCLK,
5164 
            HRESETN              => HRESETN,
5165 
            HREADYOUT            => INT_HREADYOUT_S13,
5166 
            HRESP                => INT_HRESP_S13,
5167 
            HSEL                 => HSEL_S13_xhdl62,
5168 
            HADDR                => HADDR_S13_xhdl5,
5169 
            HSIZE                => HSIZE_S13_xhdl79,
5170 
            HTRANS               => HTRANS_S13_xhdl96,
5171 
            HWRITE               => HWRITE_S13_xhdl130,
5172 
            HWDATA               => HWDATA_S13_xhdl113,
5173 
            HREADY_S             => HREADY_S13_xhdl43,
5174 
            HMASTLOCK            => HMASTLOCK_S13_xhdl22,
5175 
            MADDRSEL             => xhdl1306,
5176 
            MDATASEL             => xhdl1307,
5177 
            MPREVDATASLAVEREADY  => xhdl1308,
5178 
            MADDRREADY           => xhdl1309,
5179 
            MDATAREADY           => xhdl1310,
5180 
            MHRESP               => xhdl1311,
5181 
            M0GATEDHADDR         => m0s13GatedHADDR,
5182 
            M0GATEDHMASTLOCK     => m0s13GatedHMASTLOCK,
5183 
            M0GATEDHSIZE         => m0s13GatedHSIZE,
5184 
            M0GATEDHTRANS        => m0s13GatedHTRANS,
5185 
            M0GATEDHWRITE        => m0s13GatedHWRITE,
5186 
            M1GATEDHADDR         => m1s13GatedHADDR,
5187 
            M1GATEDHMASTLOCK     => m1s13GatedHMASTLOCK,
5188 
            M1GATEDHSIZE         => m1s13GatedHSIZE,
5189 
            M1GATEDHTRANS        => m1s13GatedHTRANS,
5190 
            M1GATEDHWRITE        => m1s13GatedHWRITE,
5191 
            M2GATEDHADDR         => m2s13GatedHADDR,
5192 
            M2GATEDHMASTLOCK     => m2s13GatedHMASTLOCK,
5193 
            M2GATEDHSIZE         => m2s13GatedHSIZE,
5194 
            M2GATEDHTRANS        => m2s13GatedHTRANS,
5195 
            M2GATEDHWRITE        => m2s13GatedHWRITE,
5196 
            M3GATEDHADDR         => m3s13GatedHADDR,
5197 
            M3GATEDHMASTLOCK     => m3s13GatedHMASTLOCK,
5198 
            M3GATEDHSIZE         => m3s13GatedHSIZE,
5199 
            M3GATEDHTRANS        => m3s13GatedHTRANS,
5200 
            M3GATEDHWRITE        => m3s13GatedHWRITE,
5201 
            HWDATA_M0            => HWDATA_M0S13,
5202 
            HWDATA_M1            => HWDATA_M1S13,
5203 
            HWDATA_M2            => HWDATA_M2S13,
5204 
            HWDATA_M3            => HWDATA_M3S13
5205 
        );
5206 
 
5207 
 
5208 
    xhdl1312 <= (m3s14AddrSel_int & m2s14AddrSel_int & m1s14AddrSel_int & m0s14AddrSel_int);
5209 
    xhdl1313 <= (m3s14DataSel_int & m2s14DataSel_int & m1s14DataSel_int & m0s14DataSel_int);
5210 
    xhdl1314 <= (m3s14PrevDataSlaveReady & m2s14PrevDataSlaveReady & m1s14PrevDataSlaveReady & m0s14PrevDataSlaveReady);
5211 
    (s14m3AddrReady, s14m2AddrReady, s14m1AddrReady, s14m0AddrReady) <= xhdl1315;
5212 
    (s14m3DataReady, s14m2DataReady, s14m1DataReady, s14m0DataReady) <= xhdl1316;
5213 
    (s14m3HResp, s14m2HResp, s14m1HResp, s14m0HResp) <= xhdl1317;
5214 
    slavestage_14 : COREAHBLITE_SLAVESTAGE
5215 
                generic map(SYNC_RESET => SYNC_RESET)
5216 
        port map (
5217 
            HCLK                 => HCLK,
5218 
            HRESETN              => HRESETN,
5219 
            HREADYOUT            => INT_HREADYOUT_S14,
5220 
            HRESP                => INT_HRESP_S14,
5221 
            HSEL                 => HSEL_S14_xhdl63,
5222 
            HADDR                => HADDR_S14_xhdl6,
5223 
            HSIZE                => HSIZE_S14_xhdl80,
5224 
            HTRANS               => HTRANS_S14_xhdl97,
5225 
            HWRITE               => HWRITE_S14_xhdl131,
5226 
            HWDATA               => HWDATA_S14_xhdl114,
5227 
            HREADY_S             => HREADY_S14_xhdl44,
5228 
            HMASTLOCK            => HMASTLOCK_S14_xhdl23,
5229 
            MADDRSEL             => xhdl1312,
5230 
            MDATASEL             => xhdl1313,
5231 
            MPREVDATASLAVEREADY  => xhdl1314,
5232 
            MADDRREADY           => xhdl1315,
5233 
            MDATAREADY           => xhdl1316,
5234 
            MHRESP               => xhdl1317,
5235 
            M0GATEDHADDR         => m0s14GatedHADDR,
5236 
            M0GATEDHMASTLOCK     => m0s14GatedHMASTLOCK,
5237 
            M0GATEDHSIZE         => m0s14GatedHSIZE,
5238 
            M0GATEDHTRANS        => m0s14GatedHTRANS,
5239 
            M0GATEDHWRITE        => m0s14GatedHWRITE,
5240 
            M1GATEDHADDR         => m1s14GatedHADDR,
5241 
            M1GATEDHMASTLOCK     => m1s14GatedHMASTLOCK,
5242 
            M1GATEDHSIZE         => m1s14GatedHSIZE,
5243 
            M1GATEDHTRANS        => m1s14GatedHTRANS,
5244 
            M1GATEDHWRITE        => m1s14GatedHWRITE,
5245 
            M2GATEDHADDR         => m2s14GatedHADDR,
5246 
            M2GATEDHMASTLOCK     => m2s14GatedHMASTLOCK,
5247 
            M2GATEDHSIZE         => m2s14GatedHSIZE,
5248 
            M2GATEDHTRANS        => m2s14GatedHTRANS,
5249 
            M2GATEDHWRITE        => m2s14GatedHWRITE,
5250 
            M3GATEDHADDR         => m3s14GatedHADDR,
5251 
            M3GATEDHMASTLOCK     => m3s14GatedHMASTLOCK,
5252 
            M3GATEDHSIZE         => m3s14GatedHSIZE,
5253 
            M3GATEDHTRANS        => m3s14GatedHTRANS,
5254 
            M3GATEDHWRITE        => m3s14GatedHWRITE,
5255 
            HWDATA_M0            => HWDATA_M0S14,
5256 
            HWDATA_M1            => HWDATA_M1S14,
5257 
            HWDATA_M2            => HWDATA_M2S14,
5258 
            HWDATA_M3            => HWDATA_M3S14
5259 
        );
5260 
 
5261 
 
5262 
    xhdl1318 <= (m3s15AddrSel_int & m2s15AddrSel_int & m1s15AddrSel_int & m0s15AddrSel_int);
5263 
    xhdl1319 <= (m3s15DataSel_int & m2s15DataSel_int & m1s15DataSel_int & m0s15DataSel_int);
5264 
    xhdl1320 <= (m3s15PrevDataSlaveReady & m2s15PrevDataSlaveReady & m1s15PrevDataSlaveReady & m0s15PrevDataSlaveReady);
5265 
    (s15m3AddrReady, s15m2AddrReady, s15m1AddrReady, s15m0AddrReady) <= xhdl1321;
5266 
    (s15m3DataReady, s15m2DataReady, s15m1DataReady, s15m0DataReady) <= xhdl1322;
5267 
    (s15m3HResp, s15m2HResp, s15m1HResp, s15m0HResp) <= xhdl1323;
5268 
    slavestage_15 : COREAHBLITE_SLAVESTAGE
5269 
                generic map(SYNC_RESET => SYNC_RESET)
5270 
        port map (
5271 
            HCLK                 => HCLK,
5272 
            HRESETN              => HRESETN,
5273 
            HREADYOUT            => INT_HREADYOUT_S15,
5274 
            HRESP                => INT_HRESP_S15,
5275 
            HSEL                 => HSEL_S15_xhdl64,
5276 
            HADDR                => HADDR_S15_xhdl7,
5277 
            HSIZE                => HSIZE_S15_xhdl81,
5278 
            HTRANS               => HTRANS_S15_xhdl98,
5279 
            HWRITE               => HWRITE_S15_xhdl132,
5280 
            HWDATA               => HWDATA_S15_xhdl115,
5281 
            HREADY_S             => HREADY_S15_xhdl45,
5282 
            HMASTLOCK            => HMASTLOCK_S15_xhdl24,
5283 
            MADDRSEL             => xhdl1318,
5284 
            MDATASEL             => xhdl1319,
5285 
            MPREVDATASLAVEREADY  => xhdl1320,
5286 
            MADDRREADY           => xhdl1321,
5287 
            MDATAREADY           => xhdl1322,
5288 
            MHRESP               => xhdl1323,
5289 
            M0GATEDHADDR         => m0s15GatedHADDR,
5290 
            M0GATEDHMASTLOCK     => m0s15GatedHMASTLOCK,
5291 
            M0GATEDHSIZE         => m0s15GatedHSIZE,
5292 
            M0GATEDHTRANS        => m0s15GatedHTRANS,
5293 
            M0GATEDHWRITE        => m0s15GatedHWRITE,
5294 
            M1GATEDHADDR         => m1s15GatedHADDR,
5295 
            M1GATEDHMASTLOCK     => m1s15GatedHMASTLOCK,
5296 
            M1GATEDHSIZE         => m1s15GatedHSIZE,
5297 
            M1GATEDHTRANS        => m1s15GatedHTRANS,
5298 
            M1GATEDHWRITE        => m1s15GatedHWRITE,
5299 
            M2GATEDHADDR         => m2s15GatedHADDR,
5300 
            M2GATEDHMASTLOCK     => m2s15GatedHMASTLOCK,
5301 
            M2GATEDHSIZE         => m2s15GatedHSIZE,
5302 
            M2GATEDHTRANS        => m2s15GatedHTRANS,
5303 
            M2GATEDHWRITE        => m2s15GatedHWRITE,
5304 
            M3GATEDHADDR         => m3s15GatedHADDR,
5305 
            M3GATEDHMASTLOCK     => m3s15GatedHMASTLOCK,
5306 
            M3GATEDHSIZE         => m3s15GatedHSIZE,
5307 
            M3GATEDHTRANS        => m3s15GatedHTRANS,
5308 
            M3GATEDHWRITE        => m3s15GatedHWRITE,
5309 
            HWDATA_M0            => HWDATA_M0S15,
5310 
            HWDATA_M1            => HWDATA_M1S15,
5311 
            HWDATA_M2            => HWDATA_M2S15,
5312 
            HWDATA_M3            => HWDATA_M3S15
5313 
        );
5314 
 
5315 
 
5316 
    xhdl1324 <= (m3s16AddrSel_int & m2s16AddrSel_int & m1s16AddrSel_int & m0s16AddrSel_int);
5317 
    xhdl1325 <= (m3s16DataSel_int & m2s16DataSel_int & m1s16DataSel_int & m0s16DataSel_int);
5318 
    xhdl1326 <= (m3s16PrevDataSlaveReady & m2s16PrevDataSlaveReady & m1s16PrevDataSlaveReady & m0s16PrevDataSlaveReady);
5319 
    (s16m3AddrReady, s16m2AddrReady, s16m1AddrReady, s16m0AddrReady) <= xhdl1327;
5320 
    (s16m3DataReady, s16m2DataReady, s16m1DataReady, s16m0DataReady) <= xhdl1328;
5321 
    (s16m3HResp, s16m2HResp, s16m1HResp, s16m0HResp) <= xhdl1329;
5322 
    slavestage_16 : COREAHBLITE_SLAVESTAGE
5323 
                generic map(SYNC_RESET => SYNC_RESET)
5324 
        port map (
5325 
            HCLK                 => HCLK,
5326 
            HRESETN              => HRESETN,
5327 
            HREADYOUT            => INT_HREADYOUT_S16,
5328 
            HRESP                => INT_HRESP_S16,
5329 
            HSEL                 => HSEL_S16_xhdl73,
5330 
            HADDR                => HADDR_S16_xhdl16,
5331 
            HSIZE                => HSIZE_S16_xhdl90,
5332 
            HTRANS               => HTRANS_S16_xhdl107,
5333 
            HWRITE               => HWRITE_S16_xhdl141,
5334 
            HWDATA               => HWDATA_S16_xhdl124,
5335 
            HREADY_S             => HREADY_S16_xhdl54,
5336 
            HMASTLOCK            => HMASTLOCK_S16_xhdl33,
5337 
            MADDRSEL             => xhdl1324,
5338 
            MDATASEL             => xhdl1325,
5339 
            MPREVDATASLAVEREADY  => xhdl1326,
5340 
            MADDRREADY           => xhdl1327,
5341 
            MDATAREADY           => xhdl1328,
5342 
            MHRESP               => xhdl1329,
5343 
            M0GATEDHADDR         => m0s16GatedHADDR,
5344 
            M0GATEDHMASTLOCK     => m0s16GatedHMASTLOCK,
5345 
            M0GATEDHSIZE         => m0s16GatedHSIZE,
5346 
            M0GATEDHTRANS        => m0s16GatedHTRANS,
5347 
            M0GATEDHWRITE        => m0s16GatedHWRITE,
5348 
            M1GATEDHADDR         => m1s16GatedHADDR,
5349 
            M1GATEDHMASTLOCK     => m1s16GatedHMASTLOCK,
5350 
            M1GATEDHSIZE         => m1s16GatedHSIZE,
5351 
            M1GATEDHTRANS        => m1s16GatedHTRANS,
5352 
            M1GATEDHWRITE        => m1s16GatedHWRITE,
5353 
            M2GATEDHADDR         => m2s16GatedHADDR,
5354 
            M2GATEDHMASTLOCK     => m2s16GatedHMASTLOCK,
5355 
            M2GATEDHSIZE         => m2s16GatedHSIZE,
5356 
            M2GATEDHTRANS        => m2s16GatedHTRANS,
5357 
            M2GATEDHWRITE        => m2s16GatedHWRITE,
5358 
            M3GATEDHADDR         => m3s16GatedHADDR,
5359 
            M3GATEDHMASTLOCK     => m3s16GatedHMASTLOCK,
5360 
            M3GATEDHSIZE         => m3s16GatedHSIZE,
5361 
            M3GATEDHTRANS        => m3s16GatedHTRANS,
5362 
            M3GATEDHWRITE        => m3s16GatedHWRITE,
5363 
            HWDATA_M0            => HWDATA_M0S16,
5364 
            HWDATA_M1            => HWDATA_M1S16,
5365 
            HWDATA_M2            => HWDATA_M2S16,
5366 
            HWDATA_M3            => HWDATA_M3S16
5367 
        );
5368 
 
5369 
HREADY_M0_xhdl36 <= HREADY_M0_pre ;
5370 
HREADY_M1_xhdl37 <= HREADY_M1_pre ;
5371 
HREADY_M2_xhdl36 <= HREADY_M2_pre ;
5372 
HREADY_M3_xhdl37 <= HREADY_M3_pre ;
5373 
 
5374 
end architecture COREAHBLITE_MATRIX4X16_arch;

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