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-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2013 Actel Corporation.  All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreAHBLite slave arbiter logic for
--                              matrix (2 masters by 16 slaves)
--
--
-- SVN Revision Information:
-- SVN $Revision: 23120 $
-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $
--
--
-- *********************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COREAHBLITE_SLAVEARBITER is
    generic(SYNC_RESET    : integer := 0);
    port (
        HCLK              : in std_logic;
        HRESETN           : in std_logic;
        MADDRSEL          : in std_logic_vector(3 downto 0);
        ADDRPHEND         : in std_logic;
        M0GATEDHMASTLOCK  : in std_logic;
        M1GATEDHMASTLOCK  : in std_logic;
        M2GATEDHMASTLOCK  : in std_logic;
        M3GATEDHMASTLOCK  : in std_logic;
        MASTERADDRINPROG  : out std_logic_vector(3 downto 0)
    );
end entity COREAHBLITE_SLAVEARBITER;
 
architecture COREAHBLITE_SLAVEARBITER_arch of COREAHBLITE_SLAVEARBITER is
 
constant M0EXTEND           : std_logic_vector(3 downto 0) := "0000";
constant M0DONE             : std_logic_vector(3 downto 0) := "0001";
constant M0LOCK             : std_logic_vector(3 downto 0) := "0010";
constant M0LOCKEXTEND       : std_logic_vector(3 downto 0) := "0011";
constant M1EXTEND           : std_logic_vector(3 downto 0) := "0100";
constant M1DONE             : std_logic_vector(3 downto 0) := "0101";
constant M1LOCK             : std_logic_vector(3 downto 0) := "0110";
constant M1LOCKEXTEND       : std_logic_vector(3 downto 0) := "0111";
constant M2EXTEND           : std_logic_vector(3 downto 0) := "1000";
constant M2DONE             : std_logic_vector(3 downto 0) := "1001";
constant M2LOCK             : std_logic_vector(3 downto 0) := "1010";
constant M2LOCKEXTEND       : std_logic_vector(3 downto 0) := "1011";
constant M3EXTEND           : std_logic_vector(3 downto 0) := "1100";
constant M3DONE             : std_logic_vector(3 downto 0) := "1101";
constant M3LOCK             : std_logic_vector(3 downto 0) := "1110";
constant M3LOCKEXTEND       : std_logic_vector(3 downto 0) := "1111";
 
constant MASTER_0         : std_logic_vector(3 downto 0) := "0001";
constant MASTER_1         : std_logic_vector(3 downto 0) := "0010";
constant MASTER_2         : std_logic_vector(3 downto 0) := "0100";
constant MASTER_3         : std_logic_vector(3 downto 0) := "1000";
constant MASTER_NONE      : std_logic_vector(3 downto 0) := "0000";
 
 
    signal arbRegSMNextState    : std_logic_vector(3 downto 0);
    signal arbRegSMCurrentState : std_logic_vector(3 downto 0);
    signal aresetn                : std_logic;
    signal sresetn                : std_logic;
 
begin
    aresetn <= '1' WHEN (SYNC_RESET=1) ELSE HRESETN;
    sresetn <= HRESETN WHEN (SYNC_RESET=1) ELSE '1';
 
    process (arbRegSMCurrentState,
             MADDRSEL,
             ADDRPHEND,
             M0GATEDHMASTLOCK,
             M1GATEDHMASTLOCK,
             M2GATEDHMASTLOCK,
             M3GATEDHMASTLOCK)
    begin
        MASTERADDRINPROG <= MASTER_NONE;
        case arbRegSMCurrentState is
            when M3DONE =>
                if ((MADDRSEL(0)) = '1') then
                    if (M0GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M0LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_0;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M0DONE;
                        else
                            arbRegSMNextState <= M0EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(1)) = '1') then
                    if (M1GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M1LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_1;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M1DONE;
                        else
                            arbRegSMNextState <= M1EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(2)) = '1') then
                    if (M2GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M2LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_2;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M2DONE;
                        else
                            arbRegSMNextState <= M2EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(3)) = '1') then
                    if (M3GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M3LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_3;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M3DONE;
                        else
                            arbRegSMNextState <= M3EXTEND;
                        end if;
                    end if;
                else
                    arbRegSMNextState <= M3DONE;
                end if;
            when M2DONE =>
                if ((MADDRSEL(3)) = '1') then
                    if (M3GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M3LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_3;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M3DONE;
                        else
                            arbRegSMNextState <= M3EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(0)) = '1') then
                    if (M0GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M0LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_0;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M0DONE;
                        else
                            arbRegSMNextState <= M0EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(1)) = '1') then
                    if (M1GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M1LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_1;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M1DONE;
                        else
                            arbRegSMNextState <= M1EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(2)) = '1') then
                    if (M2GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M2LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_2;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M2DONE;
                        else
                            arbRegSMNextState <= M2EXTEND;
                        end if;
                    end if;
                else
                    arbRegSMNextState <= M2DONE;
                end if;
            when M1DONE =>
                if ((MADDRSEL(2)) = '1') then
                    if (M2GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M2LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_2;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M2DONE;
                        else
                            arbRegSMNextState <= M2EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(3)) = '1') then
                    if (M3GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M3LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_3;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M3DONE;
                        else
                            arbRegSMNextState <= M3EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(0)) = '1') then
                    if (M0GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M0LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_0;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M0DONE;
                        else
                            arbRegSMNextState <= M0EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(1)) = '1') then
                    if (M1GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M1LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_1;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M1DONE;
                        else
                            arbRegSMNextState <= M1EXTEND;
                        end if;
                    end if;
                else
                    arbRegSMNextState <= M1DONE;
                end if;
            when M0DONE =>
                if ((MADDRSEL(1)) = '1') then
                    if (M1GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M1LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_1;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M1DONE;
                        else
                            arbRegSMNextState <= M1EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(2)) = '1') then
                    if (M2GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M2LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_2;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M2DONE;
                        else
                            arbRegSMNextState <= M2EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(3)) = '1') then
                    if (M3GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M3LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_3;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M3DONE;
                        else
                            arbRegSMNextState <= M3EXTEND;
                        end if;
                    end if;
                elsif ((MADDRSEL(0)) = '1') then
                    if (M0GATEDHMASTLOCK = '1') then
                        arbRegSMNextState <= M0LOCK;
                    else
                        MASTERADDRINPROG <= MASTER_0;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M0DONE;
                        else
                            arbRegSMNextState <= M0EXTEND;
                        end if;
                    end if;
                else
                    arbRegSMNextState <= M0DONE;
                end if;
            when M0EXTEND =>
                MASTERADDRINPROG <= MASTER_0;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M0DONE;
                else
                    arbRegSMNextState <= M0EXTEND;
                end if;
            when M1EXTEND =>
                MASTERADDRINPROG <= MASTER_1;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M1DONE;
                else
                    arbRegSMNextState <= M1EXTEND;
                end if;
            when M2EXTEND =>
                MASTERADDRINPROG <= MASTER_2;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M2DONE;
                else
                    arbRegSMNextState <= M2EXTEND;
                end if;
            when M3EXTEND =>
                MASTERADDRINPROG <= MASTER_3;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M3DONE;
                else
                    arbRegSMNextState <= M3EXTEND;
                end if;
            when M0LOCK =>
                if (M0GATEDHMASTLOCK = '1') then
                    if ((MADDRSEL(0)) = '1') then
                        MASTERADDRINPROG <= MASTER_0;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M0LOCK;
                        else
                            arbRegSMNextState <= M0LOCKEXTEND;
                        end if;
                    else
                        arbRegSMNextState <= M0LOCK;
                    end if;
                else
                    arbRegSMNextState <= M0DONE;
                end if;
            when M0LOCKEXTEND =>
                MASTERADDRINPROG <= MASTER_0;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M0LOCK;
                else
                    arbRegSMNextState <= M0LOCKEXTEND;
                end if;
            when M1LOCK =>
                if (M1GATEDHMASTLOCK = '1') then
                    if ((MADDRSEL(1)) = '1') then
                        MASTERADDRINPROG <= MASTER_1;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M1LOCK;
                        else
                            arbRegSMNextState <= M1LOCKEXTEND;
                        end if;
                    else
                        arbRegSMNextState <= M1LOCK;
                    end if;
                else
                    arbRegSMNextState <= M1DONE;
                end if;
            when M1LOCKEXTEND =>
                MASTERADDRINPROG <= MASTER_1;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M1LOCK;
                else
                    arbRegSMNextState <= M1LOCKEXTEND;
                end if;
            when M2LOCK =>
                if (M2GATEDHMASTLOCK = '1') then
                    if ((MADDRSEL(2)) = '1') then
                        MASTERADDRINPROG <= MASTER_2;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M2LOCK;
                        else
                            arbRegSMNextState <= M2LOCKEXTEND;
                        end if;
                    else
                        arbRegSMNextState <= M2LOCK;
                    end if;
                else
                    arbRegSMNextState <= M2DONE;
                end if;
            when M2LOCKEXTEND =>
                MASTERADDRINPROG <= MASTER_2;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M2LOCK;
                else
                    arbRegSMNextState <= M2LOCKEXTEND;
                end if;
            when M3LOCK =>
                if (M3GATEDHMASTLOCK = '1') then
                    if ((MADDRSEL(3)) = '1') then
                        MASTERADDRINPROG <= MASTER_3;
                        if (ADDRPHEND = '1') then
                            arbRegSMNextState <= M3LOCK;
                        else
                            arbRegSMNextState <= M3LOCKEXTEND;
                        end if;
                    else
                        arbRegSMNextState <= M3LOCK;
                    end if;
                else
                    arbRegSMNextState <= M3DONE;
                end if;
            when M3LOCKEXTEND =>
                MASTERADDRINPROG <= MASTER_3;
                if (ADDRPHEND = '1') then
                    arbRegSMNextState <= M3LOCK;
                else
                    arbRegSMNextState <= M3LOCKEXTEND;
                end if;
 
            when others =>
                arbRegSMNextState <= M1DONE;
        end case;
    end process;
 
    process (HCLK, aresetn)
    begin
        if ((not(aresetn)) = '1') then
            arbRegSMCurrentState <= M3DONE;
        elsif (HCLK'event and HCLK = '1') then
            if ((not(sresetn)) = '1') then
                arbRegSMCurrentState <= M3DONE;
                    else
                arbRegSMCurrentState <= arbRegSMNextState;
            end if;
        end if;
    end process;
 
 
end architecture COREAHBLITE_SLAVEARBITER_arch;

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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAHBLite/] [5.3.101/] [rtl/] [vhdl/] [core/] [coreahblite_slavearbiter.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`-- ********************************************************************/`
2			`-- Actel Corporation Proprietary and Confidential`
3			`-- Copyright 2013 Actel Corporation. All rights reserved.`
4			`--`
5			`-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN`
6			`-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED`
7			`-- IN ADVANCE IN WRITING.`
8			`--`
9			`-- Description: CoreAHBLite slave arbiter logic for`
10			`-- matrix (2 masters by 16 slaves)`
11			`--`
12			`--`
13			`-- SVN Revision Information:`
14			`-- SVN $Revision: 23120 $`
15			`-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $`
16			`--`
17			`--`
18			`-- *********************************************************************/`
19			`library ieee;`
20			`use ieee.std_logic_1164.all;`
21			`use ieee.numeric_std.all;`
22			`entity COREAHBLITE_SLAVEARBITER is`
23			`generic(SYNC_RESET : integer := 0);`
24			`port (`
25			`HCLK : in std_logic;`
26			`HRESETN : in std_logic;`
27			`MADDRSEL : in std_logic_vector(3 downto 0);`
28			`ADDRPHEND : in std_logic;`
29			`M0GATEDHMASTLOCK : in std_logic;`
30			`M1GATEDHMASTLOCK : in std_logic;`
31			`M2GATEDHMASTLOCK : in std_logic;`
32			`M3GATEDHMASTLOCK : in std_logic;`
33			`MASTERADDRINPROG : out std_logic_vector(3 downto 0)`
34			`);`
35			`end entity COREAHBLITE_SLAVEARBITER;`
36
37			`architecture COREAHBLITE_SLAVEARBITER_arch of COREAHBLITE_SLAVEARBITER is`
38
39			`constant M0EXTEND : std_logic_vector(3 downto 0) := "0000";`
40			`constant M0DONE : std_logic_vector(3 downto 0) := "0001";`
41			`constant M0LOCK : std_logic_vector(3 downto 0) := "0010";`
42			`constant M0LOCKEXTEND : std_logic_vector(3 downto 0) := "0011";`
43			`constant M1EXTEND : std_logic_vector(3 downto 0) := "0100";`
44			`constant M1DONE : std_logic_vector(3 downto 0) := "0101";`
45			`constant M1LOCK : std_logic_vector(3 downto 0) := "0110";`
46			`constant M1LOCKEXTEND : std_logic_vector(3 downto 0) := "0111";`
47			`constant M2EXTEND : std_logic_vector(3 downto 0) := "1000";`
48			`constant M2DONE : std_logic_vector(3 downto 0) := "1001";`
49			`constant M2LOCK : std_logic_vector(3 downto 0) := "1010";`
50			`constant M2LOCKEXTEND : std_logic_vector(3 downto 0) := "1011";`
51			`constant M3EXTEND : std_logic_vector(3 downto 0) := "1100";`
52			`constant M3DONE : std_logic_vector(3 downto 0) := "1101";`
53			`constant M3LOCK : std_logic_vector(3 downto 0) := "1110";`
54			`constant M3LOCKEXTEND : std_logic_vector(3 downto 0) := "1111";`
55
56			`constant MASTER_0 : std_logic_vector(3 downto 0) := "0001";`
57			`constant MASTER_1 : std_logic_vector(3 downto 0) := "0010";`
58			`constant MASTER_2 : std_logic_vector(3 downto 0) := "0100";`
59			`constant MASTER_3 : std_logic_vector(3 downto 0) := "1000";`
60			`constant MASTER_NONE : std_logic_vector(3 downto 0) := "0000";`
61
62
63			`signal arbRegSMNextState : std_logic_vector(3 downto 0);`
64			`signal arbRegSMCurrentState : std_logic_vector(3 downto 0);`
65			`signal aresetn : std_logic;`
66			`signal sresetn : std_logic;`
67
68			`begin`
69			`aresetn <= '1' WHEN (SYNC_RESET=1) ELSE HRESETN;`
70			`sresetn <= HRESETN WHEN (SYNC_RESET=1) ELSE '1';`
71
72			`process (arbRegSMCurrentState,`
73			`MADDRSEL,`
74			`ADDRPHEND,`
75			`M0GATEDHMASTLOCK,`
76			`M1GATEDHMASTLOCK,`
77			`M2GATEDHMASTLOCK,`
78			`M3GATEDHMASTLOCK)`
79			`begin`
80			`MASTERADDRINPROG <= MASTER_NONE;`
81			`case arbRegSMCurrentState is`
82			`when M3DONE =>`
83			`if ((MADDRSEL(0)) = '1') then`
84			`if (M0GATEDHMASTLOCK = '1') then`
85			`arbRegSMNextState <= M0LOCK;`
86			`else`
87			`MASTERADDRINPROG <= MASTER_0;`
88			`if (ADDRPHEND = '1') then`
89			`arbRegSMNextState <= M0DONE;`
90			`else`
91			`arbRegSMNextState <= M0EXTEND;`
92			`end if;`
93			`end if;`
94			`elsif ((MADDRSEL(1)) = '1') then`
95			`if (M1GATEDHMASTLOCK = '1') then`
96			`arbRegSMNextState <= M1LOCK;`
97			`else`
98			`MASTERADDRINPROG <= MASTER_1;`
99			`if (ADDRPHEND = '1') then`
100			`arbRegSMNextState <= M1DONE;`
101			`else`
102			`arbRegSMNextState <= M1EXTEND;`
103			`end if;`
104			`end if;`
105			`elsif ((MADDRSEL(2)) = '1') then`
106			`if (M2GATEDHMASTLOCK = '1') then`
107			`arbRegSMNextState <= M2LOCK;`
108			`else`
109			`MASTERADDRINPROG <= MASTER_2;`
110			`if (ADDRPHEND = '1') then`
111			`arbRegSMNextState <= M2DONE;`
112			`else`
113			`arbRegSMNextState <= M2EXTEND;`
114			`end if;`
115			`end if;`
116			`elsif ((MADDRSEL(3)) = '1') then`
117			`if (M3GATEDHMASTLOCK = '1') then`
118			`arbRegSMNextState <= M3LOCK;`
119			`else`
120			`MASTERADDRINPROG <= MASTER_3;`
121			`if (ADDRPHEND = '1') then`
122			`arbRegSMNextState <= M3DONE;`
123			`else`
124			`arbRegSMNextState <= M3EXTEND;`
125			`end if;`
126			`end if;`
127			`else`
128			`arbRegSMNextState <= M3DONE;`
129			`end if;`
130			`when M2DONE =>`
131			`if ((MADDRSEL(3)) = '1') then`
132			`if (M3GATEDHMASTLOCK = '1') then`
133			`arbRegSMNextState <= M3LOCK;`
134			`else`
135			`MASTERADDRINPROG <= MASTER_3;`
136			`if (ADDRPHEND = '1') then`
137			`arbRegSMNextState <= M3DONE;`
138			`else`
139			`arbRegSMNextState <= M3EXTEND;`
140			`end if;`
141			`end if;`
142			`elsif ((MADDRSEL(0)) = '1') then`
143			`if (M0GATEDHMASTLOCK = '1') then`
144			`arbRegSMNextState <= M0LOCK;`
145			`else`
146			`MASTERADDRINPROG <= MASTER_0;`
147			`if (ADDRPHEND = '1') then`
148			`arbRegSMNextState <= M0DONE;`
149			`else`
150			`arbRegSMNextState <= M0EXTEND;`
151			`end if;`
152			`end if;`
153			`elsif ((MADDRSEL(1)) = '1') then`
154			`if (M1GATEDHMASTLOCK = '1') then`
155			`arbRegSMNextState <= M1LOCK;`
156			`else`
157			`MASTERADDRINPROG <= MASTER_1;`
158			`if (ADDRPHEND = '1') then`
159			`arbRegSMNextState <= M1DONE;`
160			`else`
161			`arbRegSMNextState <= M1EXTEND;`
162			`end if;`
163			`end if;`
164			`elsif ((MADDRSEL(2)) = '1') then`
165			`if (M2GATEDHMASTLOCK = '1') then`
166			`arbRegSMNextState <= M2LOCK;`
167			`else`
168			`MASTERADDRINPROG <= MASTER_2;`
169			`if (ADDRPHEND = '1') then`
170			`arbRegSMNextState <= M2DONE;`
171			`else`
172			`arbRegSMNextState <= M2EXTEND;`
173			`end if;`
174			`end if;`
175			`else`
176			`arbRegSMNextState <= M2DONE;`
177			`end if;`
178			`when M1DONE =>`
179			`if ((MADDRSEL(2)) = '1') then`
180			`if (M2GATEDHMASTLOCK = '1') then`
181			`arbRegSMNextState <= M2LOCK;`
182			`else`
183			`MASTERADDRINPROG <= MASTER_2;`
184			`if (ADDRPHEND = '1') then`
185			`arbRegSMNextState <= M2DONE;`
186			`else`
187			`arbRegSMNextState <= M2EXTEND;`
188			`end if;`
189			`end if;`
190			`elsif ((MADDRSEL(3)) = '1') then`
191			`if (M3GATEDHMASTLOCK = '1') then`
192			`arbRegSMNextState <= M3LOCK;`
193			`else`
194			`MASTERADDRINPROG <= MASTER_3;`
195			`if (ADDRPHEND = '1') then`
196			`arbRegSMNextState <= M3DONE;`
197			`else`
198			`arbRegSMNextState <= M3EXTEND;`
199			`end if;`
200			`end if;`
201			`elsif ((MADDRSEL(0)) = '1') then`
202			`if (M0GATEDHMASTLOCK = '1') then`
203			`arbRegSMNextState <= M0LOCK;`
204			`else`
205			`MASTERADDRINPROG <= MASTER_0;`
206			`if (ADDRPHEND = '1') then`
207			`arbRegSMNextState <= M0DONE;`
208			`else`
209			`arbRegSMNextState <= M0EXTEND;`
210			`end if;`
211			`end if;`
212			`elsif ((MADDRSEL(1)) = '1') then`
213			`if (M1GATEDHMASTLOCK = '1') then`
214			`arbRegSMNextState <= M1LOCK;`
215			`else`
216			`MASTERADDRINPROG <= MASTER_1;`
217			`if (ADDRPHEND = '1') then`
218			`arbRegSMNextState <= M1DONE;`
219			`else`
220			`arbRegSMNextState <= M1EXTEND;`
221			`end if;`
222			`end if;`
223			`else`
224			`arbRegSMNextState <= M1DONE;`
225			`end if;`
226			`when M0DONE =>`
227			`if ((MADDRSEL(1)) = '1') then`
228			`if (M1GATEDHMASTLOCK = '1') then`
229			`arbRegSMNextState <= M1LOCK;`
230			`else`
231			`MASTERADDRINPROG <= MASTER_1;`
232			`if (ADDRPHEND = '1') then`
233			`arbRegSMNextState <= M1DONE;`
234			`else`
235			`arbRegSMNextState <= M1EXTEND;`
236			`end if;`
237			`end if;`
238			`elsif ((MADDRSEL(2)) = '1') then`
239			`if (M2GATEDHMASTLOCK = '1') then`
240			`arbRegSMNextState <= M2LOCK;`
241			`else`
242			`MASTERADDRINPROG <= MASTER_2;`
243			`if (ADDRPHEND = '1') then`
244			`arbRegSMNextState <= M2DONE;`
245			`else`
246			`arbRegSMNextState <= M2EXTEND;`
247			`end if;`
248			`end if;`
249			`elsif ((MADDRSEL(3)) = '1') then`
250			`if (M3GATEDHMASTLOCK = '1') then`
251			`arbRegSMNextState <= M3LOCK;`
252			`else`
253			`MASTERADDRINPROG <= MASTER_3;`
254			`if (ADDRPHEND = '1') then`
255			`arbRegSMNextState <= M3DONE;`
256			`else`
257			`arbRegSMNextState <= M3EXTEND;`
258			`end if;`
259			`end if;`
260			`elsif ((MADDRSEL(0)) = '1') then`
261			`if (M0GATEDHMASTLOCK = '1') then`
262			`arbRegSMNextState <= M0LOCK;`
263			`else`
264			`MASTERADDRINPROG <= MASTER_0;`
265			`if (ADDRPHEND = '1') then`
266			`arbRegSMNextState <= M0DONE;`
267			`else`
268			`arbRegSMNextState <= M0EXTEND;`
269			`end if;`
270			`end if;`
271			`else`
272			`arbRegSMNextState <= M0DONE;`
273			`end if;`
274			`when M0EXTEND =>`
275			`MASTERADDRINPROG <= MASTER_0;`
276			`if (ADDRPHEND = '1') then`
277			`arbRegSMNextState <= M0DONE;`
278			`else`
279			`arbRegSMNextState <= M0EXTEND;`
280			`end if;`
281			`when M1EXTEND =>`
282			`MASTERADDRINPROG <= MASTER_1;`
283			`if (ADDRPHEND = '1') then`
284			`arbRegSMNextState <= M1DONE;`
285			`else`
286			`arbRegSMNextState <= M1EXTEND;`
287			`end if;`
288			`when M2EXTEND =>`
289			`MASTERADDRINPROG <= MASTER_2;`
290			`if (ADDRPHEND = '1') then`
291			`arbRegSMNextState <= M2DONE;`
292			`else`
293			`arbRegSMNextState <= M2EXTEND;`
294			`end if;`
295			`when M3EXTEND =>`
296			`MASTERADDRINPROG <= MASTER_3;`
297			`if (ADDRPHEND = '1') then`
298			`arbRegSMNextState <= M3DONE;`
299			`else`
300			`arbRegSMNextState <= M3EXTEND;`
301			`end if;`
302			`when M0LOCK =>`
303			`if (M0GATEDHMASTLOCK = '1') then`
304			`if ((MADDRSEL(0)) = '1') then`
305			`MASTERADDRINPROG <= MASTER_0;`
306			`if (ADDRPHEND = '1') then`
307			`arbRegSMNextState <= M0LOCK;`
308			`else`
309			`arbRegSMNextState <= M0LOCKEXTEND;`
310			`end if;`
311			`else`
312			`arbRegSMNextState <= M0LOCK;`
313			`end if;`
314			`else`
315			`arbRegSMNextState <= M0DONE;`
316			`end if;`
317			`when M0LOCKEXTEND =>`
318			`MASTERADDRINPROG <= MASTER_0;`
319			`if (ADDRPHEND = '1') then`
320			`arbRegSMNextState <= M0LOCK;`
321			`else`
322			`arbRegSMNextState <= M0LOCKEXTEND;`
323			`end if;`
324			`when M1LOCK =>`
325			`if (M1GATEDHMASTLOCK = '1') then`
326			`if ((MADDRSEL(1)) = '1') then`
327			`MASTERADDRINPROG <= MASTER_1;`
328			`if (ADDRPHEND = '1') then`
329			`arbRegSMNextState <= M1LOCK;`
330			`else`
331			`arbRegSMNextState <= M1LOCKEXTEND;`
332			`end if;`
333			`else`
334			`arbRegSMNextState <= M1LOCK;`
335			`end if;`
336			`else`
337			`arbRegSMNextState <= M1DONE;`
338			`end if;`
339			`when M1LOCKEXTEND =>`
340			`MASTERADDRINPROG <= MASTER_1;`
341			`if (ADDRPHEND = '1') then`
342			`arbRegSMNextState <= M1LOCK;`
343			`else`
344			`arbRegSMNextState <= M1LOCKEXTEND;`
345			`end if;`
346			`when M2LOCK =>`
347			`if (M2GATEDHMASTLOCK = '1') then`
348			`if ((MADDRSEL(2)) = '1') then`
349			`MASTERADDRINPROG <= MASTER_2;`
350			`if (ADDRPHEND = '1') then`
351			`arbRegSMNextState <= M2LOCK;`
352			`else`
353			`arbRegSMNextState <= M2LOCKEXTEND;`
354			`end if;`
355			`else`
356			`arbRegSMNextState <= M2LOCK;`
357			`end if;`
358			`else`
359			`arbRegSMNextState <= M2DONE;`
360			`end if;`
361			`when M2LOCKEXTEND =>`
362			`MASTERADDRINPROG <= MASTER_2;`
363			`if (ADDRPHEND = '1') then`
364			`arbRegSMNextState <= M2LOCK;`
365			`else`
366			`arbRegSMNextState <= M2LOCKEXTEND;`
367			`end if;`
368			`when M3LOCK =>`
369			`if (M3GATEDHMASTLOCK = '1') then`
370			`if ((MADDRSEL(3)) = '1') then`
371			`MASTERADDRINPROG <= MASTER_3;`
372			`if (ADDRPHEND = '1') then`
373			`arbRegSMNextState <= M3LOCK;`
374			`else`
375			`arbRegSMNextState <= M3LOCKEXTEND;`
376			`end if;`
377			`else`
378			`arbRegSMNextState <= M3LOCK;`
379			`end if;`
380			`else`
381			`arbRegSMNextState <= M3DONE;`
382			`end if;`
383			`when M3LOCKEXTEND =>`
384			`MASTERADDRINPROG <= MASTER_3;`
385			`if (ADDRPHEND = '1') then`
386			`arbRegSMNextState <= M3LOCK;`
387			`else`
388			`arbRegSMNextState <= M3LOCKEXTEND;`
389			`end if;`
390
391			`when others =>`
392			`arbRegSMNextState <= M1DONE;`
393			`end case;`
394			`end process;`
395
396			`process (HCLK, aresetn)`
397			`begin`
398			`if ((not(aresetn)) = '1') then`
399			`arbRegSMCurrentState <= M3DONE;`
400			`elsif (HCLK'event and HCLK = '1') then`
401			`if ((not(sresetn)) = '1') then`
402			`arbRegSMCurrentState <= M3DONE;`
403			`else`
404			`arbRegSMCurrentState <= arbRegSMNextState;`
405			`end if;`
406			`end if;`
407			`end process;`
408
409
410			`end architecture COREAHBLITE_SLAVEARBITER_arch;`